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Mon, 28 Oct 2024 08:19:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF32n/Q6nOsPYGSMYib7uRTokRjrMOygZkCo4T68MpHJhsbp8sj+DkGdRAHHDpdqSgn3KKp3Q== X-Received: by 2002:a05:6000:1a48:b0:37d:3e5b:feac with SMTP id ffacd0b85a97d-38061213262mr6609645f8f.59.1730128741375; Mon, 28 Oct 2024 08:19:01 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH 01/14] target/i386: use tcg_gen_ext_tl when applicable Date: Mon, 28 Oct 2024 16:18:38 +0100 Message-ID: <20241028151851.376355-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241028151851.376355-1-pbonzini@redhat.com> References: <20241028151851.376355-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.373, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730128784745116600 Content-Type: text/plain; charset="utf-8" Prefer it to gen_ext_tl in the common case where the destination is known. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ef190416b49..dc308f31041 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -883,16 +883,16 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s= , TCGv reg) case CC_OP_SUBB ... CC_OP_SUBQ: /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ size =3D s->cc_op - CC_OP_SUBB; - gen_ext_tl(s->cc_srcT, s->cc_srcT, size, false); - gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); + tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size); + tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size); return (CCPrepare) { .cond =3D TCG_COND_LTU, .reg =3D s->cc_srcT, .reg2 =3D cpu_cc_src, .use_reg2 =3D true }; =20 case CC_OP_ADDB ... CC_OP_ADDQ: /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ size =3D s->cc_op - CC_OP_ADDB; - gen_ext_tl(cpu_cc_dst, cpu_cc_dst, size, false); - gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); + tcg_gen_ext_tl(cpu_cc_dst, cpu_cc_dst, size); + tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size); return (CCPrepare) { .cond =3D TCG_COND_LTU, .reg =3D cpu_cc_dst, .reg2 =3D cpu_cc_src, .use_reg2 =3D true }; =20 @@ -1041,8 +1041,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) size =3D s->cc_op - CC_OP_SUBB; switch (jcc_op) { case JCC_BE: - gen_ext_tl(s->cc_srcT, s->cc_srcT, size, false); - gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); + tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size); + tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size); cc =3D (CCPrepare) { .cond =3D TCG_COND_LEU, .reg =3D s->cc_sr= cT, .reg2 =3D cpu_cc_src, .use_reg2 =3D true }; break; @@ -1052,8 +1052,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) case JCC_LE: cond =3D TCG_COND_LE; fast_jcc_l: - gen_ext_tl(s->cc_srcT, s->cc_srcT, size, true); - gen_ext_tl(cpu_cc_src, cpu_cc_src, size, true); + tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size | MO_SIGN); + tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size | MO_SIGN); cc =3D (CCPrepare) { .cond =3D cond, .reg =3D s->cc_srcT, .reg2 =3D cpu_cc_src, .use_reg2 =3D true }; break; --=20 2.47.0