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a="40249475" X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="40249475" X-CSE-ConnectionGUID: zeRy5jCsRgiTRHy98DzptQ== X-CSE-MsgGUID: 4DhdYU6YRJGIUeJ75BpXWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="81420953" From: Tao Su To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 5/6] target/i386: Add support for AVX10 in CPUID enumeration Date: Mon, 28 Oct 2024 10:45:11 +0800 Message-Id: <20241028024512.156724-6-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028024512.156724-1-tao1.su@linux.intel.com> References: <20241028024512.156724-1-tao1.su@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083923355116600 Content-Type: text/plain; charset="utf-8" Intel AVX10 represents the first major new vector ISA since the introduction of Intel AVX512, which will establish a common, converged vector instruction set across all Intel architectures. AVX10 enable bit is enumerated via CPUID.(EAX=3D7,ECX=3D1):EDX[bit 19]. Add the CPUID definition for AVX10 enable bit, AVX10 will be enabled automatically when using '-cpu host' and KVM advertises AVX10 to userspace. Tested-by: Xuelian Guo Signed-off-by: Tao Su --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9666dbf29c..adde98fd26 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1133,7 +1133,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx-vnni-int8", "avx-ne-convert", NULL, NULL, "amx-complex", NULL, "avx-vnni-int16", NULL, NULL, NULL, "prefetchiti", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "avx10", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, --=20 2.34.1