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a="40249465" X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="40249465" X-CSE-ConnectionGUID: qc9EuPeGRgCX/LybdGH0Og== X-CSE-MsgGUID: qpeiZ7GXRaK9A9FMNY5ntw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="81420932" From: Tao Su To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 1/6] target/i386: Add AVX512 state when AVX10 is supported Date: Mon, 28 Oct 2024 10:45:07 +0800 Message-Id: <20241028024512.156724-2-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028024512.156724-1-tao1.su@linux.intel.com> References: <20241028024512.156724-1-tao1.su@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083937115116600 Content-Type: text/plain; charset="utf-8" AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register are identical to AVX512 state regardless of the supported vector lengths. Given that some E-cores will support AVX10 but not support AVX512, add AVX512 state components to guest when AVX10 is enabled. Tested-by: Xuelian Guo Signed-off-by: Tao Su Reviewed-by: Xiaoyao Li --- target/i386/cpu.c | 14 ++++++++++++++ target/i386/cpu.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ff1af032e..d845ff5e4e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7177,6 +7177,13 @@ static void x86_cpu_reset_hold(Object *obj, ResetTyp= e type) } if (env->features[esa->feature] & esa->bits) { xcr0 |=3D 1ull << i; + continue; + } + if (i =3D=3D XSTATE_OPMASK_BIT || i =3D=3D XSTATE_ZMM_Hi256_BIT || + i =3D=3D XSTATE_Hi16_ZMM_BIT) { + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + xcr0 |=3D 1ull << i; + } } } =20 @@ -7315,6 +7322,13 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; if (env->features[esa->feature] & esa->bits) { mask |=3D (1ULL << i); + continue; + } + if (i =3D=3D XSTATE_OPMASK_BIT || i =3D=3D XSTATE_ZMM_Hi256_BIT || + i =3D=3D XSTATE_Hi16_ZMM_BIT) { + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + mask |=3D (1ULL << i); + } } } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 74886d1580..280bec701c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -972,6 +972,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8) /* PREFETCHIT0/1 Instructions */ #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) +/* Support for Advanced Vector Extensions 10 */ +#define CPUID_7_1_EDX_AVX10 (1U << 19) /* Flexible return and event delivery (FRED) */ #define CPUID_7_1_EAX_FRED (1U << 17) /* Load into IA32_KERNEL_GS_BASE (LKGS) */ --=20 2.34.1 From nobody Sat Nov 23 17:57:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730083928; cv=none; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083929092116600 Content-Type: text/plain; charset="utf-8" Introduce avx10-version property so that avx10 version can be controlled by user and cpu model. Per spec, avx10 version can never be 0, the default value of avx10-version is set to 0 to determine whether it is specified by user. Tested-by: Xuelian Guo Signed-off-by: Tao Su --- target/i386/cpu.c | 1 + target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d845ff5e4e..5b434a107a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8343,6 +8343,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), + DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 280bec701c..d845384dcd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1920,6 +1920,8 @@ typedef struct CPUArchState { uint32_t cpuid_vendor3; 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X-CSE-ConnectionGUID: LT7xDwraRKuDYemvIsLjaQ== X-CSE-MsgGUID: tWHm3ZGJQ5O5NncuS1YX+A== X-IronPort-AV: E=McAfee;i="6700,10204,11238"; a="40249469" X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="40249469" X-CSE-ConnectionGUID: S89XMHquTVGNqyoULDMzSQ== X-CSE-MsgGUID: jRwqVWzLSD2i80Z6XNC6/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="81420941" From: Tao Su To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 3/6] target/i386: Add CPUID.24 leaf for AVX10 Date: Mon, 28 Oct 2024 10:45:09 +0800 Message-Id: <20241028024512.156724-4-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028024512.156724-1-tao1.su@linux.intel.com> References: <20241028024512.156724-1-tao1.su@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083947390116600 Content-Type: text/plain; charset="utf-8" When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10 Converged Vector ISA leaf" containing fields for the version number and the supported vector bit lengths. Tested-by: Xuelian Guo Signed-off-by: Tao Su --- target/i386/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 8 ++++++++ target/i386/kvm/kvm.c | 3 ++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5b434a107a..91fae0dcb7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -898,6 +898,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo= r1, #define TCG_SGX_12_0_EAX_FEATURES 0 #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 +#define TCG_24_0_EBX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1163,6 +1164,20 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_7_2_EDX_FEATURES, }, + [FEAT_24_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [16] =3D "avx10-128", + [17] =3D "avx10-256", + [18] =3D "avx10-512", + }, + .cpuid =3D { + .eax =3D 0x24, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, + }, + .tcg_features =3D TCG_24_0_EBX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -6835,6 +6850,26 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x24: { + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + break; + } + + if (count =3D=3D 0) { + uint8_t v =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x24, + 0, R_EBX); + if (env->avx10_version && env->avx10_version < v) { + v =3D env->avx10_version; + } + + *ebx =3D env->features[FEAT_24_0_EBX] | v; + } + break; + } case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff @@ -7483,6 +7518,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); } =20 + /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); + } + /* SVM requires CPUID[0x8000000A] */ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d845384dcd..5566a13f4f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -662,6 +662,7 @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ + FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEATURE_WORDS, } FeatureWord; =20 @@ -990,6 +991,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cp= u, FeatureWord w); /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 +/* AVX10 128-bit vector support is present */ +#define CPUID_24_0_EBX_AVX10_128 (1U << 16) +/* AVX10 256-bit vector support is present */ +#define CPUID_24_0_EBX_AVX10_256 (1U << 17) +/* AVX10 512-bit vector support is present */ +#define CPUID_24_0_EBX_AVX10_512 (1U << 18) + /* RAS Features */ #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) #define CPUID_8000_0007_EBX_SUCCOR (1U << 1) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index fd9f198892..8e17942c3b 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1923,7 +1923,8 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env, case 0x7: case 0x14: case 0x1d: - case 0x1e: { + case 0x1e: + case 0x24: { uint32_t times; =20 c->function =3D i; --=20 2.34.1 From nobody Sat Nov 23 17:57:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="40249471" X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="40249471" X-CSE-ConnectionGUID: WJsDUTziQwmHwDycveLuPA== X-CSE-MsgGUID: gczonL7ZSOWZhQZn9PyX9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="81420947" From: Tao Su To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 4/6] target/i386: Add feature dependencies for AVX10 Date: Mon, 28 Oct 2024 10:45:10 +0800 Message-Id: <20241028024512.156724-5-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028024512.156724-1-tao1.su@linux.intel.com> References: <20241028024512.156724-1-tao1.su@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083947365116600 Content-Type: text/plain; charset="utf-8" Since the highest supported vector length for a processor implies that all lesser vector lengths are also supported, add the dependencies of the supported vector lengths. If all vector lengths aren't supported, clear AVX10 enable bit as well. Note that the order of AVX10 related dependencies should be kept as: CPUID_24_0_EBX_AVX10_128 -> CPUID_24_0_EBX_AVX10_256, CPUID_24_0_EBX_AVX10_256 -> CPUID_24_0_EBX_AVX10_512, CPUID_24_0_EBX_AVX10_VL_MASK -> CPUID_7_1_EDX_AVX10, CPUID_7_1_EDX_AVX10 -> CPUID_24_0_EBX, so that prevent user from setting weird CPUID combinations, e.g. 256-bits and 512-bits are supported but 128-bits is not, no vector lengths are supported but AVX10 enable bit is still set. Since AVX10_128 will be reserved as 1, adding these dependencies has the bonus that when user sets -cpu host,-avx10-128, CPUID_7_1_EDX_AVX10 and CPUID_24_0_EBX will be disabled automatically. Tested-by: Xuelian Guo Signed-off-by: Tao Su Reviewed-by: Zhao Liu --- target/i386/cpu.c | 16 ++++++++++++++++ target/i386/cpu.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 91fae0dcb7..9666dbf29c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1760,6 +1760,22 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, .to =3D { FEAT_SGX_12_1_EAX, ~0ull }, }, + { + .from =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, + .to =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, + }, + { + .from =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, + .to =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, + }, + { + .from =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK= }, + .to =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + }, + { + .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + .to =3D { FEAT_24_0_EBX, ~0ull }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5566a13f4f..e4c947b478 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -997,6 +997,10 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cp= u, FeatureWord w); #define CPUID_24_0_EBX_AVX10_256 (1U << 17) /* AVX10 512-bit vector support is present */ #define CPUID_24_0_EBX_AVX10_512 (1U << 18) +/* AVX10 vector length support mask */ +#define CPUID_24_0_EBX_AVX10_VL_MASK (CPUID_24_0_EBX_AVX10_128 | \ + CPUID_24_0_EBX_AVX10_256 | \ + CPUID_24_0_EBX_AVX10_512) =20 /* RAS Features */ #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) --=20 2.34.1 From nobody Sat Nov 23 17:57:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730083921; cv=none; d=zohomail.com; s=zohoarc; b=J8xXiHiwHhoUzF0TVox9mjvaJaO9pnU2u8GNNTqZdo9Uu51q2thD93UspXwc2UWivuu7kVb6HP/XG+dTICR5R7XEFDaWXxKjdDuc8WGqK21w6ze86tYSdHJE20JMy8q6QbrrpjDnjYVBj25RxoNz6qBrT9sI2CBYvxBhBnILxJA= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083923355116600 Content-Type: text/plain; charset="utf-8" Intel AVX10 represents the first major new vector ISA since the introduction of Intel AVX512, which will establish a common, converged vector instruction set across all Intel architectures. AVX10 enable bit is enumerated via CPUID.(EAX=3D7,ECX=3D1):EDX[bit 19]. Add the CPUID definition for AVX10 enable bit, AVX10 will be enabled automatically when using '-cpu host' and KVM advertises AVX10 to userspace. Tested-by: Xuelian Guo Signed-off-by: Tao Su --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9666dbf29c..adde98fd26 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1133,7 +1133,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx-vnni-int8", "avx-ne-convert", NULL, NULL, "amx-complex", NULL, "avx-vnni-int16", NULL, NULL, NULL, "prefetchiti", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "avx10", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, --=20 2.34.1 From nobody Sat Nov 23 17:57:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730083933; cv=none; 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i=@intel.com; q=dns/txt; s=Intel; t=1730083879; x=1761619879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rp03Uwl7l03pPj4HY9BuMvQ1YdrKKOFrRjevx8nf8/s=; b=HSAhEO+GuaVj9ZnhvsfZ+IHp1svEmJTimWDYUQPfWcTIZOZmEqAgYzyZ X3TwMwM89RlkJlrAUhLr8x6t+Ox6hkmR80FXlxFUgE7Avyj/O6XetomnH TVHjgsyr1qNFSmAW0VR9HkbO83EBz2BEvL77pxQOEaF5fDuxZQb6P02/S 0fX1wPjVQafH5ok0DZRLuZyozRPpZAJ5PzuLro57IfT8Q418dgM0fdwLQ 8TKIWxUdwxHilc4RWU/85pRTo8O144/Bkiz0ftI4RVe87hCAaSzk1iGnQ m14FUFt1QAYTlhAY+TdmOjfDL+0O+4l77R8TsuNKPOm0caGsQCbl+cMkf Q==; X-CSE-ConnectionGUID: QaHNSbK2RnGcNdJgxsET4w== X-CSE-MsgGUID: 1TrsxcjtTmCVFlwi6ENLqQ== X-IronPort-AV: E=McAfee;i="6700,10204,11238"; a="40249478" X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="40249478" X-CSE-ConnectionGUID: DDpFGIdcT9ujjbRSzhG3Cg== X-CSE-MsgGUID: zTjI3JZVQmeColUNzejurA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="81420959" From: Tao Su To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 6/6] target/i386: Introduce GraniteRapids-v2 model Date: Mon, 28 Oct 2024 10:45:12 +0800 Message-Id: <20241028024512.156724-7-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028024512.156724-1-tao1.su@linux.intel.com> References: <20241028024512.156724-1-tao1.su@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.11; envelope-from=tao1.su@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730083935158116600 Content-Type: text/plain; charset="utf-8" Update GraniteRapids CPU model to add AVX10 and the missing features(ss, tsc-adjust, cldemote, movdiri, movdir64b). Tested-by: Xuelian Guo Signed-off-by: Tao Su Reviewed-by: Zhao Liu --- target/i386/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index adde98fd26..8d72c08b66 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4375,6 +4375,23 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .model_id =3D "Intel Xeon Processor (GraniteRapids)", .versions =3D (X86CPUVersionDefinition[]) { { .version =3D 1 }, + { + .version =3D 2, + .props =3D (PropValue[]) { + { "ss", "on" }, + { "tsc-adjust", "on" }, + { "cldemote", "on" }, + { "movdiri", "on" }, + { "movdir64b", "on" }, + { "avx10", "on" }, + { "avx10-128", "on" }, + { "avx10-256", "on" }, + { "avx10-512", "on" }, + { "avx10-version", "1" }, + { "stepping", "1" }, + { /* end of list */ } + } + }, { /* end of list */ }, }, }, --=20 2.34.1