From nobody Sat Nov 23 18:05:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1730082529; cv=none; d=zohomail.com; s=zohoarc; b=YMH7EK/qhH/Ci5y7HX95POSJK1zL7K7n9DM+wpM2JpglzXsWKsiS30EWjZgK72ZW+m9l/wjSZgarflAgQOSvruQ+aeHvLsOLFQYh8G9Vi8eWU/57mY3v3gm8FkK/8QzAyL0bx/TM0zKgplnE9PJsXaA1coXnxaSqxcTqFCNN5z8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730082529; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mN0vMN+C8MllKCvxpmdFVWKXfR4zUDoUJMkSWTnaqrM=; b=AdYKPkA+W7DNZBtlISrXEgsJKMq4sJn/8WiNYKO5aKrFL6KlJZ4mxwzV2ziv6o058D9AO6VVfQkl3gzPP+SZH0rKe0TGYk9P87FRaJQkR2Nov0x5Pup0JmzB2YQo5zapXV1kp2ZH3o2rqPzVM8RWV9KNq1+0mvkQm4o9dBOTe18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730082529082657.0867175885169; Sun, 27 Oct 2024 19:28:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t5FUW-0000Ur-Ni; Sun, 27 Oct 2024 22:28:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5FUU-0000UZ-GN for qemu-devel@nongnu.org; Sun, 27 Oct 2024 22:28:22 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t5FUS-0001Up-PG for qemu-devel@nongnu.org; Sun, 27 Oct 2024 22:28:22 -0400 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2024 19:28:18 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2024 19:28:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730082501; x=1761618501; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Kl7S6zlTFz7qHl+7wyxWluZGnAUh2UPTeqAC6mt/ZXo=; b=BTz34760bwJOofh+9jZh9KXwtpOoXylqCRZK9fgZdX4V7wzMlbOQsrkZ KXzUSs1b6mPTXNt5fJVCECcVOmGkn5tSFkde5afFJFI6PCligRKft6cBf RiWsLvimlKS57B7176Yw4PHcufwe1Iky9M/sFvQR5zrxhqpvM7BZzlsEg auUbXb1MNeJzwB4FV9CwdN+dDLmsvEsSKRdEPZ1c5YqJTIlzqKRp/+s2j z9R4YReFa1WUv4zckkqhZ/XsHicbc+mz+K/Q4S49MoZJDkD489TD1tFJS Ju0Ig0pIVdjSCovbhUz/Z6bxGTTp5rj0460UgW8k2CWt1QE7qfmEjbo+M A==; X-CSE-ConnectionGUID: tw0F9KIiQBqcIGS3IrkKRQ== X-CSE-MsgGUID: k6EYZuEdSRKT5UY1dVdNJQ== X-IronPort-AV: E=McAfee;i="6700,10204,11238"; a="40288516" X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="40288516" X-CSE-ConnectionGUID: U8HxFQmSTiunf0Nebz7pPA== X-CSE-MsgGUID: zrUisUziT+eOwsB2c1vDvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,238,1725346800"; d="scan'208";a="81379685" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: chao.p.peng@intel.com, Zhenzhong Duan , Yi Liu , Jason Wang , "Michael S. Tsirkin" , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v5] intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) field Date: Mon, 28 Oct 2024 10:25:14 +0800 Message-Id: <20241028022514.806657-1-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.287, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1730082530215116600 Content-Type: text/plain; charset="utf-8" VT-d spec removed Transient Mapping (TM) field from second-level page-tables and treat the field as Reserved(0) since revision 3.2. Changing the field as reserved(0) will break backward compatibility, so introduce a property "stale-tm" to allow user to control the setting. Use pc_compat_9_1 to handle the compatibility for machines before 9.2 which allow guest to set the field. Starting from 9.2, this field is reserved(0) by default to match spec. Of course, user can force it on command line. This doesn't impact function of vIOMMU as there was no logic to emulate Transient Mapping. Suggested-by: Yi Liu Suggested-by: Jason Wang Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- v5: fix typo, s/hw_compat_9_1/pc_compat_9_1 (Liuyi) v4: s/x-stale-tm/stale-tm (Jason) v3: still need to check x86_iommu->dt_supported v2: introcude "x-stale-tm" to handle migration compatibility (Jason) hw/i386/intel_iommu_internal.h | 12 ++++++------ include/hw/i386/intel_iommu.h | 3 +++ hw/i386/intel_iommu.c | 7 ++++--- hw/i386/pc.c | 1 + 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 13d5d129ae..2f9bc0147d 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -412,8 +412,8 @@ typedef union VTDInvDesc VTDInvDesc; /* Rsvd field masks for spte */ #define VTD_SPTE_SNP 0x800ULL =20 -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ - dt_supported ? \ +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, stale_tm) \ + stale_tm ? \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ @@ -423,12 +423,12 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ - dt_supported ? \ +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, stale_tm) \ + stale_tm ? \ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) := \ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ - dt_supported ? \ +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, stale_tm) \ + stale_tm ? \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1eb05c29fc..d372cd396b 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -306,6 +306,9 @@ struct IntelIOMMUState { bool dma_translation; /* Whether DMA translation supported */ bool pasid; /* Whether to support PASID */ =20 + /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */ + bool stale_tm; + /* * Protects IOMMU states in general. Currently it protects the * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 08fe218935..8612d0917b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3372,6 +3372,7 @@ static Property vtd_properties[] =3D { DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, = true), + DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -4138,15 +4139,15 @@ static void vtd_init(IntelIOMMUState *s) */ vtd_spte_rsvd[0] =3D ~0ULL; vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, - x86_iommu->dt_supported); + x86_iommu->dt_supported && s->stal= e_tm); vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); =20 vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, - x86_iommu->dt_supporte= d); + x86_iommu->dt_supported && s->stal= e_tm); vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, - x86_iommu->dt_supporte= d); + x86_iommu->dt_supported && s->stal= e_tm); =20 if (s->scalable_mode || s->snoop_control) { vtd_spte_rsvd[1] &=3D ~VTD_SPTE_SNP; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2047633e4c..830614d930 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -82,6 +82,7 @@ GlobalProperty pc_compat_9_1[] =3D { { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, { "ICH9-LPC", "x-smi-periodic-timer", "off" }, + { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, }; const size_t pc_compat_9_1_len =3D G_N_ELEMENTS(pc_compat_9_1); =20 --=20 2.34.1