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Sat, 26 Oct 2024 10:55:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson Subject: [PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext Date: Sat, 26 Oct 2024 14:53:49 -0300 Message-ID: <20241026175349.84523-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965328682116600 Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/mips/tcg/loong_translate.c | 41 ++----------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index c02e60bb15b..a005c279a3e 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -31,13 +31,6 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int = rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2, *l3; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -61,8 +54,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int r= s, int rt, tcg_gen_br(l3); gen_set_label(l1); =20 - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS =3D= =3D 64 - ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l= 2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); tcg_gen_mov_tl(cpu_gpr[rd], t0); =20 @@ -93,13 +85,6 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int= rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -147,13 +132,6 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, in= t rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2, *l3; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -173,8 +151,7 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int= rs, int rt, tcg_gen_ext32u_tl(t1, t1); } tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS =3D= =3D 64 - ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l= 2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); gen_set_label(l1); tcg_gen_movi_tl(cpu_gpr[rd], 0); @@ -205,13 +182,6 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, i= nt rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -257,13 +227,6 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd, i= nt rs, int rt, { TCGv t0, t1; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; --=20 2.45.2