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Sat, 26 Oct 2024 10:54:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper Date: Sat, 26 Oct 2024 14:53:41 -0300 Message-ID: <20241026175349.84523-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965308574116600 Extract the decode_64bit_enabled() helper which detects whether CPUs can run 64-bit instructions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/translate.c | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 5d196e69ac4..ae6c25aa0c4 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -217,6 +217,8 @@ void msa_translate_init(void); void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); =20 +bool decode_64bit_enabled(DisasContext *ctx); + /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index d92fc418edd..6c881af5618 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } =20 +bool decode_64bit_enabled(DisasContext *ctx) +{ + return ctx->hflags & MIPS_HFLAG_64; +} + /* * This code generates a "reserved instruction" exception if cpu is not * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely((TARGET_LONG_BITS !=3D 64) || !(ctx->hflags & MIPS_HFLAG_= 64))) { + if (unlikely((TARGET_LONG_BITS !=3D 64) || !decode_64bit_enabled(ctx))= ) { gen_reserved_instruction(ctx); } } --=20 2.45.2 From nobody Sat Nov 23 17:45:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729965306; cv=none; d=zohomail.com; s=zohoarc; b=Tuu2bx7xmEpOZnyDQ91slBilvUW8WNW3nN6Xcy5qaTX17nFAsjYhviUf9ZHQKolsxlWJdXSD26LgoFWQBwe9qLAelx/qn64+k/GHHm4LgzF9eSy3iWrec6U0q9VOuJgeIzYqOMDdzHp5DBKB6O13VcGxKlEPOES4RwzUcWoQns0= ARC-Message-Signature: i=1; a=rsa-sha256; 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Sat, 26 Oct 2024 10:54:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson Subject: [PATCH v3 2/9] target/mips: Simplify Loongson MULTU.G opcode Date: Sat, 26 Oct 2024 14:53:42 -0300 Message-ID: <20241026175349.84523-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965306678116600 Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DMULTU). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6c881af5618..6d7e913263e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -3615,8 +3615,6 @@ static void gen_loongson_integer(DisasContext *ctx, u= int32_t opc, break; case OPC_MULTU_G_2E: case OPC_MULTU_G_2F: - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; --=20 2.45.2 From nobody Sat Nov 23 17:45:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965342906116600 From: Philippe Mathieu-Daud=C3=A9 There is no issue having multiple enum declarations with the same value. As we are going to remove the OPC_MULT_G_2E definition in few commits, restore the OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP definitions and use them where they belong. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/translate.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6d7e913263e..509488fdc7a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -389,16 +389,14 @@ enum { OPC_ADDU_OB_DSP =3D 0x14 | OPC_SPECIAL3, OPC_ABSQ_S_PH_DSP =3D 0x12 | OPC_SPECIAL3, OPC_ABSQ_S_QH_DSP =3D 0x16 | OPC_SPECIAL3, - /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ - /* OPC_ADDUH_QB_DSP =3D 0x18 | OPC_SPECIAL3, */ + OPC_ADDUH_QB_DSP =3D 0x18 | OPC_SPECIAL3, OPC_CMPU_EQ_QB_DSP =3D 0x11 | OPC_SPECIAL3, OPC_CMPU_EQ_OB_DSP =3D 0x15 | OPC_SPECIAL3, /* MIPS DSP GPR-Based Shift Sub-class */ OPC_SHLL_QB_DSP =3D 0x13 | OPC_SPECIAL3, OPC_SHLL_OB_DSP =3D 0x17 | OPC_SPECIAL3, /* MIPS DSP Multiply Sub-class insns */ - /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ - /* OPC_MUL_PH_DSP =3D 0x18 | OPC_SPECIAL3, */ + OPC_MUL_PH_DSP =3D 0x18 | OPC_SPECIAL3, OPC_DPA_W_PH_DSP =3D 0x30 | OPC_SPECIAL3, OPC_DPAQ_W_QH_DSP =3D 0x34 | OPC_SPECIAL3, /* DSP Bit/Manipulation Sub-class */ @@ -556,7 +554,6 @@ enum { OPC_MULQ_S_PH =3D (0x1E << 6) | OPC_ADDU_QB_DSP, }; =20 -#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)= )) enum { /* MIPS DSP Arithmetic Sub-class */ @@ -11587,8 +11584,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, gen_load_gpr(v2_t, v2); =20 switch (op1) { - /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ - case OPC_MULT_G_2E: + case OPC_ADDUH_QB_DSP: check_dsp_r2(ctx); switch (op2) { case OPC_ADDUH_QB: @@ -12271,11 +12267,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx= , uint32_t op1, uint32_t op2, gen_load_gpr(v2_t, v2); =20 switch (op1) { - /* - * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have - * the same mask and op1. - */ - case OPC_MULT_G_2E: + case OPC_MUL_PH_DSP: check_dsp_r2(ctx); switch (op2) { case OPC_MUL_PH: @@ -13811,7 +13803,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ - if ((ctx->insn_flags & ASE_DSP_R2) && (op1 =3D=3D OPC_MULT_G_2E)) { + if ((ctx->insn_flags & ASE_DSP_R2) && (op1 =3D=3D OPC_MUL_PH_DSP))= { op2 =3D MASK_ADDUH_QB(ctx->opcode); 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Sat, 26 Oct 2024 10:54:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 4/9] target/mips: Convert Loongson DDIV.G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:44 -0300 Message-ID: <20241026175349.84523-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965314745116600 From: Philippe Mathieu-Daud=C3=A9 Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/translate.h | 1 + target/mips/tcg/godson2.decode | 16 ++++++ target/mips/tcg/loong-ext.decode | 17 ++++++ target/mips/tcg/loong_translate.c | 86 +++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 26 ++-------- target/mips/tcg/meson.build | 3 ++ 6 files changed, 126 insertions(+), 23 deletions(-) create mode 100644 target/mips/tcg/godson2.decode create mode 100644 target/mips/tcg/loong-ext.decode create mode 100644 target/mips/tcg/loong_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index ae6c25aa0c4..23a489c0f38 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -223,6 +223,7 @@ bool decode_64bit_enabled(DisasContext *ctx); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); +bool decode_ext_loongson(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ase_lcsr(DisasContext *ctx, uint32_t insn); bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode new file mode 100644 index 00000000000..47ea5a1c438 --- /dev/null +++ b/target/mips/tcg/godson2.decode @@ -0,0 +1,16 @@ +# Godson2 64-bit Integer instructions +# +# Copyright (C) 2021 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# Godson-2E Software Manual +# (Document Number: godson2e-user-manual-V0.6) +# + +&muldiv rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv + +DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.d= ecode new file mode 100644 index 00000000000..8b78ec48599 --- /dev/null +++ b/target/mips/tcg/loong-ext.decode @@ -0,0 +1,17 @@ +# Loongson 64-bit Extension instructions +# +# Copyright (C) 2021 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# STLS2F01 User Manual +# Appendix A: new integer instructions +# (Document Number: UM0447) +# + +&muldiv rs rt rd !extern + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv + +DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c new file mode 100644 index 00000000000..53e4047cfa0 --- /dev/null +++ b/target/mips/tcg/loong_translate.c @@ -0,0 +1,86 @@ +/* + * MIPS Loongson 64-bit translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2011 Richard Henderson + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 + * + * This code is licensed under the GNU GPLv2 and later. + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-godson2.c.inc" +#include "decode-loong-ext.c.inc" + +/* + * Word or double-word Fixed-point instructions. + * --------------------------------------------- + * + * Fixed-point multiplies and divisions write only + * one result into general-purpose registers. + */ + +static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt) +{ + TCGv t0, t1; + TCGLabel *l1, *l2, *l3; + + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + l3 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l1); + + tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + gen_set_label(l3); + + return true; +} + +static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIV_G(s, a->rt, a->rs, a->rd); +} + +bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) +{ + if (!decode_64bit_enabled(ctx)) { + return false; + } + if ((ctx->insn_flags & INSN_LOONGSON2E) && decode_godson2(ctx, ctx->op= code)) { + return true; + } + if ((ctx->insn_flags & ASE_LEXT) && decode_loong_ext(ctx, ctx->opcode)= ) { + return true; + } + return false; +} diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 509488fdc7a..73445dd9074 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -333,7 +333,6 @@ enum { OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, OPC_DIV_G_2F =3D 0x14 | OPC_SPECIAL2, - OPC_DDIV_G_2F =3D 0x15 | OPC_SPECIAL2, OPC_DIVU_G_2F =3D 0x16 | OPC_SPECIAL2, OPC_DDIVU_G_2F =3D 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F =3D 0x1c | OPC_SPECIAL2, @@ -375,7 +374,6 @@ enum { OPC_DIVU_G_2E =3D 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E =3D 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E =3D 0x1D | OPC_SPECIAL3, - OPC_DDIV_G_2E =3D 0x1E | OPC_SPECIAL3, OPC_DDIVU_G_2E =3D 0x1F | OPC_SPECIAL3, OPC_MOD_G_2E =3D 0x22 | OPC_SPECIAL3, OPC_MODU_G_2E =3D 0x23 | OPC_SPECIAL3, @@ -3698,25 +3696,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DDIV_G_2E: - case OPC_DDIV_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - TCGLabel *l3 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); - tcg_gen_mov_tl(cpu_gpr[rd], t0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l3); - } - break; case OPC_DDIVU_G_2E: case OPC_DDIVU_G_2F: { @@ -13654,7 +13633,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DDIV_G_2F: case OPC_DDIVU_G_2F: case OPC_DMOD_G_2F: case OPC_DMODU_G_2F: @@ -14061,7 +14039,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E: case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: @@ -15262,6 +15239,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->= opcode)) { return; } + if (TARGET_LONG_BITS =3D=3D 64 && decode_ext_loongson(ctx, ctx->opcode= )) { + return; + } #if defined(TARGET_MIPS64) if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { return; diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index ea7fb582f2a..fd91148df74 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,4 +1,6 @@ gen =3D [ + decodetree.process('godson2.decode', extra_args: ['--static-decode=3Ddec= ode_godson2']), + decodetree.process('loong-ext.decode', extra_args: ['--static-decode=3Dd= ecode_loong_ext']), decodetree.process('rel6.decode', extra_args: ['--decode=3Ddecode_isa_re= l6']), decodetree.process('msa.decode', extra_args: '--decode=3Ddecode_ase_msa'= ), decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), @@ -28,6 +30,7 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', 'octeon_translate.c', 'lcsr_translate.c', + 'loong_translate.c', ), if_false: files( 'mxu_translate.c', )) --=20 2.45.2 From nobody Sat Nov 23 17:45:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sat, 26 Oct 2024 10:54:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 5/9] target/mips: Convert Loongson DIV.G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:45 -0300 Message-ID: <20241026175349.84523-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965306748116600 From: Philippe Mathieu-Daud=C3=A9 DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a 'is_double' argument so it can generate DIV.G (divide 32-bit signed integers). With this commit we explicit the template used to generate opcode for 32/64-bit word variants. Next commits will be less verbose by providing both variants at once. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/godson2.decode | 1 + target/mips/tcg/loong-ext.decode | 1 + target/mips/tcg/loong_translate.c | 28 ++++++++++++++++++++++------ target/mips/tcg/translate.c | 26 -------------------------- 4 files changed, 24 insertions(+), 32 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index 47ea5a1c438..cbf24ed88da 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -13,4 +13,5 @@ =20 @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv =20 +DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.d= ecode index 8b78ec48599..9397606beb6 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -14,4 +14,5 @@ =20 @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv =20 +DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index 53e4047cfa0..7c405078795 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -25,15 +25,18 @@ * one result into general-purpose registers. */ =20 -static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt) +static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) { TCGv t0, t1; TCGLabel *l1, *l2, *l3; =20 - if (TARGET_LONG_BITS !=3D 64) { - return false; + if (is_double) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); } - check_mips_64(s); =20 if (rd =3D=3D 0) { /* Treat as NOP. */ @@ -49,26 +52,39 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int= rs, int rt) gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); =20 + if (!is_double) { + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + } tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); tcg_gen_movi_tl(cpu_gpr[rd], 0); tcg_gen_br(l3); gen_set_label(l1); =20 - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS =3D= =3D 64 + ? LLONG_MIN : INT_MIN, l2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); tcg_gen_mov_tl(cpu_gpr[rd], t0); =20 tcg_gen_br(l3); gen_set_label(l2); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } gen_set_label(l3); =20 return true; } =20 +static bool trans_DIV_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, false); +} + static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) { - return gen_lext_DIV_G(s, a->rt, a->rs, a->rd); + return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true); } =20 bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 73445dd9074..1c38e893d31 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,7 +332,6 @@ enum { OPC_DMULT_G_2F =3D 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, - OPC_DIV_G_2F =3D 0x14 | OPC_SPECIAL2, OPC_DIVU_G_2F =3D 0x16 | OPC_SPECIAL2, OPC_DDIVU_G_2F =3D 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F =3D 0x1c | OPC_SPECIAL2, @@ -370,7 +369,6 @@ enum { /* Loongson 2E */ OPC_MULT_G_2E =3D 0x18 | OPC_SPECIAL3, OPC_MULTU_G_2E =3D 0x19 | OPC_SPECIAL3, - OPC_DIV_G_2E =3D 0x1A | OPC_SPECIAL3, OPC_DIVU_G_2E =3D 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E =3D 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E =3D 0x1D | OPC_SPECIAL3, @@ -3613,28 +3611,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_DIV_G_2E: - case OPC_DIV_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - TCGLabel *l3 =3D gen_new_label(); - tcg_gen_ext32s_tl(t0, t0); - tcg_gen_ext32s_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); - tcg_gen_mov_tl(cpu_gpr[rd], t0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l3); - } - break; case OPC_DIVU_G_2E: case OPC_DIVU_G_2F: { @@ -13598,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_DIV_G_2F: case OPC_DIVU_G_2F: case OPC_MULT_G_2F: case OPC_MULTU_G_2F: @@ -13771,7 +13746,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); 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Sat, 26 Oct 2024 10:54:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 6/9] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:46 -0300 Message-ID: <20241026175349.84523-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965360676116600 From: Philippe Mathieu-Daud=C3=A9 Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G (divide 64-bit unsigned integers) opcodes to decodetree. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/godson2.decode | 2 ++ target/mips/tcg/loong-ext.decode | 2 ++ target/mips/tcg/loong_translate.c | 54 +++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 37 --------------------- 4 files changed, 58 insertions(+), 37 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index cbf24ed88da..581cb9c8608 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -14,4 +14,6 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv =20 DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd +DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd +DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.d= ecode index 9397606beb6..e222167af56 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -16,3 +16,5 @@ =20 DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd +DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd +DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index 7c405078795..903d242e7cc 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -87,6 +87,60 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true); } =20 +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2; + + if (is_double) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); + } + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l2); + + return true; +} + +static bool trans_DIVU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1c38e893d31..53bbbb761f8 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,8 +332,6 @@ enum { OPC_DMULT_G_2F =3D 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, - OPC_DIVU_G_2F =3D 0x16 | OPC_SPECIAL2, - OPC_DDIVU_G_2F =3D 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F =3D 0x1c | OPC_SPECIAL2, OPC_DMOD_G_2F =3D 0x1d | OPC_SPECIAL2, OPC_MODU_G_2F =3D 0x1e | OPC_SPECIAL2, @@ -369,10 +367,8 @@ enum { /* Loongson 2E */ OPC_MULT_G_2E =3D 0x18 | OPC_SPECIAL3, OPC_MULTU_G_2E =3D 0x19 | OPC_SPECIAL3, - OPC_DIVU_G_2E =3D 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E =3D 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E =3D 0x1D | OPC_SPECIAL3, - OPC_DDIVU_G_2E =3D 0x1F | OPC_SPECIAL3, OPC_MOD_G_2E =3D 0x22 | OPC_SPECIAL3, OPC_MODU_G_2E =3D 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E =3D 0x26 | OPC_SPECIAL3, @@ -3611,22 +3607,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_DIVU_G_2E: - case OPC_DIVU_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l2); - } - break; case OPC_MOD_G_2E: case OPC_MOD_G_2F: { @@ -3672,19 +3652,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DDIVU_G_2E: - case OPC_DDIVU_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l2); - } - break; case OPC_DMOD_G_2E: case OPC_DMOD_G_2F: { @@ -13574,7 +13541,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_DIVU_G_2F: case OPC_MULT_G_2F: case OPC_MULTU_G_2F: case OPC_MOD_G_2F: @@ -13608,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DDIVU_G_2F: case OPC_DMOD_G_2F: case OPC_DMODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); @@ -13746,7 +13711,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_DIVU_G_2E: case OPC_MOD_G_2E: case OPC_MODU_G_2E: case OPC_MULT_G_2E: @@ -14013,7 +13977,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DDIVU_G_2E: case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: case OPC_DMOD_G_2E: --=20 2.45.2 From nobody Sat Nov 23 17:45:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965368785116600 From: Philippe Mathieu-Daud=C3=A9 Convert the following opcodes to decodetree: - MOD.G - mod 32-bit signed integers - MODU.G - mod 32-bit unsigned integers - DMOD.G - mod 64-bit signed integers - DMODU.G - mod 64-bit unsigned integers Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/godson2.decode | 5 ++ target/mips/tcg/loong-ext.decode | 5 ++ target/mips/tcg/loong_translate.c | 111 ++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 82 ---------------------- 4 files changed, 121 insertions(+), 82 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index 581cb9c8608..c03c8b717d9 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -17,3 +17,8 @@ DIV_G 011111 ..... ..... ..... 00000 011010 @= rs_rt_rd DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd + +MOD_G 011111 ..... ..... ..... 00000 100010 @rs_rt_rd +MODU_G 011111 ..... ..... ..... 00000 100011 @rs_rt_rd +DMOD_G 011111 ..... ..... ..... 00000 100110 @rs_rt_rd +DMODU_G 011111 ..... ..... ..... 00000 100111 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.d= ecode index e222167af56..f0fd36c9218 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -18,3 +18,8 @@ DIV_G 011100 ..... ..... ..... 00000 010100 @= rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd + +MOD_G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd +DMOD_G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd +MODU_G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd +DMODU_G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index 903d242e7cc..76c1a8cef2d 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -141,6 +141,117 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv= *a) return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true); } =20 +static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2, *l3; + + if (is_double) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); + } + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + l3 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS =3D= =3D 64 + ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l3); + + return true; +} + +static bool trans_MOD_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, true); +} + +static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2; + + if (is_double) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); + } + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l2); + + return true; +} + +static bool trans_MODU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 53bbbb761f8..4abc30a6a5f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,10 +332,6 @@ enum { OPC_DMULT_G_2F =3D 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, - OPC_MOD_G_2F =3D 0x1c | OPC_SPECIAL2, - OPC_DMOD_G_2F =3D 0x1d | OPC_SPECIAL2, - OPC_MODU_G_2F =3D 0x1e | OPC_SPECIAL2, - OPC_DMODU_G_2F =3D 0x1f | OPC_SPECIAL2, /* Misc */ OPC_CLZ =3D 0x20 | OPC_SPECIAL2, OPC_CLO =3D 0x21 | OPC_SPECIAL2, @@ -369,10 +365,6 @@ enum { OPC_MULTU_G_2E =3D 0x19 | OPC_SPECIAL3, OPC_DMULT_G_2E =3D 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E =3D 0x1D | OPC_SPECIAL3, - OPC_MOD_G_2E =3D 0x22 | OPC_SPECIAL3, - OPC_MODU_G_2E =3D 0x23 | OPC_SPECIAL3, - OPC_DMOD_G_2E =3D 0x26 | OPC_SPECIAL3, - OPC_DMODU_G_2E =3D 0x27 | OPC_SPECIAL3, =20 /* MIPS DSP Load */ OPC_LX_DSP =3D 0x0A | OPC_SPECIAL3, @@ -3607,42 +3599,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_MOD_G_2E: - case OPC_MOD_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - TCGLabel *l3 =3D gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l3); - } - break; - case OPC_MODU_G_2E: - case OPC_MODU_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l2); - } - break; #if defined(TARGET_MIPS64) case OPC_DMULT_G_2E: case OPC_DMULT_G_2F: @@ -3652,36 +3608,6 @@ static void gen_loongson_integer(DisasContext *ctx, = uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DMOD_G_2E: - case OPC_DMOD_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - TCGLabel *l3 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l3); - } - break; - case OPC_DMODU_G_2E: - case OPC_DMODU_G_2F: - { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l2); - } - break; #endif } } @@ -13543,8 +13469,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_MULT_G_2F: case OPC_MULTU_G_2F: - case OPC_MOD_G_2F: - case OPC_MODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); gen_loongson_integer(ctx, op1, rd, rs, rt); break; @@ -13574,8 +13498,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DMOD_G_2F: - case OPC_DMODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); gen_loongson_integer(ctx, op1, rd, rs, rt); break; @@ -13711,8 +13633,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_MOD_G_2E: - case OPC_MODU_G_2E: case OPC_MULT_G_2E: case OPC_MULTU_G_2E: /* @@ -13979,8 +13899,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: - case OPC_DMOD_G_2E: - case OPC_DMODU_G_2E: check_insn(ctx, INSN_LOONGSON2E); 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Sat, 26 Oct 2024 10:54:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 8/9] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:48 -0300 Message-ID: <20241026175349.84523-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965352681116600 From: Philippe Mathieu-Daud=C3=A9 Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed integers - DMULTU.G - multiply 64-bit unsigned integers Now that all opcodes from the extension have been converted, we can remove completely gen_loongson_integer() and its 2 calls in decode_opc_special2_legacy() and decode_opc_special3_legacy(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/godson2.decode | 3 ++ target/mips/tcg/loong-ext.decode | 3 ++ target/mips/tcg/loong_translate.c | 41 +++++++++++++++++ target/mips/tcg/translate.c | 73 +------------------------------ 4 files changed, 49 insertions(+), 71 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index c03c8b717d9..25b396b6822 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -13,6 +13,9 @@ =20 @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv =20 +MULTu_G 011111 ..... ..... ..... 00000 01100- @rs_rt_rd +DMULTu_G 011111 ..... ..... ..... 00000 01110- @rs_rt_rd + DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.d= ecode index f0fd36c9218..b43979d0ef5 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -14,6 +14,9 @@ =20 @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv =20 +MULTu_G 011100 ..... ..... ..... 00000 0100-0 @rs_rt_rd +DMULTu_G 011100 ..... ..... ..... 00000 0100-1 @rs_rt_rd + DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index 76c1a8cef2d..c02e60bb15b 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -252,6 +252,47 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv = *a) return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true); } =20 +static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + + if (is_double) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } + check_mips_64(s); + } + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + + return true; +} + +static bool trans_MULTu_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DMULTu_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4abc30a6a5f..2d01f5c4a8b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -327,11 +327,6 @@ enum { OPC_MUL =3D 0x02 | OPC_SPECIAL2, OPC_MSUB =3D 0x04 | OPC_SPECIAL2, OPC_MSUBU =3D 0x05 | OPC_SPECIAL2, - /* Loongson 2F */ - OPC_MULT_G_2F =3D 0x10 | OPC_SPECIAL2, - OPC_DMULT_G_2F =3D 0x11 | OPC_SPECIAL2, - OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, - OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, /* Misc */ OPC_CLZ =3D 0x20 | OPC_SPECIAL2, OPC_CLO =3D 0x21 | OPC_SPECIAL2, @@ -360,12 +355,6 @@ enum { OPC_RDHWR =3D 0x3B | OPC_SPECIAL3, OPC_GINV =3D 0x3D | OPC_SPECIAL3, =20 - /* Loongson 2E */ - OPC_MULT_G_2E =3D 0x18 | OPC_SPECIAL3, - OPC_MULTU_G_2E =3D 0x19 | OPC_SPECIAL3, - OPC_DMULT_G_2E =3D 0x1C | OPC_SPECIAL3, - OPC_DMULTU_G_2E =3D 0x1D | OPC_SPECIAL3, - /* MIPS DSP Load */ OPC_LX_DSP =3D 0x0A | OPC_SPECIAL3, /* MIPS DSP Arithmetic */ @@ -3572,46 +3561,6 @@ static void gen_cl(DisasContext *ctx, uint32_t opc, } } =20 -/* Godson integer instructions */ -static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0, t1; - - if (rd =3D=3D 0) { - /* Treat as NOP. */ - return; - } - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_MULT_G_2E: - case OPC_MULT_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - break; - case OPC_MULTU_G_2E: - case OPC_MULTU_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - break; -#if defined(TARGET_MIPS64) - case OPC_DMULT_G_2E: - case OPC_DMULT_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - break; - case OPC_DMULTU_G_2E: - case OPC_DMULTU_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - break; -#endif - } -} - /* Loongson multimedia instructions */ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int= rt) { @@ -13467,11 +13416,6 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_MULT_G_2F: - case OPC_MULTU_G_2F: - check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); - gen_loongson_integer(ctx, op1, rd, rs, rt); - break; case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS_R1); @@ -13496,11 +13440,6 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; - case OPC_DMULT_G_2F: - case OPC_DMULTU_G_2F: - check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); - gen_loongson_integer(ctx, op1, rd, rs, rt); - break; #endif default: /* Invalid */ MIPS_INVAL("special2_legacy"); @@ -13633,10 +13572,9 @@ static void decode_opc_special3_legacy(CPUMIPSStat= e *env, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_MULT_G_2E: - case OPC_MULTU_G_2E: + case OPC_MUL_PH_DSP: /* - * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have + * OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ if ((ctx->insn_flags & ASE_DSP_R2) && (op1 =3D=3D OPC_MUL_PH_DSP))= { @@ -13667,8 +13605,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_reserved_instruction(ctx); break; } - } else if (ctx->insn_flags & INSN_LOONGSON2E) { - gen_loongson_integer(ctx, op1, rd, rs, rt); } else { gen_reserved_instruction(ctx); } @@ -13897,11 +13833,6 @@ static void decode_opc_special3_legacy(CPUMIPSStat= e *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DMULT_G_2E: - case OPC_DMULTU_G_2E: - check_insn(ctx, INSN_LOONGSON2E); - gen_loongson_integer(ctx, op1, rd, rs, rt); - break; case OPC_ABSQ_S_QH_DSP: op2 =3D MASK_ABSQ_S_QH(ctx->opcode); switch (op2) { --=20 2.45.2 From nobody Sat Nov 23 17:45:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729965327; cv=none; d=zohomail.com; s=zohoarc; b=Kz08K+yhvn6vsJ08QBUNwua/mbMdmLIe0dbGUYWym0HjkuN0ZutModNdhC33GLz4Ft2XdWwWUHxa72UZo2M/T9xq8EhK/9LxaPJt43p6AE2IQLcYveCPthq4VGW/qhwwNyht9ndHY3aMnNsSIxUkoQG59wLF9Blo9ne21bYUX5k= ARC-Message-Signature: i=1; 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Sat, 26 Oct 2024 10:55:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson Subject: [PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext Date: Sat, 26 Oct 2024 14:53:49 -0300 Message-ID: <20241026175349.84523-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729965328682116600 Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/mips/tcg/loong_translate.c | 41 ++----------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index c02e60bb15b..a005c279a3e 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -31,13 +31,6 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int = rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2, *l3; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -61,8 +54,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int r= s, int rt, tcg_gen_br(l3); gen_set_label(l1); =20 - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS =3D= =3D 64 - ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l= 2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); tcg_gen_mov_tl(cpu_gpr[rd], t0); =20 @@ -93,13 +85,6 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int= rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -147,13 +132,6 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, in= t rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2, *l3; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -173,8 +151,7 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int= rs, int rt, tcg_gen_ext32u_tl(t1, t1); } tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS =3D= =3D 64 - ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l= 2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); gen_set_label(l1); tcg_gen_movi_tl(cpu_gpr[rd], 0); @@ -205,13 +182,6 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, i= nt rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; @@ -257,13 +227,6 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd, i= nt rs, int rt, { TCGv t0, t1; =20 - if (is_double) { - if (TARGET_LONG_BITS !=3D 64) { - return false; - } - check_mips_64(s); - } - if (rd =3D=3D 0) { /* Treat as NOP. */ return true; --=20 2.45.2