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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865582; x=1730470382; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zz8dlKtWuutyQ/7iCySTdzhMOZ3Vcdo7OJOwt3HomLY=; b=LmZoURKWsnnKWlhyHsn/ezI3dpOfdDbZFr1rMDgWbM8ukch1WWE6mcQ5SlQhGTOtkU smjeDVTHfMzLWv3qIR5XK+LcKCDuGZB0aucXO3qzNV/Z/AAaoiH/2uJTh1dpl6BBNn5n lKz3CL/dngeQMjRpuux5Sh8t0uems5lHeWxB0Mc1+W1ZKeYl+zAC7hLkPuwUNetZHlS7 oQUp9vscMh3AFAasKjisuPNmcX53CyoyZFoY4S+7QcpyWISP6InVhRtdFcbCJd0/SqvX eqpZc4O1PeSE26gy4ilwV9IgERpZYjnrxemtRyUP+1sjDLj4R1B5zj63Y51sRmo+MLMP SMmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865582; x=1730470382; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zz8dlKtWuutyQ/7iCySTdzhMOZ3Vcdo7OJOwt3HomLY=; b=GJ4sUNRKqEKc00KGO3vc8+GivWG3Cw/q0D7dfkCQ+RLKs24+5j1ANcISSMjhzASeLt 5vR4sZDq5iIGV18k1XMIMj0Z34FSVzoh7hggfzoDM1f1SpOSMR28J410c8vmYL4FUVjn Xn6wab3bw/b2yMcGdybQdD6lPzXeLDAAf4o7hLt9dFT94Hz2rcPd9VB3Rgxg0iiDKjUj kiMy+S1gG/W3pq5jLHF//no7+1ffE5heZNDaZKg3+8UNG6hkW9AyWLq3URi8sLeqxJ6z Bd5q7TVOj8r8mYWdmoF+20TyGSbx+XuiOQ0Hojchh66eLHLP6sXFs6EsEKXz+TCGDpbA MQkQ== X-Forwarded-Encrypted: i=1; AJvYcCVQc3lIPkfU4NYD77R1dzN3OSofX9z3LUIC/XBRxPrOlC6GFnB6q1YgFvVxNAk4IdMD2aFRy6NIQjPg@nongnu.org X-Gm-Message-State: AOJu0YwB0BndqXO3EZq83SRM2r74KO9Hm+ZeJZ1HYvh+ZgyRp87JGXBa kmcEuvycjMlXe/4Lg1veQx4MS2W4LUGzrReUxh66Zx8ApxM7S6C87RDYEFjPeMU= X-Google-Smtp-Source: AGHT+IGLCvNrSlGLRK4tTQGeAufx9cVAlqWidYJfC1pDKzhqcf51xyMqLj7Hu7WTPTDCJTjWqk7VCg== X-Received: by 2002:a05:6512:3f13:b0:52e:9cc7:4461 with SMTP id 2adb3069b0e04-53b1a2f5445mr5904378e87.5.1729865581703; Fri, 25 Oct 2024 07:13:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 06/21] target/hppa: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:39 +0100 Message-Id: <20241025141254.2141506-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729865743042116600 Content-Type: text/plain; charset="utf-8" Set the 2-NaN propagation rule explicitly in env->fp_status. Really we only need to do this at CPU reset (after reset has zeroed out most of the CPU state struct, which typically includes fp_status fields). However target/hppa does not currently implement CPU reset at all, so leave a TODO comment to note that this could be moved if we ever do implement reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 6 ++++++ fpu/softfloat-specialize.c.inc | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index deaed2b65d1..0e44074ba82 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -49,6 +49,12 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) d =3D FIELD_EX32(shadow, FPSR, D); set_flush_to_zero(d, &env->fp_status); set_flush_inputs_to_zero(d, &env->fp_status); + + /* + * TODO: we only need to do this at CPU reset, but currently + * HPPA does note implement a CPU reset method at all... + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); } =20 void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index bbc3b70fa9d..4e51cf8d083 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -403,9 +403,9 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MI= PS) \ - || defined(TARGET_LOONGARCH64) + || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) g_assert_not_reached(); -#elif defined(TARGET_HPPA) || defined(TARGET_S390X) +#elif defined(TARGET_S390X) rule =3D float_2nan_prop_s_ab; #elif defined(TARGET_PPC) || defined(TARGET_M68K) /* --=20 2.34.1