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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865580; x=1730470380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oxpTyYZBHeinKYjs0KLdQZTFPyy0lkXjTFzf5hZbbFo=; b=CGBuWOgnxSzMdPYu0Rqs/8R6Pw7jLtC2XSAHErJjZbnCk75QLKtNPWZlryveWc0Ile 8V0uW9QhvS1i9bzN67Xkl3k8KZAzaZVGiLeC9Uy+KEp1uJ+O88fJM9nmTi7rgAXLnYl1 TuSuikrcAK7V12/E9k6/cpFuxzbC4gHCCKr3tYZAhjvywF6djZoX+qQg7UcVzoSA0LIT DqYKreg8VrONjmnCnNcS2Prx9ZsCD6nVzgLLMxNP+S46puGCq1w4Rvmzg8648k9Ze1sR I94Z22WNprp5IfK2t0L4oZvUnmdGlM2Ok2c/JpRBN0GPWncUOSMY0zA+dCPvAiAvVkFP R7cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865580; x=1730470380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oxpTyYZBHeinKYjs0KLdQZTFPyy0lkXjTFzf5hZbbFo=; b=G+B9gMOZs4tGVGMRPIb0rEzKxO0lvxZEGi4FnSyOzxDdcDDcVYkD6bAMqDp6J0aXqA 4DDb8uXwgHcey+AIL22r8rGHetFnmvNWkC+Px9AmhhNBTv9WVxu6cEx8VUYM2zOwgjJH e4NeGEBO7MraixUCuCHUIWCllPUlQjaZoCMLIox3K9JGR570uh82l31KiDyiGWNji4Bd apu37jyb0oSTNcxSTb5u3M7FpVdMs7EboSnsfAI+S7N0aKLGmXzvXaf/wqcpGnUntiU6 88S7H+x/mEDMNu20xjz5TrnGYhLG5fR6tvo56FXYvvPmpMSnlhfUjf66ib8CI+CdHGr4 F4oA== X-Forwarded-Encrypted: i=1; AJvYcCWXPWGFVi1/fCPJJs0bfVYrNA2bxGymiuoVLR3ujuTFSxM17Yf8NzDJJVt7GskVmGv0fjwCSLQWlncG@nongnu.org X-Gm-Message-State: AOJu0YyjQrWL02OHU7qXJZ6DkZYPh7IpRsJJV1D/utI4SmLWvh5MNUkR +S8GZEp3aHmLV80Vp8RcrlxMSiAY4nfvgbYBgbL3XYhLNhzc7DzK1/dDgGzGV/A= X-Google-Smtp-Source: AGHT+IFmo0A/cK7mxek7qVmenyHyXSHRnCM6HvcgZruK2l+y0NWBmuNTPj3PU5VnMspDYKzexoWsSw== X-Received: by 2002:a05:600c:511c:b0:42f:823d:dddd with SMTP id 5b1f17b1804b1-4318423b856mr71363435e9.27.1729865580016; Fri, 25 Oct 2024 07:13:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 04/21] target/mips: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:37 +0100 Message-Id: <20241025141254.2141506-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729865805267116600 Content-Type: text/plain; charset="utf-8" Set the 2-NaN propagation rule explicitly in the float_status words we use. For active_fpu.fp_status, we do this in a new fp_reset() function which mirrors the existing msa_reset() function in doing "first call restore to set the fp status parts that depend on CPU state, then set the fp status parts that are constant". Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/fpu_helper.h | 22 ++++++++++++++++++++++ target/mips/cpu.c | 2 +- target/mips/msa.c | 17 +++++++++++++++++ fpu/softfloat-specialize.c.inc | 18 ++---------------- 4 files changed, 42 insertions(+), 17 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index ad1116e8c10..7c3c7897b45 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -44,6 +44,28 @@ static inline void restore_fp_status(CPUMIPSState *env) restore_snan_bit_mode(env); } =20 +static inline void fp_reset(CPUMIPSState *env) +{ + restore_fp_status(env); + + /* + * According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always silenced before returning it. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, + &env->active_fpu.fp_status); +} + /* MSA */ =20 enum CPUMIPSMSADataFormat { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9724e71a5e0..d0a43b6d5c7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -407,9 +407,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) } =20 msa_reset(env); + fp_reset(env); =20 compute_hflags(env); - restore_fp_status(env); restore_pamask(env); cs->exception_index =3D EXCP_NONE; =20 diff --git a/target/mips/msa.c b/target/mips/msa.c index 61f1a9a5936..9dffc428f5c 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -49,6 +49,23 @@ void msa_reset(CPUMIPSState *env) set_float_detect_tininess(float_tininess_after_rounding, &env->active_tc.msa_fp_status); =20 + /* + * According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always silenced before returning it. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); =20 diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 70cd3628b54..c60b999aa3d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -402,24 +402,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, /* target didn't set the rule: fall back to old ifdef choices */ #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ - || defined(TARGET_TRICORE) || defined(TARGET_ARM) + || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MI= PS) g_assert_not_reached(); -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ +#elif defined(TARGET_HPPA) || \ defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) - /* - * According to MIPS specifications, if one of the two operands is - * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_silence_nan(). For qNaN inputs the specifications - * says: "When possible, this QNaN result is one of the operand QN= aN - * values." In practice it seems that most implementations choose - * the first operand if both operands are qNaN. In short this gives - * the following rules: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always silenced before returning it. - */ rule =3D float_2nan_prop_s_ab; #elif defined(TARGET_PPC) || defined(TARGET_M68K) /* --=20 2.34.1