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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865579; x=1730470379; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eGwvRk7TZZeC43moIVYb7p9RL4z/VBbvk9hnG7xUO3c=; b=csU1314FYbm4YozNi99R86y+c/GF1E2b4jGCRATbeBgb8HKVNk/fBvz2dnq02NeeyJ x5lT6UADsEWBGk4QGftmz4W+JLAm+07Giahp1Uv2GkaBgIeMmTmBONPRZaL4kT3Gz1ft nMmDAx3DCRTyDVPRP4ehLMLzFrH9GIerqqM6QLoRRXLzRdPktSQvNQRglwt9pe89LEvV zVl6uHiGJeNtQZTI7yGfOqA5+X6IbNRpd5BnoGilMDl70XxgL1kz1IYt+YRFopy+zWH2 Sx84BiLdoVSbl2kDPKECJcxZmDG47bll/3iP3JR8g5j4WdzbrLmgyT9OMadz4woJCBhX 3Ixw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865579; x=1730470379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eGwvRk7TZZeC43moIVYb7p9RL4z/VBbvk9hnG7xUO3c=; b=OQBDU9SHA6jhwzBTBHQizxRVSy5hO+wMnzlqJ8iKBYl+JlGAJrdG9nOOi1CrkA8FbC DJ2951nee4JZrIwJPavuLWaH0qMgrYSQm2fiRIFuNSEJrDIZXwT074l/DgzCjw5NhgYV F9EURcGFVl7hePY/5Ujdgk59gghuCn7Um/0u7Pt52rLsVGPH7HIlkcACQ4ol6ofmid08 Vrl3oTRz4jx1z/scm5DQpupkBaREKWFpVDxGon7TwDYRHqugq4RfWM2LCDsGUb9/3kSb +LEdad67TvrvCC5029HdDHjKhlCpVxUNGISUl8d8V7PMnmNbAykUM7282/AILQIq3w3N QWbg== X-Forwarded-Encrypted: i=1; AJvYcCUcxax5989PYRc+b2CzWfIysqhLb0R2C7xR9kvg5bYzn7zNYlC+BPEm+leqOZP13NtNkmc6oFsNQxlg@nongnu.org X-Gm-Message-State: AOJu0YzalOeLZIsaaOAg6zJQESb8nTA4RaM/oJl5QYWmjGEHMdHrnps6 q/fi4Bt11CQ/0kZvYHJgA9BycBUgi69n5QYR7ouT73bD6nsUQWCbzynMifo9Gm8= X-Google-Smtp-Source: AGHT+IEYimKNM/5+v3TTeeUBvxWOef5wpaX97b0yuiLjdVPgKthFZTkVWfIVxbwFrprYwlrLlBD4eA== X-Received: by 2002:a05:600c:1f09:b0:426:59fe:ac27 with SMTP id 5b1f17b1804b1-43184241cc5mr111818875e9.26.1729865579076; Fri, 25 Oct 2024 07:12:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 03/21] target/arm: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:36 +0100 Message-Id: <20241025141254.2141506-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729865696789116600 Content-Type: text/plain; charset="utf-8" Set the 2-NaN propagation rule explicitly in the float_status words we use. We wrap this plus the pre-existing setting of the tininess-before-rounding flag in a new function arm_set_default_fp_behaviours() to avoid repetition, since we have a lot of float_status words at this point. The situation with FPA11 emulation in linux-user is a little odd, and arguably "correct" behaviour there would be to exactly match a real Linux kernel's FPA11 emulation. However FPA11 emulation is essentially dead at this point and so it seems better to continue with QEMU's current behaviour and leave a comment describing the situation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/arm/nwfpe/fpa11.c | 18 ++++++++++++++++++ target/arm/cpu.c | 25 +++++++++++++++++-------- fpu/softfloat-specialize.c.inc | 13 ++----------- 3 files changed, 37 insertions(+), 19 deletions(-) diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index 9a93610d245..8356beb52c6 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -51,6 +51,24 @@ void resetFPA11(void) #ifdef MAINTAIN_FPCR fpa11->fpcr =3D MASK_RESET; #endif + + /* + * Real FPA11 hardware does not handle NaNs, but always takes an + * exception for them to be software-emulated (ARM7500FE datasheet + * section 10.4). There is no documented architectural requirement + * for NaN propagation rules and it will depend on how the OS + * level software emulation opted to do it. We here use prop_s_ab + * which matches the later VFP hardware choice and how QEMU's + * fpa11 emulation has worked in the past. The real Linux kernel + * does something slightly different: arch/arm/nwfpe/softfloat-specialize + * propagateFloat64NaN() has the curious behaviour that it prefers + * the QNaN over the SNaN, but if both are QNaN it picks A and + * if both are SNaN it picks B. In theory we could add this as + * a NaN propagation rule, but in practice FPA11 emulation is so + * close to totally dead that it's not worth trying to match it at + * this late date. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); } =20 void SetRoundingMode(const unsigned int opcode) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1320fd8c8fe..2fd286972a9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -168,6 +168,18 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELCha= ngeHookFn *hook, QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); } =20 +/* + * Set the float_status behaviour to match the Arm defaults: + * * tininess-before-rounding + * * 2-input NaN propagation prefers SNaN over QNaN, and then + * operand A over operand B (see FPProcessNaNs() pseudocode) + */ +static void arm_set_default_fp_behaviours(float_status *s) +{ + set_float_detect_tininess(float_tininess_before_rounding, s); + set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -549,14 +561,11 @@ static void arm_cpu_reset_hold(Object *obj, ResetType= type) set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.fp_status); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.standard_fp_status); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.fp_status_f16); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.standard_fp_status_f16); + arm_set_default_fp_behaviours(&env->vfp.fp_status); + arm_set_default_fp_behaviours(&env->vfp.standard_fp_status); + arm_set_default_fp_behaviours(&env->vfp.fp_status_f16); + arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16); + #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_arm_reset_vcpu(cpu); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index fae6794a152..70cd3628b54 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -402,19 +402,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, /* target didn't set the rule: fall back to old ifdef choices */ #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ - || defined(TARGET_TRICORE) + || defined(TARGET_TRICORE) || defined(TARGET_ARM) g_assert_not_reached(); -#elif defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) = || \ +#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) - /* - * ARM mandated NaN propagation rules (see FPProcessNaNs()), take - * the first of: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always quietened before returning it. - */ /* * According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in --=20 2.34.1