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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851710; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qvibL5FsKsRjUbXsu0htnvW3wkSS5Q2NsoKUwT3D8Gw=; b=HunqMY4etpRXin5k3n1LvNc5kjkQVJvS99RFljRVJPAg/peeyTFAxWUSTjml8b4SfXuTLc v1dMPk4g3eHeoXSghZwi2fy7MLvVuUr6a0cGUkvm30jTXvSXXEF1NBDk/mTf0in4awQrw2 PDahjjd+pedK6VqNsNT1iHzu3OpIJF4= X-MC-Unique: Yi9TIWwZNQONS9uQhZxKLg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 14/21] arm/cpu: Add sysreg generation scripts Date: Fri, 25 Oct 2024 12:17:33 +0200 Message-ID: <20241025101959.601048-15-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce scripts that automate the generation of system register definitions from a given linux source tree arch/arm64/tools/sysreg. Invocation of ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE in scripts directory do generate 2 qemu files: - target/arm/cpu-sysreg-properties.c - target/arm/cpu-sysregs.h cpu-sysregs.h creates defined for all system registers. However cpu-sysreg-properties.c only cares about feature ID registers. update-aarch64-sysreg-code.sh calls two awk scripts. gen-cpu-sysreg-properties.awk is inherited from kernel arch/arm64/tools/gen-sysreg.awk. All credits to Mark Rutland the original author of this script. Signed-off-by: Eric Auger --- scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++++++++++++++++ scripts/gen-cpu-sysregs-header.awk | 47 ++++ scripts/update-aarch64-sysreg-code.sh | 27 +++ 3 files changed, 399 insertions(+) create mode 100755 scripts/gen-cpu-sysreg-properties.awk create mode 100755 scripts/gen-cpu-sysregs-header.awk create mode 100755 scripts/update-aarch64-sysreg-code.sh diff --git a/scripts/gen-cpu-sysreg-properties.awk b/scripts/gen-cpu-sysreg= -properties.awk new file mode 100755 index 0000000000..b0ed55e059 --- /dev/null +++ b/scripts/gen-cpu-sysreg-properties.awk @@ -0,0 +1,325 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# gen-sysreg.awk: arm64 sysreg header generator +# +# Usage: awk -f gen-custom-sysreg.awk $LINUX_PATH/arch/arm64/tools/sysreg + +function block_current() { + return __current_block[__current_block_depth]; +} + +# Log an error and terminate +function fatal(msg) { + print "Error at " NR ": " msg > "/dev/stderr" + + printf "Current block nesting:" + + for (i =3D 0; i <=3D __current_block_depth; i++) { + printf " " __current_block[i] + } + printf "\n" + + exit 1 +} + +# Enter a new block, setting the active block to @block +function block_push(block) { + __current_block[++__current_block_depth] =3D block +} + +# Exit a block, setting the active block to the parent block +function block_pop() { + if (__current_block_depth =3D=3D 0) + fatal("error: block_pop() in root block") + + __current_block_depth--; +} + +# Sanity check the number of records for a field makes sense. If not, prod= uce +# an error and terminate. +function expect_fields(nf) { + if (NF !=3D nf) + fatal(NF " fields found where " nf " expected") +} + +# Print a CPP macro definition, padded with spaces so that the macro bodies +# line up in a column +function define(name, val) { + printf "%-56s%s\n", "#define " name, val +} + +# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field +function define_field(reg, field, msb, lsb, idreg) { + if (idreg) + print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "= msb");" +} + +# Print a field _SIGNED definition for a field +function define_field_sign(reg, field, sign, idreg) { + if (idreg) + print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "= msb");" +} + +# Parse a "[:]" string into the global variables @msb and @lsb +function parse_bitdef(reg, field, bitdef, _bits) +{ + if (bitdef ~ /^[0-9]+$/) { + msb =3D bitdef + lsb =3D bitdef + } else if (split(bitdef, _bits, ":") =3D=3D 2) { + msb =3D _bits[1] + lsb =3D _bits[2] + } else { + fatal("invalid bit-range definition '" bitdef "'") + } + + + if (msb !=3D next_bit) + fatal(reg "." field " starts at " msb " not " next_bit) + if (63 < msb || msb < 0) + fatal(reg "." field " invalid high bit in '" bitdef "'") + if (63 < lsb || lsb < 0) + fatal(reg "." field " invalid low bit in '" bitdef "'") + if (msb < lsb) + fatal(reg "." field " invalid bit-range '" bitdef "'") + if (low > high) + fatal(reg "." field " has invalid range " high "-" low) + + next_bit =3D lsb - 1 +} + +BEGIN { + print "#include \"cpu-custom.h\"" + print "" + print "ARM64SysReg arm64_id_regs[NR_ID_REGS];" + print "" + print "void initialize_cpu_sysreg_properties(void)" + print "{" + print " memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NR_ID_RE= GS);" + print "" + + __current_block_depth =3D 0 + __current_block[__current_block_depth] =3D "Root" +} + +END { + if (__current_block_depth !=3D 0) + fatal("Missing terminator for " block_current() " block") + + print "}" +} + +# skip blank lines and comment lines +/^$/ { next } +/^[\t ]*#/ { next } + +/^SysregFields/ && block_current() =3D=3D "Root" { + block_push("SysregFields") + + expect_fields(2) + + reg =3D $2 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + next_bit =3D 63 + + next +} + +/^EndSysregFields/ && block_current() =3D=3D "SysregFields" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + reg =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + block_pop() + next +} + +/^Sysreg/ && block_current() =3D=3D "Root" { + block_push("Sysreg") + + expect_fields(7) + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + if (op0 =3D=3D 3 && (op1>=3D0 && op1<=3D3) && crn=3D=3D0 && (crm>=3D0 && = crm<=3D7) && (op2>=3D0 && op2<=3D7)) { + idreg =3D 1 + } else { + idreg =3D 0 + } + + if (idreg =3D=3D 1) { + print " /* "reg" */" + print " ARM64SysReg *"reg" =3D arm64_sysreg_get("op0", "op1", "crn"= , "crm", "op2");" + print " "reg"->name =3D \""reg"\";" + } + + next_bit =3D 63 + + next +} + +/^EndSysreg/ && block_current() =3D=3D "Sysreg" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + reg =3D null + op0 =3D null + op1 =3D null + crn =3D null + crm =3D null + op2 =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + if (idreg=3D=3D1) + print "" + block_pop() + next +} + +# Currently this is effectivey a comment, in future we may want to emit +# defines for the fields. +/^Fields/ && block_current() =3D=3D "Sysreg" { + expect_fields(2) + + if (next_bit !=3D 63) + fatal("Some fields already defined for " reg) + + print "/* For " reg " fields see " $2 " */" + print "" + + next_bit =3D 0 + res0 =3D null + res1 =3D null + unkn =3D null + + next +} + + +/^Res0/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "RES0", $2) + field =3D "RES0_" msb "_" lsb + + res0 =3D res0 " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Res1/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "RES1", $2) + field =3D "RES1_" msb "_" lsb + + res1 =3D res1 " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Unkn/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "UNKN", $2) + field =3D "UNKN_" msb "_" lsb + + unkn =3D unkn " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Field/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sy= sregFields") { + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + + define_field(reg, field, msb, lsb, idreg) + + next +} + +/^Raz/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sysr= egFields") { + expect_fields(2) + parse_bitdef(reg, field, $2) + + next +} + +/^SignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + define_field_sign(reg, field, "true", idreg) + + next +} + +/^UnsignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + #define_field_sign(reg, field, "false", idreg) + + next +} + +/^Enum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + + next +} + +/^EndEnum/ && block_current() =3D=3D "Enum" { + + field =3D null + msb =3D null + lsb =3D null + + block_pop() + next +} + +/0b[01]+/ && block_current() =3D=3D "Enum" { + expect_fields(2) + val =3D $1 + name =3D $2 + + next +} + +# Any lines not handled by previous rules are unexpected +{ + fatal("unhandled statement") +} diff --git a/scripts/gen-cpu-sysregs-header.awk b/scripts/gen-cpu-sysregs-h= eader.awk new file mode 100755 index 0000000000..cdad686a53 --- /dev/null +++ b/scripts/gen-cpu-sysregs-header.awk @@ -0,0 +1,47 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# gen-sysreg.awk: arm64 sysreg header generator +# +# Usage: awk -f gen-custom-sysreg.awk $LINUX_PATH/arch/arm64/tools/sysreg + +# Sanity check the number of records for a field makes sense. If not, prod= uce +# an error and terminate. + +# Print a CPP macro definition, padded with spaces so that the macro bodies +# line up in a column +function define(name, val) { + printf "%-56s%s\n", "#define " name, val +} + +BEGIN { + print "#ifndef ARM_CPU_SYSREGS_H" + print "#define ARM_CPU_SYSREGS_H" + print "" + print "/* Generated file - do not edit */" + print "" +} END { + print "" + print "#endif /* ARM_CPU_SYSREGS_H */" +} + +# skip blank lines and comment lines +/^$/ { next } +/^[\t ]*#/ { next } + +/^Sysreg\t/ || /^Sysreg /{ + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") + next +} + +{ + /* skip all other lines */ + next +} diff --git a/scripts/update-aarch64-sysreg-code.sh b/scripts/update-aarch64= -sysreg-code.sh new file mode 100755 index 0000000000..e1fe40308b --- /dev/null +++ b/scripts/update-aarch64-sysreg-code.sh @@ -0,0 +1,27 @@ +#!/bin/sh -e +# +# Update target/arm/cpu-sysreg-properties.c and target/arm/cpu-sysregs.h +# from a linux source tree (arch/arm64/tools/sysreg) +# +# Copyright Red Hat, Inc. 2024 +# +# Authors: +# Eric Auger +# + +linux=3D"$1" +output=3D"$PWD" + +if [ -z "$linux" ] || ! [ -d "$linux" ]; then + cat << EOF +usage: update-aarch64-sysreg-code.sh LINUX_PATH + +LINUX_PATH Linux kernel directory to obtain the headers from +EOF + exit 1 +fi + +awk -f gen-cpu-sysregs-header.awk \ + $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysregs.h +awk -f gen-cpu-sysreg-properties.awk \ + $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysreg-propertie= s.c --=20 2.41.0