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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851721; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kp5QFl0T+y2RN+mj0Xap6zvqN21krl+Kxh65E9f4CQI=; b=ZB9HrRlsEaKaO6yRm9rX8qa5mWi+NAo01bujTK1xDexBROaCA3cWY9501aUWwLIpvRSE7x XvreA4ABsjtZo8Uzf9mPp1UQiNAU8tLgP5QTeKsob1Xsp3DtdUY/Y16htJSV1PQFFj2EQF d1il5YvNFEn5nreCM6FqDJLeH+KWfd4= X-MC-Unique: vN9ycNIOMZenEaTWGsnKyw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 01/21] kvm: kvm_get_writable_id_regs Date: Fri, 25 Oct 2024 12:17:20 +0200 Message-ID: <20241025101959.601048-2-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Add an helper to retrieve the writable id reg bitmask. The status of the query is stored in the CPU struct so that an an error, if any, can be reported on vcpu realize(). Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu.h | 19 +++++++++++++++++++ target/arm/kvm_arm.h | 7 +++++++ target/arm/kvm.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d8eb986a04..1493b35d99 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -821,6 +821,19 @@ typedef struct { uint32_t map, init, supported; } ARMVQMap; =20 +typedef enum ARMIdRegsState { + WRITABLE_ID_REGS_UNKNOWN, + WRITABLE_ID_REGS_NOT_DISCOVERABLE, + WRITABLE_ID_REGS_FAILED, + WRITABLE_ID_REGS_AVAIL, +} ARMIdRegsState; + +#define NR_ID_REGS (3 * 8 * 8) + +typedef struct IdRegMap { + uint64_t regs[NR_ID_REGS]; +} IdRegMap; + /** * ARMCPU: * @env: #CPUARMState @@ -960,6 +973,12 @@ struct ArchCPU { */ bool host_cpu_probe_failed; =20 + /* + * state of writable id regs query used to report an error, if any, + * on KVM custom vcpu model realize + */ + ARMIdRegsState writable_id_regs; + /* QOM property to indicate we should use the back-compat CNTFRQ defau= lt */ bool backcompat_cntfrq; =20 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index cfaa0d9bc7..9868065277 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,6 +214,8 @@ void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa); =20 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); =20 +int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idregmap); + #else =20 /* @@ -235,6 +237,11 @@ static inline bool kvm_arm_sve_supported(void) return false; } =20 +static inline int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idre= gmap) +{ + return -ENOSYS; +} + /* * These functions should never actually be called without KVM support. */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 70f79eda33..be98f8be18 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -47,6 +47,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = =3D { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; +static int cap_writable_id_regs; =20 /** * ARMHostCPUFeatures: information about the host CPU (identified @@ -478,6 +479,37 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features =3D arm_host_cpu_features.features; } =20 +int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idregmap) +{ + struct reg_mask_range range =3D { + .range =3D 0, /* up to now only a single range is supported */ + .addr =3D (uint64_t)idregmap, + }; + int ret; + + if (!kvm_enabled()) { + cpu->writable_id_regs =3D WRITABLE_ID_REGS_NOT_DISCOVERABLE; + return -ENOSYS; + } + + cap_writable_id_regs =3D + kvm_check_extension(kvm_state, KVM_CAP_ARM_SUPPORTED_REG_MASK_RANG= ES); + + if (!cap_writable_id_regs || + !(cap_writable_id_regs & (1 << KVM_ARM_FEATURE_ID_RANGE))) { + cpu->writable_id_regs =3D WRITABLE_ID_REGS_NOT_DISCOVERABLE; + return -ENOSYS; + } + + ret =3D kvm_vm_ioctl(kvm_state, KVM_ARM_GET_REG_WRITABLE_MASKS, &range= ); + if (ret) { + cpu->writable_id_regs =3D WRITABLE_ID_REGS_FAILED; + return ret; + } + cpu->writable_id_regs =3D WRITABLE_ID_REGS_AVAIL; + return ret; +} + static bool kvm_no_adjvtime_get(Object *obj, Error **errp) { return !ARM_CPU(obj)->kvm_adjvtime; --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851789; cv=none; d=zohomail.com; s=zohoarc; b=O2TL6GD75Nb6vLhSjMyalpc36nX4/h4OkPt3JO1hHRC3DRxHYmY6D1QO883ciZv/I9vzI7+ImwuY8LSwwl0PEuPn/GEHACLbPvLkCi9/p0rmVPkXAtMF9Hc4IgvZFwh+aiGrjB0fhzyUVVwYUEd1RIRhbi3I9RNqQRzVApl1qaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729851789; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 25 Oct 2024 10:20:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851721; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ky3ThRkvDhjr0upkbEECwN+3U+A5A3WcAWKqNWydsmA=; b=LmLvFvqHQhoDWUo+SIt/n8mIBuabLi27adVOEr4QXlFKG73dvUabt4CYjUp1dw6Qjm1PEX QWeigorMfT+8l202QX5c1E2PZMkGXyqDmPpBu8rkn4sqcHvGBBlNqAGXN1qlmhCqm7vJms xNEJSuOr0EJHf5V+ZDp45ziMoMpSI54= X-MC-Unique: ZohcQP7aM26-5wtACeHH9g-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 02/21] arm/cpu: Add sysreg definitions in cpu-sysegs.h Date: Fri, 25 Oct 2024 12:17:21 +0200 Message-ID: <20241025101959.601048-3-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This new header contains macros that define aarch64 regiters. In a subsequent patche, this will be replaced by a more exhaustive version that will be generated from linux arch/arm64/tools/sysreg file. Those macros are sufficient to migrate the storage of those ID regs from named fields in isar struct to an array cell. Signed-off-by: Eric Auger --- target/arm/cpu-sysregs.h | 42 +++++++++++++++++++++++++++++++ target/arm/cpu.h | 54 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 target/arm/cpu-sysregs.h diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h new file mode 100644 index 0000000000..f4b63a3af7 --- /dev/null +++ b/target/arm/cpu-sysregs.h @@ -0,0 +1,42 @@ +#ifndef ARM_CPU_SYSREGS_H +#define ARM_CPU_SYSREGS_H + +/* to be generated */ + +#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4= , 0) +#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4= , 1) +#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4= , 5) +#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5= , 0) +#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5= , 1) +#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6= , 0) +#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6= , 1) +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6= , 2) +#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7= , 0) +#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7= , 1) +#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7= , 2) +#define SYS_ID_AA64MMFR3_EL1 sys_reg(3, 0, 0, 7= , 3) + +#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1= , 0) +#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1= , 1) +#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1= , 2) +#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1= , 4) +#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1= , 5) +#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1= , 6) +#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1= , 7) +#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2= , 0) +#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2= , 1) +#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2= , 2) +#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2= , 3) +#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2= , 4) +#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2= , 5) +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2= , 6) +#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2= , 7) +#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3= , 0) +#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3= , 1) +#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3= , 2) +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3= , 4) +#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3= , 5) +#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3= , 6) +#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4= , 4) + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1493b35d99..0491a482f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -144,6 +144,14 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 +typedef struct ARMSysReg { + int op0; + int op1; + int crn; + int crm; + int op2; +} ARMSysReg; + /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -834,6 +842,51 @@ typedef struct IdRegMap { uint64_t regs[NR_ID_REGS]; } IdRegMap; =20 +#define ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 =3D (op1) & 3; \ + __op1 -=3D (__op1 =3D=3D 3); = \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + +static inline uint64_t _get_idreg(const IdRegMap *map, ARMSysReg sr) +{ + int index =3D ARM_FEATURE_ID_RANGE_IDX(sr.op0, sr.op1, sr.crn, sr.crm,= sr.op2); + + return map->regs[index]; +} + +static inline void _set_idreg(IdRegMap *map, ARMSysReg sr, uint64_t value) +{ + int index =3D ARM_FEATURE_ID_RANGE_IDX(sr.op0, sr.op1, sr.crn, sr.crm,= sr.op2); + + map->regs[index] =3D value; +} + +/* REG is ID_XXX */ +#define FIELD_DP64_IDREG(MAP, REG, FIELD, VALUE) \ +{ \ +uint64_t regval =3D _get_idreg(MAP, SYS_ ## REG ## _EL1); \ +regval =3D FIELD_DP64(regval, REG, FIELD, VALUE); \ +_set_idreg(MAP, SYS_ ## REG ## _EL1, regval); \ +} + +#define FIELD_EX64_IDREG(MAP, REG, FIELD) \ +FIELD_EX64(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ + +#define SET_IDREG(MAP, REG, VALUE) \ +_set_idreg(MAP, SYS_ ## REG ## _EL1, VALUE) + +#define GET_IDREG(MAP, REG) \ +_get_idreg(MAP, SYS_ ## REG ## _EL1) + +static inline ARMSysReg sys_reg(int op0, int op1, int crn, int crm, int op= 2) +{ + ARMSysReg sr =3D {op0, op1, crn, crm, op2}; + + return sr; +} + /** * ARMCPU: * @env: #CPUARMState @@ -1043,6 +1096,7 @@ struct ArchCPU { uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; + IdRegMap idregs; } isar; uint64_t midr; uint32_t revidr; --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=eSdMfeFt1lJCM93pd5/q1sWsGwYFN+aWb2incI3k+lNWcCz/xKSgP/ktlTHjgiOV8eqaVz OuV1mfM8frVYG7DSxEJdGxZ0gwugzzLjF2O53x10HrnbLpFrOaRMV9QDsOcsj71eOvGTFM pPbdK9Y1IwbGbJyfpu9GLFIj4gVjPhA= X-MC-Unique: bUx_ipttNZmNQbpxmzSX3Q-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 03/21] arm/cpu: Store aa64isar0 into the idregs arrays Date: Fri, 25 Oct 2024 12:17:22 +0200 Message-ID: <20241025101959.601048-4-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 57 ++++++++++++++++++++------------------- target/arm/cpu.h | 2 -- target/arm/cpu.c | 13 ++++----- target/arm/cpu64.c | 8 +++--- target/arm/helper.c | 6 +++-- target/arm/kvm.c | 20 +++++++++++--- target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------ 7 files changed, 86 insertions(+), 64 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index c59ca104fe..4eb29d205c 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -21,6 +21,7 @@ #define TARGET_ARM_FEATURES_H =20 #include "hw/registerfields.h" +#include "cpu-sysregs.h" =20 /* * Naming convention for isar_feature functions: @@ -375,92 +376,92 @@ static inline bool isar_feature_aa32_doublelock(const= ARMISARegisters *id) */ static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, AES) > 1; } =20 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA2) > 1; } =20 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, RDM) !=3D 0; } =20 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SM3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, DP) !=3D 0; } =20 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, FHM) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TS) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TS) >=3D 2; } =20 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, RNDR) !=3D 0; } =20 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TLB) !=3D 0; } =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) @@ -901,52 +902,52 @@ static inline bool isar_feature_aa64_doublelock(const= ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, SVEVER) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *= id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, AES) >=3D 2; } =20 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, BFLOAT16) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, F32MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, F64MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0491a482f0..aee8dfe439 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1082,7 +1082,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64isar2; uint64_t id_aa64pfr0; @@ -1093,7 +1092,6 @@ struct ArchCPU { uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; - uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; IdRegMap idregs; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 14d4eca127..9521eed586 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1967,6 +1967,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); ARMCPU *cpu =3D ARM_CPU(dev); + IdRegMap *idregs =3D &cpu->isar.idregs; ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(dev); CPUARMState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -2168,7 +2169,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 unset_feature(env, ARM_FEATURE_NEON); =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(idregs, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); @@ -2176,7 +2177,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(idregs, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); @@ -2221,13 +2222,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); - cpu->isar.id_aa64isar0 =3D t; + FIELD_DP64_IDREG(idregs, ID_AA64ISAR0, FHM, 0); =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); - cpu->isar.id_aa64isar1 =3D t; + FIELD_DP64_IDREG(idregs, ID_AA64ISAR1, FRINTTS, 0); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 262a1d6c0b..1451b3e1b3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -113,7 +113,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * SVE is disabled and so are all vector lengths. Good. * Disable all SVE extensions as well. */ - cpu->isar.id_aa64zfr0 =3D 0; + SET_IDREG(&cpu->isar.idregs, ID_AA64ZFR0, 0); return; } =20 @@ -598,6 +598,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -635,7 +636,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -656,6 +657,7 @@ static void aarch64_a57_initfn(Object *obj) static void aarch64_a53_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -693,7 +695,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; diff --git a/target/arm/helper.c b/target/arm/helper.c index ce31957235..8eae775d87 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8702,6 +8702,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ CPUARMState *env =3D &cpu->env; + IdRegMap *idregs =3D &cpu->isar.idregs; + if (arm_feature(env, ARM_FEATURE_M)) { /* M profile has no coprocessor registers */ return; @@ -8893,7 +8895,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64zfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64ZFR0)}, { .name =3D "ID_AA64SMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8953,7 +8955,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar0 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64ISAR0)}, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index be98f8be18..7a2087c195 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -26,6 +26,7 @@ #include "sysemu/kvm_int.h" #include "kvm_arm.h" #include "cpu.h" +#include "cpu-sysregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -230,6 +231,18 @@ static bool kvm_arm_pauth_supported(void) kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); } =20 +/* read a 64b sysreg value and store it in the idregs */ +static int get_host_cpu_reg64(int fd, ARMHostCPUFeatures *ahcf, ARMSysReg = sr) +{ + int index =3D KVM_ARM_FEATURE_ID_RANGE_IDX(sr.op0, sr.op1, sr.crn, sr.= crm, sr.op2); + uint64_t *reg =3D &ahcf->isar.idregs.regs[index]; + int ret; + + ret =3D read_sys_reg64(fd, reg, + ARM64_SYS_REG(sr.op0, sr.op1, sr.crn, sr.crm, sr.= op2)); + return ret; +} + static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -289,6 +302,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) =20 ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; + int fd =3D fdarray[2]; =20 err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, ARM64_SYS_REG(3, 0, 0, 4, 0)); @@ -320,8 +334,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 5, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, @@ -430,8 +443,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) * enabled SVE support, which resulted in an error rather than= RAZ. * So only read the register if we set KVM_ARM_VCPU_SVE above. */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ZFR0_EL1); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fe232eb306..1b25ca4382 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -58,6 +58,7 @@ static uint64_t make_ccsidr64(unsigned assoc, unsigned li= nesize, static void aarch64_a35_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a35"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -92,7 +93,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64pfr1 =3D 0; cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64isar1 =3D 0; cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; @@ -227,6 +228,7 @@ static Property arm_cpu_lpa2_property =3D static void aarch64_a55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a55"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -244,7 +246,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -296,6 +298,7 @@ static void aarch64_a55_initfn(Object *obj) static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -331,7 +334,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -352,6 +355,7 @@ static void aarch64_a72_initfn(Object *obj) static void aarch64_a76_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a76"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -369,7 +373,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -422,6 +426,7 @@ static void aarch64_a76_initfn(Object *obj) static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,a64fx"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -445,9 +450,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + SET_IDREG(idregs, ID_AA64ISAR0, 0x0000000010211120); cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + SET_IDREG(idregs, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ @@ -592,6 +597,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,neoverse-n1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -609,7 +615,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -664,6 +670,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) static void aarch64_neoverse_v1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,neoverse-v1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -684,7 +691,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->id_aa64afr1 =3D 0x00000000; cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; - cpu->isar.id_aa64isar0 =3D 0x1011111110212120ull; /* with FEAT_RNG */ + SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_R= NG */ cpu->isar.id_aa64isar1 =3D 0x0111000001211032ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -740,7 +747,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; =20 /* From 3.7.5 ID_AA64ZFR0_EL1 */ - cpu->isar.id_aa64zfr0 =3D 0x0000100000100000; + SET_IDREG(idregs, ID_AA64ZFR0, 0x0000100000100000); cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1); /* 256bit */ =20 @@ -887,6 +894,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] =3D { static void aarch64_a710_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a710"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -924,12 +932,12 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto= */ cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -985,6 +993,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] =3D { static void aarch64_neoverse_n2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,neoverse-n2"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -1022,12 +1031,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x1221111110212120ull; /* with Crypto and F= EAT_RNG */ + SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto= and FEAT_RNG */ cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) void aarch64_max_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; uint64_t t; uint32_t u; =20 @@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(idregs, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ @@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(idregs, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ @@ -1240,7 +1250,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ cpu->isar.id_aa64mmfr3 =3D t; =20 - t =3D cpu->isar.id_aa64zfr0; + t =3D GET_IDREG(idregs, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ @@ -1250,7 +1260,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ - cpu->isar.id_aa64zfr0 =3D t; + SET_IDREG(idregs, ID_AA64ZFR0, t); =20 t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 38 +++++++++++++++++++------------------- target/arm/cpu.h | 2 -- target/arm/cpu.c | 9 +++------ target/arm/cpu64.c | 9 +++++---- target/arm/helper.c | 4 ++-- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu64.c | 24 ++++++++++++------------ 7 files changed, 43 insertions(+), 49 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4eb29d205c..de571b520f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -466,12 +466,12 @@ static inline bool isar_feature_aa64_tlbios(const ARM= ISARegisters *id) =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, FCMA) !=3D 0; } =20 /* @@ -495,9 +495,9 @@ isar_feature_pauth_feature(const ARMISARegisters *id) * Architecturally, only one of {APA,API,APA3} may be active (non-zero) * and the other two must be zero. Thus we may avoid conditionals. */ - return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) | - FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) | - FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3)); + return (FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, APA) | + FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, API) | + FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, APA3)); } =20 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) @@ -515,7 +515,7 @@ static inline bool isar_feature_aa64_pauth_qarma5(const= ARMISARegisters *id) * Return true if pauth is enabled with the architected QARMA5 algorit= hm. * QEMU will always enable or disable both APA and GPA. */ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, APA) !=3D 0; } =20 static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *i= d) @@ -524,67 +524,67 @@ static inline bool isar_feature_aa64_pauth_qarma3(con= st ARMISARegisters *id) * Return true if pauth is enabled with the architected QARMA3 algorit= hm. * QEMU will always enable or disable both APA3 and GPA3. */ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, APA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, SB) !=3D 0; } =20 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, FRINTTS) !=3D 0; } =20 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, DPB) !=3D 0; } =20 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, DPB) >=3D 2; } =20 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, BF16) !=3D 0; } =20 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, LRCPC) !=3D 0; } =20 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, LRCPC) >=3D 2; } =20 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, WFXT) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, WFXT) >=3D 2; } =20 static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, BC) !=3D 0; } =20 static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); + return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, MOPS); } =20 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aee8dfe439..87df224121 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1082,8 +1082,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar1; - uint64_t id_aa64isar2; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9521eed586..a4b59b259c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2124,9 +2124,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); - cpu->isar.id_aa64isar1 =3D t; + FIELD_DP64_IDREG(idregs, ID_AA64ISAR1, JSCVT, 0); =20 t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); @@ -2179,11 +2177,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); SET_IDREG(idregs, ID_AA64ISAR0, t); =20 - t =3D cpu->isar.id_aa64isar1; + t =3D GET_IDREG(idregs, ID_AA64ISAR1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); - cpu->isar.id_aa64isar1 =3D t; + SET_IDREG(idregs, ID_AA64ISAR1, t); =20 t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); @@ -2219,7 +2217,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } =20 if (!cpu->has_neon && !cpu->has_vfp) { - uint64_t t; uint32_t u; =20 FIELD_DP64_IDREG(idregs, ID_AA64ISAR0, FHM, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1451b3e1b3..d16c7487ac 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -479,6 +479,7 @@ void aarch64_add_sme_properties(Object *obj) void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features =3D cpu_isar_feature(pauth_feature, cpu); + IdRegMap *idregs =3D &cpu->isar.idregs; uint64_t isar1, isar2; =20 /* @@ -489,13 +490,13 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) * * Begin by disabling all fields. */ - isar1 =3D cpu->isar.id_aa64isar1; + isar1 =3D GET_IDREG(idregs, ID_AA64ISAR1); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); =20 - isar2 =3D cpu->isar.id_aa64isar2; + isar2 =3D GET_IDREG(idregs, ID_AA64ISAR2); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); =20 @@ -542,8 +543,8 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } } =20 - cpu->isar.id_aa64isar1 =3D isar1; - cpu->isar.id_aa64isar2 =3D isar2; + SET_IDREG(idregs, ID_AA64ISAR1, isar1); + SET_IDREG(idregs, ID_AA64ISAR2, isar2); } =20 static Property arm_cpu_pauth_property =3D diff --git a/target/arm/helper.c b/target/arm/helper.c index 8eae775d87..209b7c22b6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8960,12 +8960,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar1 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64ISAR1)}, { .name =3D "ID_AA64ISAR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar2 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64ISAR2)}, { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7a2087c195..c30dc53622 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -335,10 +335,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, - ARM64_SYS_REG(3, 0, 0, 6, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, - ARM64_SYS_REG(3, 0, 0, 6, 2)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, ARM64_SYS_REG(3, 0, 0, 7, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 1b25ca4382..7be63f21a1 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -94,7 +94,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64isar1 =3D 0; + SET_IDREG(idregs, ID_AA64ISAR1, 0); cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; cpu->clidr =3D 0x0a200023; @@ -247,7 +247,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -374,7 +374,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -451,7 +451,7 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000000010211120); - cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ @@ -616,7 +616,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -692,7 +692,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_R= NG */ - cpu->isar.id_aa64isar1 =3D 0x0111000001211032ull; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0111000001211032ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; @@ -938,7 +938,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto= */ - cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0010111101211052ull); cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; @@ -1037,7 +1037,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto= and FEAT_RNG */ - cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; + SET_IDREG(idregs, ID_AA64ISAR1, 0x0011111101211052ull); cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; @@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ SET_IDREG(idregs, ID_AA64ISAR0, t); =20 - t =3D cpu->isar.id_aa64isar1; + t =3D GET_IDREG(idregs, ID_AA64ISAR1); t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 1); @@ -1173,13 +1173,13 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ - cpu->isar.id_aa64isar1 =3D t; + SET_IDREG(idregs, ID_AA64ISAR1, t); =20 - t =3D cpu->isar.id_aa64isar2; + t =3D GET_IDREG(idregs, ID_AA64ISAR2); t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); 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Fri, 25 Oct 2024 10:20:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gkibzcnB6clf7OmcuSAILk3dYeaUIpX/AS3GV2HV7Sg=; b=Ailgoskk+x9z7HE6diz38wEIqCckGrQAtKGwlCtttxemssDyWDO30AT0H/f41DCOGYwMUU CoCE35yj0qNwohN2wN+7gr6JmptEK9XM1r8D102Q0GQ9lnQ7gxli60UqUYfPbvVglj4BbK TXP8Ulwzi8ol/fy44baEg95Znc9fvGE= X-MC-Unique: gDVN1WiUOsabjshEosEhVA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 05/21] arm/cpu: Store aa64drf0/1 into the idregs array Date: Fri, 25 Oct 2024 12:17:24 +0200 Message-ID: <20241025101959.601048-6-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 40 ++++++++++++++++----------------- target/arm/cpu.h | 5 +++-- target/arm/cpu.c | 27 +++++++--------------- target/arm/cpu64.c | 14 ++++-------- target/arm/helper.c | 6 ++--- target/arm/kvm.c | 24 +++++++++----------- target/arm/tcg/cpu64.c | 47 ++++++++++++++++++--------------------- 7 files changed, 70 insertions(+), 93 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index de571b520f..5e195f117d 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -590,68 +590,68 @@ static inline bool isar_feature_aa64_mops(const ARMIS= ARegisters *id) static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) !=3D 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, FP) !=3D 0xf; } =20 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, FP) =3D=3D 1; } =20 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, EL0) >=3D 2; } =20 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, EL1) >=3D 2; } =20 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, EL2) >=3D 2; } =20 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, RAS) >=3D 2; } =20 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, SVE) !=3D 0; } =20 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, SEL2) !=3D 0; } =20 static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, RME) !=3D 0; } =20 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) { - int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + int key =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, CSV2); if (key >=3D 2) { return true; /* FEAT_CSV2_2 */ } if (key =3D=3D 1) { - key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + key =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, CSV2_FRAC); return key >=3D 2; /* FEAT_CSV2_1p2 */ } return false; @@ -659,37 +659,37 @@ static inline bool isar_feature_aa64_scxtnum(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, BT) !=3D 0; } =20 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, MTE) !=3D 0; } =20 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, MTE) >=3D 2; } =20 static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 3; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, MTE) >=3D 3; } =20 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, SME) !=3D 0; } =20 static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, NMI) !=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 87df224121..bebee2e694 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -874,6 +874,9 @@ _set_idreg(MAP, SYS_ ## REG ## _EL1, regval); = \ #define FIELD_EX64_IDREG(MAP, REG, FIELD) \ FIELD_EX64(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ =20 +#define FIELD_EX32_IDREG(MAP, REG, FIELD) \ +FIELD_EX32(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ + #define SET_IDREG(MAP, REG, VALUE) \ _set_idreg(MAP, SYS_ ## REG ## _EL1, VALUE) =20 @@ -1082,8 +1085,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64pfr0; - uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a4b59b259c..cbfb6df435 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2121,14 +2121,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!cpu->has_vfp) { - uint64_t t; uint32_t u; =20 FIELD_DP64_IDREG(idregs, ID_AA64ISAR1, JSCVT, 0); =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, FP, 0xf); =20 u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); @@ -2183,9 +2180,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); SET_IDREG(idregs, ID_AA64ISAR1, t); =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, ADVSIMD, 0xf); =20 u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); @@ -2327,12 +2322,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, EL3, 0); + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0); =20 /* Disable the realm management extension, which requires EL3. */ - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, RME, 0); + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, RME, 0); } =20 if (!cpu->has_el2) { @@ -2367,8 +2360,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the hypervisor feature bits in the processor feature * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, EL2, 0); + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL2, 0); cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, VIRTUALIZATION, 0); } @@ -2389,8 +2381,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * This matches Cortex-A710 BROADCASTMTE input being LOW. */ if (cpu->tag_memory =3D=3D NULL) { - cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); + FIELD_DP64_IDREG(idregs, ID_AA64PFR1, MTE, 1); } #endif } @@ -2429,13 +2420,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ - cpu->isar.id_aa64pfr0 =3D - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0); cpu->isar.id_pfr0 =3D FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ - cpu->isar.id_aa64pfr0 =3D - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); + FIELD_DP64_IDREG(idregs, ID_AA64PFR0, MPAM, 0); } =20 /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d16c7487ac..7dd458012a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -287,16 +287,13 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp) static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { error_setg(errp, "'sve' feature not supported by KVM on this host"= ); return; } =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64PFR0, SVE, value); } =20 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) @@ -347,11 +344,8 @@ static bool cpu_arm_get_sme(Object *obj, Error **errp) static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, value); - cpu->isar.id_aa64pfr1 =3D t; + FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64PFR1, SME, value); } =20 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) @@ -635,7 +629,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; @@ -694,7 +688,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 209b7c22b6..541bc27587 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7688,7 +7688,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; + uint64_t pfr0 =3D GET_IDREG(&cpu->isar.idregs, ID_AA64PFR0); =20 if (env->gicv3state) { pfr0 |=3D 1 << 24; @@ -8868,7 +8868,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_aa64pfr0 + .resetvalue =3D GET_IDREG(idregs, ID_AA64PFR0) #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa64_tid3, @@ -8880,7 +8880,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64pfr1}, + .resetvalue =3D GET_IDREG(idregs, ID_AA64PFR1)}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index c30dc53622..888b10213c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -304,8 +304,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ahcf->dtb_compatible =3D "arm,arm-v8"; int fd =3D fdarray[2]; =20 - err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, - ARM64_SYS_REG(3, 0, 0, 4, 0)); + err =3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1); if (unlikely(err < 0)) { /* * Before v4.15, the kernel only exposed a limited number of system @@ -323,11 +322,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * ??? Either of these sounds like too much effort just * to work around running a modern host kernel. */ - ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + SET_IDREG(&ahcf->isar.idregs, ID_AA64PFR0, 0x00000011); /* EL1&0, = AArch64 only */ err =3D 0; } else { - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, - ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, @@ -353,10 +351,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, - ARM64_SYS_REG(3, 0, 0, 1, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, - ARM64_SYS_REG(3, 0, 0, 1, 1)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, @@ -407,14 +403,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. * We only do this if the CPU supports AArch32 at EL1. */ - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); - int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + if (FIELD_EX32_IDREG(&ahcf->isar.idregs, ID_AA64PFR0, EL1) >=3D 2)= { + int wrps =3D FIELD_EX64_IDREG(&ahcf->isar.idregs, ID_AA64DFR0,= WRPS); + int brps =3D FIELD_EX64_IDREG(&ahcf->isar.idregs, ID_AA64DFR0,= BRPS); int ctx_cmps =3D - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + FIELD_EX64_IDREG(&ahcf->isar.idregs, ID_AA64DFR0, CTX_CMPS= ); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + !!FIELD_EX32_IDREG(&ahcf->isar.idregs, ID_AA64PFR0, EL3); uint32_t dbgdidr =3D 0; =20 dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7be63f21a1..b2a88a0ebd 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -89,8 +89,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar3 =3D 0x01112131; cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64pfr1 =3D 0; + SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); + SET_IDREG(idregs, ID_AA64PFR1, 0); cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); @@ -181,11 +181,8 @@ static bool cpu_arm_get_rme(Object *obj, Error **errp) static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, RME, value); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64PFR0, RME, value); } =20 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, @@ -251,8 +248,8 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x0000000010112222ull; - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull); + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -332,7 +329,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar3 =3D 0x01112131; cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; @@ -378,8 +375,8 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled i= n later */ + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -441,8 +438,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->revidr =3D 0x00000000; cpu->ctr =3D 0x86668006; cpu->reset_sctlr =3D 0x30000180; - cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + SET_IDREG(idregs, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensio= ns */ + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000000); cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; @@ -620,8 +617,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled i= n later */ + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -696,8 +693,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; - cpu->isar.id_aa64pfr0 =3D 0x1101110120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled i= n later */ + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; cpu->isar.id_isar0 =3D 0x02101110; @@ -930,8 +927,8 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; cpu->isar.id_pfr2 =3D 0x00000011; - cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled i= n later */ + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; @@ -1029,8 +1026,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; cpu->isar.id_pfr2 =3D 0x00000011; - cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled i= n later */ + SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; @@ -1181,7 +1178,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ SET_IDREG(idregs, ID_AA64ISAR2, t); =20 - t =3D cpu->isar.id_aa64pfr0; + t =3D GET_IDREG(idregs, ID_AA64PFR0); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ @@ -1190,9 +1187,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ - cpu->isar.id_aa64pfr0 =3D t; + SET_IDREG(idregs, ID_AA64PFR0, t); =20 - t =3D cpu->isar.id_aa64pfr1; + t =3D GET_IDREG(idregs, ID_AA64PFR1); t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* @@ -1205,7 +1202,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ - cpu->isar.id_aa64pfr1 =3D t; + SET_IDREG(idregs, ID_AA64PFR1, t); =20 t =3D cpu->isar.id_aa64mmfr0; t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=Ya4TcxOeNT0WzKozvi7fayC3ategenTElHasrBIC0u4AKIjsPA/gMr2H3dl/ozFnRbQzr/ SCN8XQv5t/XZK254ggC9ZzX+dpQLzefFNryfpWMfgreFF1vyr7rKD8N+YkJr7g2htWA6SW VMAp2yvxFXkl0jl6LyJgKU4KvogR01A= X-MC-Unique: sp7ST7OsNUi803pU5La1qw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 06/21] arm/cpu: Store aa64mmfr0-3 into the idregs array Date: Fri, 25 Oct 2024 12:17:25 +0200 Message-ID: <20241025101959.601048-7-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 70 +++++++++++++++++++-------------------- target/arm/cpu.h | 7 ++-- target/arm/cpu64.c | 8 ++--- target/arm/helper.c | 8 ++--- target/arm/kvm.c | 12 +++---- target/arm/ptw.c | 6 ++-- target/arm/tcg/cpu64.c | 64 +++++++++++++++++------------------ 7 files changed, 84 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5e195f117d..45f315df7b 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -694,182 +694,182 @@ static inline bool isar_feature_aa64_nmi(const ARMI= SARegisters *id) =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; + return FIELD_SEX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *= id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran4_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16) >=3D 2; } =20 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters = *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran16_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 0; + return FIELD_SEX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 1; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >=3D 0; + return FIELD_SEX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN64) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran4(id)); } =20 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran16(id)); } =20 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + unsigned t =3D FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN64_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); } =20 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, FGT) !=3D 0; } =20 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, ECV) > 0; } =20 static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, ECV) > 1; } =20 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, VH) !=3D 0; } =20 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, LO) !=3D 0; } =20 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, PAN) !=3D 0; } =20 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, PAN) >=3D 2; } =20 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 3; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, PAN) >=3D 3; } =20 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, HCX) !=3D 0; } =20 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, TIDCP1) !=3D 0; } =20 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, HAFDBS) !=3D 0; } =20 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, HAFDBS) >=3D 2; } =20 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, XNX) !=3D 0; } =20 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, UAO) !=3D 0; } =20 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, ST) !=3D 0; } =20 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, AT) !=3D 0; } =20 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, FWB) !=3D 0; } =20 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, IDS) !=3D 0; } =20 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 1; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, EVT) >=3D 1; } =20 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, EVT) >=3D 2; } =20 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, E0PD) !=3D 0; } =20 static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) !=3D 0; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, NV) !=3D 0; } =20 static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >=3D 2; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, NV) >=3D 2; } =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bebee2e694..419dfde638 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -874,6 +874,9 @@ _set_idreg(MAP, SYS_ ## REG ## _EL1, regval); = \ #define FIELD_EX64_IDREG(MAP, REG, FIELD) \ FIELD_EX64(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ =20 +#define FIELD_SEX64_IDREG(MAP, REG, FIELD) \ +FIELD_SEX64(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ + #define FIELD_EX32_IDREG(MAP, REG, FIELD) \ FIELD_EX32(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ =20 @@ -1085,10 +1088,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; - uint64_t id_aa64mmfr2; - uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7dd458012a..594778a031 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -582,12 +582,12 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) return; } =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(&cpu->isar.idregs, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2= */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2= */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, t); } =20 static void aarch64_a57_initfn(Object *obj) @@ -632,7 +632,7 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -691,7 +691,7 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + SET_IDREG(idregs, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; cpu->isar.dbgdevid1 =3D 0x1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 541bc27587..fa04383921 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8995,22 +8995,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64MMFR0)}, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr1 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64MMFR1) }, { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr2 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64MMFR2) }, { .name =3D "ID_AA64MMFR3_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr3 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64MMFR3) }, { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 888b10213c..c9b99bf5ee 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -335,14 +335,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, - ARM64_SYS_REG(3, 0, 0, 7, 3)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR0_EL1); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR1_EL1); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR2_EL1); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR3_EL1); =20 /* * Note that if AArch32 support is not present in the host, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4476b32ff5..dea4621352 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -104,7 +104,7 @@ unsigned int arm_pamax(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { unsigned int parange =3D - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, PARANGE); =20 /* * id_aa64mmfr0 is a read-only register so values outside of the @@ -312,7 +312,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, * physical address size is invalid. */ pps =3D FIELD_EX64(gpccr, GPCCR, PPS); - if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + if (pps > FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, PARANGE)) { goto fault_walk; } pps =3D pamax_map[pps]; @@ -1727,7 +1727,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * ID_AA64MMFR0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ - ps =3D FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps =3D FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, PARANGE); ps =3D MIN(ps, param.ps); assert(ps < ARRAY_SIZE(pamax_map)); outputsize =3D pamax_map[ps]; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b2a88a0ebd..64473fc3c7 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -95,8 +95,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64ISAR1, 0); - cpu->isar.id_aa64mmfr0 =3D 0x00101122; - cpu->isar.id_aa64mmfr1 =3D 0; + SET_IDREG(idregs, ID_AA64MMFR0, 0x00101122); + SET_IDREG(idregs, ID_AA64MMFR1, 0); cpu->clidr =3D 0x0a200023; cpu->dcz_blocksize =3D 4; =20 @@ -245,9 +245,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -332,7 +332,7 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -372,9 +372,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -444,9 +444,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000001122); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000011212100); + SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011); SET_IDREG(idregs, ID_AA64ISAR0, 0x0000000010211120); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000000000000000); @@ -614,9 +614,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -690,9 +690,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_R= NG */ SET_IDREG(idregs, ID_AA64ISAR1, 0x0111000001211032ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull), + SET_IDREG(idregs, ID_AA64MMFR2, 0x0220011102101011ull), SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -936,9 +936,9 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto= */ SET_IDREG(idregs, ID_AA64ISAR1, 0x0010111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000022200101122ull); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(idregs, ID_AA64MMFR2, 0x1221011110101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x000000049444c004ull; @@ -1035,9 +1035,9 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto= and FEAT_RNG */ SET_IDREG(idregs, ID_AA64ISAR1, 0x0011111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; + SET_IDREG(idregs, ID_AA64MMFR0, 0x0000022200101125ull); + SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(idregs, ID_AA64MMFR2, 0x1221011112101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x00000004b444c004ull; @@ -1204,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ SET_IDREG(idregs, ID_AA64PFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(idregs, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ @@ -1212,9 +1212,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(idregs, ID_AA64MMFR0, t); =20 - t =3D cpu->isar.id_aa64mmfr1; + t =3D GET_IDREG(idregs, ID_AA64MMFR1); t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ @@ -1225,9 +1225,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ - cpu->isar.id_aa64mmfr1 =3D t; + SET_IDREG(idregs, ID_AA64MMFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr2; + t =3D GET_IDREG(idregs, ID_AA64MMFR2); t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ @@ -1241,11 +1241,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ - cpu->isar.id_aa64mmfr2 =3D t; + SET_IDREG(idregs, ID_AA64MMFR2, t); =20 - t =3D cpu->isar.id_aa64mmfr3; - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - cpu->isar.id_aa64mmfr3 =3D t; + FIELD_DP64_IDREG(idregs, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_S= PEC */ =20 t =3D GET_IDREG(idregs, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851815; cv=none; d=zohomail.com; s=zohoarc; b=kiKqb3BVa/3QmSCSHJ1iS6uHpLEhyvss6q9TgPBs0daUxSvpv3QHvj1JPdvWO3YSk3IIxGLZesJ0FOVM+JwjLWwWQWFz2NDfDkjIIhd7BxW0nUTHR7acadQXoJ9bdRbqKKxjO6TVXqvKTBlBlTuYTY+qAaw0bJjYqI0/HBMk+M4= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.h | 2 -- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 15 +++++---------- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu64.c | 33 +++++++++++++++++---------------- 8 files changed, 39 insertions(+), 47 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 45f315df7b..9b0d5157bf 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -874,30 +874,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, DEBUGVER) >=3D 8; } =20 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >=3D 0; + return FIELD_SEX64_IDREG(&id->idregs, ID_AA64DFR0, DOUBLELOCK) >=3D 0; } =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 419dfde638..6954952d5f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1088,8 +1088,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; IdRegMap idregs; diff --git a/target/arm/internals.h b/target/arm/internals.h index e1aa1a63b9..02c57f546b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,7 +1002,7 @@ static inline bool regime_using_lpae_format(CPUARMSta= te *env, ARMMMUIdx mmu_idx) static inline int arm_num_brps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, BRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } @@ -1016,7 +1016,7 @@ static inline int arm_num_brps(ARMCPU *cpu) static inline int arm_num_wrps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, WRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } @@ -1030,7 +1030,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) static inline int arm_num_ctx_cmps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, CTX_CMPS) = + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cbfb6df435..42664dbfc1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2348,8 +2348,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; @@ -2401,19 +2400,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) * try to access the non-existent system registers for them. */ /* FEAT_SPE (Statistical Profiling Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMSVER, 0); /* FEAT_TRBE (Trace Buffer Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEFILT, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 594778a031..85f581edb7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -630,7 +630,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -689,7 +689,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index fa04383921..c15b24933d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8915,12 +8915,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64DFR0) }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr1 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64DFR1) }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index c9b99bf5ee..7377e4a133 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -328,10 +328,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR0_EL1); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR1_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 64473fc3c7..56f086cb28 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -91,8 +91,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); SET_IDREG(idregs, ID_AA64PFR1, 0); - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); + SET_IDREG(idregs, ID_AA64DFR1, 0); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64ISAR1, 0); SET_IDREG(idregs, ID_AA64MMFR0, 0x00101122); @@ -242,7 +242,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull); @@ -330,7 +330,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -369,7 +369,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408ull), SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull); @@ -440,8 +440,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr =3D 0x30000180; SET_IDREG(idregs, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensio= ns */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000000); - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408), + SET_IDREG(idregs, ID_AA64DFR1, 0x0000000000000000), cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000001122); @@ -611,7 +611,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + SET_IDREG(idregs, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull); @@ -686,8 +686,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->id_aa64afr0 =3D 0x00000000; cpu->id_aa64afr1 =3D 0x00000000; - cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; - cpu->isar.id_aa64dfr1 =3D 0x00000000; + SET_IDREG(idregs, ID_AA64DFR0, 0x000001f210305519ull), + SET_IDREG(idregs, ID_AA64DFR1, 0x00000000), SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_R= NG */ SET_IDREG(idregs, ID_AA64ISAR1, 0x0111000001211032ull); SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull); @@ -930,8 +930,9 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ - cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(idregs, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(idregs, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(idregs, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto= */ @@ -1029,8 +1030,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ - cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(idregs, ID_AA64DFR0, 0x000011f210305619ull); + SET_IDREG(idregs, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto= and FEAT_RNG */ @@ -1257,11 +1258,11 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ SET_IDREG(idregs, ID_AA64ZFR0, t); =20 - t =3D cpu->isar.id_aa64dfr0; + t =3D GET_IDREG(idregs, ID_AA64DFR0); t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_aa64dfr0 =3D t; + SET_IDREG(idregs, ID_AA64DFR0, t); =20 t =3D cpu->isar.id_aa64smfr0; t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851921; cv=none; d=zohomail.com; s=zohoarc; b=drshVB/ELPVTh8LotnsjpiA3bHMD/4Xe92NZmZABihXRf3gu/nZdmqolK/5AfEplPr0m2EgfQdNPYB2iGMEE8r4R38v2IQnO6/FCRI3kVypGupdBoiKyogMYifUUkSzkakCYKgp06FAUxRuy0H9H4ob3rz6RHbXeiC4bIBxy5Mc= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 6 +++--- target/arm/cpu.h | 1 - target/arm/cpu64.c | 7 ++----- target/arm/helper.c | 2 +- target/arm/kvm.c | 3 +-- target/arm/tcg/cpu64.c | 4 ++-- 6 files changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 9b0d5157bf..ada5d7eccc 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -952,17 +952,17 @@ static inline bool isar_feature_aa64_sve_f64mm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); + return FIELD_EX64_IDREG(&id->idregs, ID_AA64SMFR0, F64F64); } =20 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) =3D=3D 0xf; + return FIELD_EX64_IDREG(&id->idregs, ID_AA64SMFR0, I16I64) =3D=3D 0xf; } =20 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); + return FIELD_EX64_IDREG(&id->idregs, ID_AA64SMFR0, FA64); } =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6954952d5f..7f808e5772 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1088,7 +1088,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; IdRegMap idregs; } isar; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 85f581edb7..bf3eb5d0b5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -305,7 +305,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { - cpu->isar.id_aa64smfr0 =3D 0; + SET_IDREG(&cpu->isar.idregs, ID_AA64SMFR0, 0); return; } =20 @@ -358,11 +358,8 @@ static bool cpu_arm_get_sme_fa64(Object *obj, Error **= errp) static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64smfr0; - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, value); - cpu->isar.id_aa64smfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64SMFR0, FA64, value); } =20 #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index c15b24933d..7e73130d35 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8900,7 +8900,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64smfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_AA64SMFR0)}, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7377e4a133..e899f180f8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -326,8 +326,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err =3D 0; } else { err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64SMFR0_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR0_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR1_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 56f086cb28..611c252eae 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1264,7 +1264,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ SET_IDREG(idregs, ID_AA64DFR0, t); =20 - t =3D cpu->isar.id_aa64smfr0; + t =3D GET_IDREG(idregs, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ @@ -1272,7 +1272,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ - cpu->isar.id_aa64smfr0 =3D t; + SET_IDREG(idregs, ID_AA64SMFR0, t); =20 /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851865; cv=none; d=zohomail.com; s=zohoarc; b=nUnAWficWC/W8MbtHIciDRqnRo0uaM7fg0xDursHukIGu2uvOEGwJhAvkPr1tLD8KrddfbuGLW0PryUE6qpCHXzP+DM4jO3jt3gsLdQiuDbJUh+ViUHTNAhmbiojhAz1DOoliWuZBgCb6UUNr0et7QM10yf4dmdyHJ8/nT9r53Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729851865; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 36 +++++----- target/arm/cpu.h | 14 ++-- hw/intc/armv7m_nvic.c | 12 ++-- target/arm/cpu.c | 24 +++---- target/arm/cpu64.c | 28 ++++---- target/arm/helper.c | 14 ++-- target/arm/kvm.c | 34 +++++---- target/arm/tcg/cpu-v7m.c | 90 +++++++++++++----------- target/arm/tcg/cpu32.c | 143 ++++++++++++++++++++------------------ target/arm/tcg/cpu64.c | 108 ++++++++++++++-------------- 10 files changed, 262 insertions(+), 241 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index ada5d7eccc..306e6fa29f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -44,93 +44,93 @@ */ static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR0, DIVIDE) !=3D 0; } =20 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR0, DIVIDE) > 1; } =20 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) { /* (M-profile) low-overhead loops and branch future */ - return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >=3D 3; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR0, CMPBRANCH) >=3D 3; } =20 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR1, JAZELLE) !=3D 0; } =20 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, AES) !=3D 0; } =20 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, AES) > 1; } =20 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, RDM) !=3D 0; } =20 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, VCMA) !=3D 0; } =20 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, DP) !=3D 0; } =20 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, FHM) !=3D 0; } =20 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, SB) !=3D 0; } =20 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, BF16) !=3D 0; } =20 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7f808e5772..1c4fa6a561 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -871,6 +871,13 @@ regval =3D FIELD_DP64(regval, REG, FIELD, VALUE); = \ _set_idreg(MAP, SYS_ ## REG ## _EL1, regval); \ } =20 +#define FIELD_DP32_IDREG(MAP, REG, FIELD, VALUE) \ +{ \ +uint64_t regval =3D _get_idreg(MAP, SYS_ ## REG ## _EL1); \ +regval =3D FIELD_DP32(regval, REG, FIELD, VALUE); \ +_set_idreg(MAP, SYS_ ## REG ## _EL1, regval); \ +} + #define FIELD_EX64_IDREG(MAP, REG, FIELD) \ FIELD_EX64(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ =20 @@ -1064,13 +1071,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_isar0; - uint32_t id_isar1; - uint32_t id_isar2; - uint32_t id_isar3; - uint32_t id_isar4; - uint32_t id_isar5; - uint32_t id_isar6; uint32_t id_mmfr0; uint32_t id_mmfr1; uint32_t id_mmfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 404a445138..818f6fdfa9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar0; + return GET_IDREG(&cpu->isar.idregs, ID_ISAR0); case 0xd64: /* ISAR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar1; + return GET_IDREG(&cpu->isar.idregs, ID_ISAR1); case 0xd68: /* ISAR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar2; + return GET_IDREG(&cpu->isar.idregs, ID_ISAR2); case 0xd6c: /* ISAR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar3; + return GET_IDREG(&cpu->isar.idregs, ID_ISAR3); case 0xd70: /* ISAR4. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar4; + return GET_IDREG(&cpu->isar.idregs, ID_ISAR4); case 0xd74: /* ISAR5. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar5; + return GET_IDREG(&cpu->isar.idregs, ID_ISAR5); case 0xd78: /* CLIDR */ return cpu->clidr; case 0xd7c: /* CTR */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 42664dbfc1..bc80945da1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2127,10 +2127,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(idregs, ID_AA64PFR0, FP, 0xf); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(idregs, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(idregs, ID_ISAR6, u); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, FPSP, 0); @@ -2182,20 +2182,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(idregs, ID_AA64PFR0, ADVSIMD, 0xf); =20 - u =3D cpu->isar.id_isar5; + u =3D GET_IDREG(idregs, ID_ISAR5); u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 0); u =3D FIELD_DP32(u, ID_ISAR5, RDM, 0); u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 0); - cpu->isar.id_isar5 =3D u; + SET_IDREG(idregs, ID_ISAR5, u); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(idregs, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, DP, 0); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(idregs, ID_ISAR6, u); =20 if (!arm_feature(env, ARM_FEATURE_M)) { u =3D cpu->isar.mvfr1; @@ -2233,19 +2233,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 unset_feature(env, ARM_FEATURE_THUMB_DSP); =20 - u =3D cpu->isar.id_isar1; - u =3D FIELD_DP32(u, ID_ISAR1, EXTEND, 1); - cpu->isar.id_isar1 =3D u; + FIELD_DP32_IDREG(idregs, ID_ISAR1, EXTEND, 1); =20 - u =3D cpu->isar.id_isar2; + u =3D GET_IDREG(idregs, ID_ISAR2); u =3D FIELD_DP32(u, ID_ISAR2, MULTU, 1); u =3D FIELD_DP32(u, ID_ISAR2, MULTS, 1); - cpu->isar.id_isar2 =3D u; + SET_IDREG(idregs, ID_ISAR2, u); =20 - u =3D cpu->isar.id_isar3; + u =3D GET_IDREG(idregs, ID_ISAR3); u =3D FIELD_DP32(u, ID_ISAR3, SIMD, 1); u =3D FIELD_DP32(u, ID_ISAR3, SATURATE, 0); - cpu->isar.id_isar3 =3D u; + SET_IDREG(idregs, ID_ISAR3, u); } =20 =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bf3eb5d0b5..9c3784a35f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -619,13 +619,13 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00011142); + SET_IDREG(idregs, ID_ISAR5, 0x00011121); + SET_IDREG(idregs, ID_ISAR6, 0); SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); @@ -678,13 +678,13 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00011142); + SET_IDREG(idregs, ID_ISAR5, 0x00011121); + SET_IDREG(idregs, ID_ISAR6, 0); SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e73130d35..1782de26f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8778,32 +8778,32 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar0 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR0)}, { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar1 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR1)}, { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar2 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR2)}, { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar3 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR3) }, { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar4 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR4) }, { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar5 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR5) }, { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8813,7 +8813,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar6 }, + .resetvalue =3D GET_IDREG(idregs, ID_ISAR6) }, }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e899f180f8..9873f8e849 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -231,6 +231,18 @@ static bool kvm_arm_pauth_supported(void) kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); } =20 +/* read a 32b sysreg value and store it in the idregs */ +static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysReg = sr) +{ + int index =3D KVM_ARM_FEATURE_ID_RANGE_IDX(sr.op0, sr.op1, sr.crn, sr.= crm, sr.op2); + uint64_t *reg =3D &ahcf->isar.idregs.regs[index]; + int ret; + + ret =3D read_sys_reg32(fd, (uint32_t *)reg, + ARM64_SYS_REG(sr.op0, sr.op1, sr.crn, sr.crm, sr.= op2)); + return ret; +} + /* read a 64b sysreg value and store it in the idregs */ static int get_host_cpu_reg64(int fd, ARMHostCPUFeatures *ahcf, ARMSysReg = sr) { @@ -243,6 +255,7 @@ static int get_host_cpu_reg64(int fd, ARMHostCPUFeature= s *ahcf, ARMSysReg sr) return ret; } =20 + static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -356,22 +369,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) ARM64_SYS_REG(3, 0, 0, 1, 6)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR0_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR1_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR2_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR3_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR4_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR5_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR6_EL1); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index c059c681e9..fbde43d45e 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -46,6 +46,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_M); =20 @@ -67,18 +68,19 @@ static void cortex_m0_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(idregs, ID_ISAR0, 0x01141110); + SET_IDREG(idregs, ID_ISAR1, 0x02111000); + SET_IDREG(idregs, ID_ISAR2, 0x21112231); + SET_IDREG(idregs, ID_ISAR3, 0x01111110); + SET_IDREG(idregs, ID_ISAR4, 0x01310102); + SET_IDREG(idregs, ID_ISAR5, 0x00000000); + SET_IDREG(idregs, ID_ISAR6, 0x00000000); } =20 static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); @@ -92,18 +94,19 @@ static void cortex_m3_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(idregs, ID_ISAR0, 0x01141110); + SET_IDREG(idregs, ID_ISAR1, 0x02111000); + SET_IDREG(idregs, ID_ISAR2, 0x21112231); + SET_IDREG(idregs, ID_ISAR3, 0x01111110); + SET_IDREG(idregs, ID_ISAR4, 0x01310102); + SET_IDREG(idregs, ID_ISAR5, 0x00000000); + SET_IDREG(idregs, ID_ISAR6, 0x00000000); } =20 static void cortex_m4_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -122,18 +125,19 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(idregs, ID_ISAR0, 0x01141110); + SET_IDREG(idregs, ID_ISAR1, 0x02111000); + SET_IDREG(idregs, ID_ISAR2, 0x21112231); + SET_IDREG(idregs, ID_ISAR3, 0x01111110); + SET_IDREG(idregs, ID_ISAR4, 0x01310102); + SET_IDREG(idregs, ID_ISAR5, 0x00000000); + SET_IDREG(idregs, ID_ISAR6, 0x00000000); } =20 static void cortex_m7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -152,18 +156,19 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(idregs, ID_ISAR0, 0x01101110); + SET_IDREG(idregs, ID_ISAR1, 0x02112000); + SET_IDREG(idregs, ID_ISAR2, 0x20232231); + SET_IDREG(idregs, ID_ISAR3, 0x01111131); + SET_IDREG(idregs, ID_ISAR4, 0x01310132); + SET_IDREG(idregs, ID_ISAR5, 0x00000000); + SET_IDREG(idregs, ID_ISAR6, 0x00000000); } =20 static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_M); @@ -184,13 +189,13 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(idregs, ID_ISAR0, 0x01101110); + SET_IDREG(idregs, ID_ISAR1, 0x02212000); + SET_IDREG(idregs, ID_ISAR2, 0x20232232); + SET_IDREG(idregs, ID_ISAR3, 0x01111131); + SET_IDREG(idregs, ID_ISAR4, 0x01310132); + SET_IDREG(idregs, ID_ISAR5, 0x00000000); + SET_IDREG(idregs, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; cpu->ctr =3D 0x8000c000; } @@ -198,6 +203,7 @@ static void cortex_m33_initfn(Object *obj) static void cortex_m55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8_1M); @@ -221,13 +227,13 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000011; - cpu->isar.id_isar0 =3D 0x01103110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(idregs, ID_ISAR0, 0x01103110); + SET_IDREG(idregs, ID_ISAR1, 0x02212000); + SET_IDREG(idregs, ID_ISAR2, 0x20232232); + SET_IDREG(idregs, ID_ISAR3, 0x01111131); + SET_IDREG(idregs, ID_ISAR4, 0x01310132); + SET_IDREG(idregs, ID_ISAR5, 0x00000000); + SET_IDREG(idregs, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; /* caches not implemented */ cpu->ctr =3D 0x8303c003; } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 20c2737f17..ae5c909048 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -25,16 +25,16 @@ void aa32_max_features(ARMCPU *cpu) uint32_t t; =20 /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; + t =3D GET_IDREG(&cpu->isar.idregs, ID_ISAR5); t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - cpu->isar.id_isar5 =3D t; + SET_IDREG(&cpu->isar.idregs, ID_ISAR5, t); =20 - t =3D cpu->isar.id_isar6; + t =3D GET_IDREG(&cpu->isar.idregs, ID_ISAR6); t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ @@ -42,7 +42,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - cpu->isar.id_isar6 =3D t; + SET_IDREG(&cpu->isar.idregs, ID_ISAR6, t); =20 t =3D cpu->isar.mvfr1; t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ @@ -140,7 +140,7 @@ static void arm926_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar.idregs, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -182,7 +182,7 @@ static void arm1026_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar.idregs, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -206,6 +206,7 @@ static void arm1026_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; /* * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not @@ -233,17 +234,18 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(idregs, ID_ISAR0, 0x00140011); + SET_IDREG(idregs, ID_ISAR1, 0x12002111); + SET_IDREG(idregs, ID_ISAR2, 0x11231111); + SET_IDREG(idregs, ID_ISAR3, 0x01102131); + SET_IDREG(idregs, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1136_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -264,17 +266,18 @@ static void arm1136_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(idregs, ID_ISAR0, 0x00140011); + SET_IDREG(idregs, ID_ISAR1, 0x12002111); + SET_IDREG(idregs, ID_ISAR2, 0x11231111); + SET_IDREG(idregs, ID_ISAR3, 0x01102131); + SET_IDREG(idregs, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1176_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -296,17 +299,18 @@ static void arm1176_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222100; - cpu->isar.id_isar0 =3D 0x0140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231121; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x01141; + SET_IDREG(idregs, ID_ISAR0, 0x0140011); + SET_IDREG(idregs, ID_ISAR1, 0x12002111); + SET_IDREG(idregs, ID_ISAR2, 0x11231121); + SET_IDREG(idregs, ID_ISAR3, 0x01102131); + SET_IDREG(idregs, ID_ISAR4, 0x01141); cpu->reset_auxcr =3D 7; } =20 static void arm11mpcore_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -325,11 +329,11 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; cpu->isar.id_mmfr2 =3D 0x01222000; - cpu->isar.id_isar0 =3D 0x00100011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11221011; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(idregs, ID_ISAR0, 0x00100011); + SET_IDREG(idregs, ID_ISAR1, 0x12002111); + SET_IDREG(idregs, ID_ISAR2, 0x11221011); + SET_IDREG(idregs, ID_ISAR3, 0x01102131); + SET_IDREG(idregs, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 1; } =20 @@ -343,6 +347,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { static void cortex_a8_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -365,11 +370,11 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01202000; cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(idregs, ID_ISAR0, 0x00101111); + SET_IDREG(idregs, ID_ISAR1, 0x12112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232031); + SET_IDREG(idregs, ID_ISAR3, 0x11112131); + SET_IDREG(idregs, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x15141000; cpu->clidr =3D (1 << 27) | (2 << 24) | 3; cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ @@ -412,6 +417,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { static void cortex_a9_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -440,11 +446,11 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01230000; cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(idregs, ID_ISAR0, 0x00101111); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232041); + SET_IDREG(idregs, ID_ISAR3, 0x11112131); + SET_IDREG(idregs, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x35141000; cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ @@ -479,6 +485,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { static void cortex_a7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -509,11 +516,11 @@ static void cortex_a7_initfn(Object *obj) * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232041); + SET_IDREG(idregs, ID_ISAR3, 0x11112131); + SET_IDREG(idregs, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f005; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x1; @@ -528,6 +535,7 @@ static void cortex_a7_initfn(Object *obj) static void cortex_a15_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -556,11 +564,11 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01240000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232041); + SET_IDREG(idregs, ID_ISAR3, 0x11112131); + SET_IDREG(idregs, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f021; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x0; @@ -585,6 +593,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { static void cortex_r5_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_V7MP); @@ -599,13 +608,13 @@ static void cortex_r5_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0x0211; - cpu->isar.id_isar0 =3D 0x02101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232141; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x0010142; - cpu->isar.id_isar5 =3D 0x0; - cpu->isar.id_isar6 =3D 0x0; + SET_IDREG(idregs, ID_ISAR0, 0x02101111); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232141); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x0010142); + SET_IDREG(idregs, ID_ISAR5, 0x21232141); + SET_IDREG(idregs, ID_ISAR6, 0x0); cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; cpu->isar.reset_pmcr_el0 =3D 0x41151800; @@ -720,6 +729,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] =3D { static void cortex_r52_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -746,12 +756,12 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0xf0102211; cpu->isar.id_mmfr4 =3D 0x00000010; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232142; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x00010001; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232142); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00010142); + SET_IDREG(idregs, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr =3D 0x77168000; cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ @@ -949,6 +959,7 @@ static void pxa270c5_initfn(Object *obj) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -976,13 +987,13 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00011142); + SET_IDREG(idregs, ID_ISAR5, 0x00011121); + SET_IDREG(idregs, ID_ISAR6, 0); cpu->isar.reset_pmcr_el0 =3D 0x41013000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 611c252eae..cdaba9b184 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -83,12 +83,12 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00011142); + SET_IDREG(idregs, ID_ISAR5, 0x00011121); SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); SET_IDREG(idregs, ID_AA64PFR1, 0); SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); @@ -252,13 +252,13 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00011142); + SET_IDREG(idregs, ID_ISAR5, 0x01011121); + SET_IDREG(idregs, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -323,12 +323,12 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00011142); + SET_IDREG(idregs, ID_ISAR5, 0x00011121); SET_IDREG(idregs, ID_AA64PFR0, 0x00002222); SET_IDREG(idregs, ID_AA64DFR0, 0x10305106); SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120); @@ -379,13 +379,13 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00010142); + SET_IDREG(idregs, ID_ISAR5, 0x01011121); + SET_IDREG(idregs, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -621,13 +621,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00010142); + SET_IDREG(idregs, ID_ISAR5, 0x01011121); + SET_IDREG(idregs, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -697,13 +697,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; - cpu->isar.id_isar6 =3D 0x01100111; + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00010142); + SET_IDREG(idregs, ID_ISAR5, 0x11011121); + SET_IDREG(idregs, ID_ISAR6, 0x01100111); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -915,14 +915,14 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00010142); + SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x21021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(idregs, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; @@ -1015,14 +1015,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(idregs, ID_ISAR0, 0x02101110); + SET_IDREG(idregs, ID_ISAR1, 0x13112111); + SET_IDREG(idregs, ID_ISAR2, 0x21232042); + SET_IDREG(idregs, ID_ISAR3, 0x01112131); + SET_IDREG(idregs, ID_ISAR4, 0x00010142); + SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(idregs, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851789; cv=none; d=zohomail.com; s=zohoarc; b=gU4+NsQo7lNUw6g9Bl2fNTb/7jN5dlj6Ouc5pebC18shR0iudDlJ5ewGyI8o6kVA3aVZRr5LerOn0t9fRcrIWGKrkROvJzKQ5IDDsm5wuZq8+MybobqeIOMmtbIGyVVwSL9d5ijXb512t6dMn1KHy8j9cLbpXikZdQwh0kAWJJI= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 10 +++---- target/arm/cpu.h | 3 -- hw/intc/armv7m_nvic.c | 5 ++-- target/arm/cpu.c | 8 ++--- target/arm/cpu64.c | 8 ++--- target/arm/helper.c | 8 ++--- target/arm/kvm.c | 3 +- target/arm/tcg/cpu-v7m.c | 24 +++++++-------- target/arm/tcg/cpu32.c | 61 ++++++++++++++++++++------------------- target/arm/tcg/cpu64.c | 44 ++++++++++++++-------------- 10 files changed, 85 insertions(+), 89 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 306e6fa29f..217de5769e 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -135,12 +135,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_PFR1, MPROGMOD) !=3D 0; } =20 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) @@ -149,7 +149,7 @@ static inline bool isar_feature_aa32_m_sec_state(const = ARMISARegisters *id) * Return true if M-profile state handling insns * (VSCCLRM, CLRM, FPCTX access insns) are implemented */ - return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >=3D 3; + return FIELD_EX32_IDREG(&id->idregs, ID_PFR1, SECURITY) >=3D 3; } =20 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) @@ -348,12 +348,12 @@ static inline bool isar_feature_aa32_evt(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_PFR2, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1c4fa6a561..11c3b93a07 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1077,9 +1077,6 @@ struct ArchCPU { uint32_t id_mmfr3; uint32_t id_mmfr4; uint32_t id_mmfr5; - uint32_t id_pfr0; - uint32_t id_pfr1; - uint32_t id_pfr2; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 818f6fdfa9..8ab809eee9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int l= evel) static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; + IdRegMap *idregs =3D &cpu->isar.idregs; uint32_t val; =20 switch (offset) { @@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr0; + return GET_IDREG(idregs, ID_PFR0); case 0xd44: /* PFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr1; + return GET_IDREG(idregs, ID_PFR1); case 0xd48: /* DFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bc80945da1..eeb5db6085 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2318,7 +2318,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the security extension feature bits in the processor * feature registers as well. */ - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + FIELD_DP32_IDREG(idregs, ID_PFR1, SECURITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0); =20 @@ -2358,8 +2358,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * registers if we don't have EL2. */ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL2, 0); - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, - ID_PFR1, VIRTUALIZATION, 0); + FIELD_DP32_IDREG(idregs, ID_PFR1, VIRTUALIZATION, 0); } =20 if (cpu_isar_feature(aa64_mte, cpu)) { @@ -2414,8 +2413,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0); - cpu->isar.id_pfr0 =3D - FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + FIELD_DP32_IDREG(idregs, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, MPAM, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9c3784a35f..7e39235900 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -611,8 +611,8 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00000131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -670,8 +670,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00000131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/helper.c b/target/arm/helper.c index 1782de26f5..5e0094458f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7677,7 +7677,7 @@ static void define_pmu_regs(ARMCPU *cpu) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr1 =3D cpu->isar.id_pfr1; + uint64_t pfr1 =3D GET_IDREG(&cpu->isar.idregs, ID_PFR1); =20 if (env->gicv3state) { pfr1 |=3D 1 << 28; @@ -8725,7 +8725,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_pfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_PFR0)}, /* * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. @@ -8736,7 +8736,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa32_tid3, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_pfr1, + .resetvalue =3D GET_IDREG(idregs, ID_PFR0), #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa32_tid3, @@ -9082,7 +9082,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_pfr2 }, + .resetvalue =3D GET_IDREG(idregs, ID_PFR2)}, { .name =3D "ID_DFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9873f8e849..53e4216897 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -385,8 +385,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, ARM64_SYS_REG(3, 0, 0, 3, 5)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index fbde43d45e..06f9dce6ee 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -60,8 +60,8 @@ static void cortex_m0_initfn(Object *obj) * by looking at ID register fields. We use the same values as * for the M3. */ - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(idregs, ID_PFR0, 0x00000030); + SET_IDREG(idregs, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -86,8 +86,8 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); cpu->midr =3D 0x410fc231; cpu->pmsav7_dregion =3D 8; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(idregs, ID_PFR0, 0x00000030); + SET_IDREG(idregs, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -117,8 +117,8 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000000; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(idregs, ID_PFR0, 0x00000030); + SET_IDREG(idregs, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -148,8 +148,8 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(idregs, ID_PFR0, 0x00000030); + SET_IDREG(idregs, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; @@ -181,8 +181,8 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000210; + SET_IDREG(idregs, ID_PFR0, 0x00000030); + SET_IDREG(idregs, ID_PFR1, 0x00000210); cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; @@ -219,8 +219,8 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x20000030; - cpu->isar.id_pfr1 =3D 0x00000230; + SET_IDREG(idregs, ID_PFR0, 0x20000030); + SET_IDREG(idregs, ID_PFR1, 0x00000230); cpu->isar.id_dfr0 =3D 0x10200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index ae5c909048..ca771e54fc 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -23,18 +23,19 @@ void aa32_max_features(ARMCPU *cpu) { uint32_t t; + IdRegMap *idregs =3D &cpu->isar.idregs; =20 /* Add additional features supported by QEMU */ - t =3D GET_IDREG(&cpu->isar.idregs, ID_ISAR5); + t =3D GET_IDREG(idregs, ID_ISAR5); t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - SET_IDREG(&cpu->isar.idregs, ID_ISAR5, t); + SET_IDREG(idregs, ID_ISAR5, t); =20 - t =3D GET_IDREG(&cpu->isar.idregs, ID_ISAR6); + t =3D GET_IDREG(idregs, ID_ISAR6); t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ @@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - SET_IDREG(&cpu->isar.idregs, ID_ISAR6, t); + SET_IDREG(idregs, ID_ISAR6, t); =20 t =3D cpu->isar.mvfr1; t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ @@ -70,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ cpu->isar.id_mmfr5 =3D t; =20 - t =3D cpu->isar.id_pfr0; + t =3D GET_IDREG(idregs, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - cpu->isar.id_pfr0 =3D t; + SET_IDREG(idregs, ID_PFR0, t); =20 - t =3D cpu->isar.id_pfr2; + t =3D GET_IDREG(idregs, ID_PFR2); t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - cpu->isar.id_pfr2 =3D t; + SET_IDREG(idregs, ID_PFR2, t); =20 t =3D cpu->isar.id_dfr0; t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ @@ -227,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(idregs, ID_PFR0, 0x111); + SET_IDREG(idregs, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -259,8 +260,8 @@ static void arm1136_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(idregs, ID_PFR0, 0x111); + SET_IDREG(idregs, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -292,8 +293,8 @@ static void arm1176_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(idregs, ID_PFR0, 0x111); + SET_IDREG(idregs, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -322,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(idregs, ID_PFR0, 0x111); + SET_IDREG(idregs, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; @@ -362,8 +363,8 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00011111; cpu->ctr =3D 0x82048004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(idregs, ID_PFR0, 0x1031); + SET_IDREG(idregs, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; @@ -438,8 +439,8 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x01111111; cpu->ctr =3D 0x80038003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(idregs, ID_PFR0, 0x1031); + SET_IDREG(idregs, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; @@ -504,8 +505,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x84448003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00001131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -556,8 +557,8 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00001131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -600,8 +601,8 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->isar.id_pfr0 =3D 0x0131; - cpu->isar.id_pfr1 =3D 0x001; + SET_IDREG(idregs, ID_PFR0, 0x0131); + SET_IDREG(idregs, ID_PFR1, 0x001); cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; @@ -747,8 +748,8 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8144c004; cpu->reset_sctlr =3D 0x30c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x10111001; + SET_IDREG(idregs, ID_PFR0, 0x00000131); + SET_IDREG(idregs, ID_PFR1, 0x10111001); cpu->isar.id_dfr0 =3D 0x03010006; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; @@ -979,8 +980,8 @@ static void arm_max_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00000131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index cdaba9b184..9caa18f0dc 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -75,8 +75,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->midr =3D 0x411fd040; cpu->revidr =3D 0; cpu->ctr =3D 0x84448004; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00000131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -264,9 +264,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(idregs, ID_PFR0, 0x10010131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); + SET_IDREG(idregs, ID_PFR2, 0x00000011); cpu->midr =3D 0x412FD050; /* r2p0 */ cpu->revidr =3D 0; =20 @@ -315,8 +315,8 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(idregs, ID_PFR0, 0x00000131); + SET_IDREG(idregs, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -391,9 +391,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(idregs, ID_PFR0, 0x10010131); + SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(idregs, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0b1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -633,9 +633,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(idregs, ID_PFR0, 0x10010131); + SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(idregs, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0c1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -709,9 +709,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(idregs, ID_PFR0, 0x21110131); + SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(idregs, ID_PFR2, 0x00000011); cpu->midr =3D 0x411FD402; /* r1p2 */ cpu->revidr =3D 0; =20 @@ -907,8 +907,8 @@ static void aarch64_a710_initfn(Object *obj) /* Ordered by Section B.4: AArch64 registers */ cpu->midr =3D 0x412FD471; /* r2p1 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(idregs, ID_PFR0, 0x21110131); + SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -926,7 +926,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(idregs, ID_PFR2, 0x00000011); SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ @@ -1007,8 +1007,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) /* Ordered by Section B.5: AArch64 ID registers */ cpu->midr =3D 0x410FD493; /* r0p3 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(idregs, ID_PFR0, 0x21110131); + SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -1026,7 +1026,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(idregs, ID_PFR2, 0x00000011); SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto = */ --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851790; cv=none; d=zohomail.com; s=zohoarc; b=XZEncXg+4GQ/Rl3ku7wc2wzp0yku2lowNUl1aDzaPzEDwns9jCQFqIIARfGJSrAo6tjHNTIdUTYaKDI88T1XnxiGH5z/CZxrKi9n3dJ3WKa6t8dKSKvyCUloPHYwnuAFAUOz3RQBJXgnTzm6nUqIxL6aOjbZAKUOqOYAYhkTquY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.h | 2 -- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu.c | 13 +++++-------- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu-v7m.c | 12 ++++++------ target/arm/tcg/cpu32.c | 30 ++++++++++++++---------------- target/arm/tcg/cpu64.c | 16 ++++++++-------- 10 files changed, 48 insertions(+), 57 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 217de5769e..bd8a24169a 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -298,22 +298,22 @@ static inline bool isar_feature_aa32_ats1e1(const ARM= ISARegisters *id) static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >=3D 5 && + FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 6 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >=3D 6 && + FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) @@ -358,12 +358,12 @@ static inline bool isar_feature_aa32_ssbs(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 5; + return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, COPDBG) >=3D 5; } =20 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; + return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, COPDBG) >=3D 8; } =20 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11c3b93a07..8fae42d5b9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1080,8 +1080,6 @@ struct ArchCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; - uint32_t id_dfr0; - uint32_t id_dfr1; uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 8ab809eee9..7a11322b2c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1274,7 +1274,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_dfr0; + return GET_IDREG(idregs, ID_DFR0); case 0xd4c: /* AFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index eeb5db6085..454d546feb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2319,7 +2319,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ FIELD_DP32_IDREG(idregs, ID_PFR1, SECURITY, 0); - cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); + FIELD_DP32_IDREG(idregs, ID_DFR0, COPSDBG, 0); FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0); =20 /* Disable the realm management extension, which requires EL3. */ @@ -2347,7 +2347,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMUVER, 0); - cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); + FIELD_DP32_IDREG(idregs, ID_DFR0, PERFMON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } @@ -2402,15 +2402,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEFILT, 0); - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); + FIELD_DP32_IDREG(idregs, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEVER, 0); - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); + FIELD_DP32_IDREG(idregs, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); + FIELD_DP32_IDREG(idregs, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0); FIELD_DP32_IDREG(idregs, ID_PFR0, AMU, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7e39235900..6b8fdd8678 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -613,7 +613,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(idregs, ID_PFR0, 0x00000131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -672,7 +672,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(idregs, ID_PFR0, 0x00000131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e0094458f..81c2caee2c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8748,7 +8748,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_dfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_DFR0)}, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -9087,7 +9087,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_dfr1 }, + .resetvalue =3D GET_IDREG(idregs, ID_DFR1)}, { .name =3D "ID_MMFR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 53e4216897..144764cc54 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -359,8 +359,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) */ err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, - ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR0_EL1); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, ARM64_SYS_REG(3, 0, 0, 1, 4)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, @@ -386,8 +385,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, - ARM64_SYS_REG(3, 0, 0, 3, 5)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, ARM64_SYS_REG(3, 0, 0, 3, 6)); =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 06f9dce6ee..369e3e4c59 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -62,7 +62,7 @@ static void cortex_m0_initfn(Object *obj) */ SET_IDREG(idregs, ID_PFR0, 0x00000030); SET_IDREG(idregs, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -88,7 +88,7 @@ static void cortex_m3_initfn(Object *obj) cpu->pmsav7_dregion =3D 8; SET_IDREG(idregs, ID_PFR0, 0x00000030); SET_IDREG(idregs, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -119,7 +119,7 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000000; SET_IDREG(idregs, ID_PFR0, 0x00000030); SET_IDREG(idregs, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -150,7 +150,7 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(idregs, ID_PFR0, 0x00000030); SET_IDREG(idregs, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -183,7 +183,7 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(idregs, ID_PFR0, 0x00000030); SET_IDREG(idregs, ID_PFR1, 0x00000210); - cpu->isar.id_dfr0 =3D 0x00200000; + SET_IDREG(idregs, ID_DFR0, 0x00200000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -221,7 +221,7 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(idregs, ID_PFR0, 0x20000030); SET_IDREG(idregs, ID_PFR1, 0x00000230); - cpu->isar.id_dfr0 =3D 0x10200000; + SET_IDREG(idregs, ID_DFR0, 0x10200000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; cpu->isar.id_mmfr1 =3D 0x00000000; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index ca771e54fc..d1712216ff 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -82,11 +82,11 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ SET_IDREG(idregs, ID_PFR2, t); =20 - t =3D cpu->isar.id_dfr0; + t =3D GET_IDREG(idregs, ID_DFR0); t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - cpu->isar.id_dfr0 =3D t; + SET_IDREG(idregs, ID_DFR0, t); =20 /* Debug ID registers. */ =20 @@ -116,9 +116,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); cpu->isar.dbgdevid1 =3D t; =20 - t =3D cpu->isar.id_dfr1; - t =3D FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_dfr1 =3D t; + FIELD_DP32_IDREG(idregs, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ } =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ @@ -230,7 +228,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(idregs, ID_PFR0, 0x111); SET_IDREG(idregs, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0x2; + SET_IDREG(idregs, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -262,7 +260,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(idregs, ID_PFR0, 0x111); SET_IDREG(idregs, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0x2; + SET_IDREG(idregs, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -295,7 +293,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(idregs, ID_PFR0, 0x111); SET_IDREG(idregs, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x33; + SET_IDREG(idregs, ID_DFR0, 0x33); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -325,7 +323,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ SET_IDREG(idregs, ID_PFR0, 0x111); SET_IDREG(idregs, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0; + SET_IDREG(idregs, ID_DFR0, 0); cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; @@ -365,7 +363,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(idregs, ID_PFR0, 0x1031); SET_IDREG(idregs, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x400; + SET_IDREG(idregs, ID_DFR0, 0x400); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -441,7 +439,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(idregs, ID_PFR0, 0x1031); SET_IDREG(idregs, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x000; + SET_IDREG(idregs, ID_DFR0, 0x000); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -507,7 +505,7 @@ static void cortex_a7_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(idregs, ID_PFR0, 0x00001131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x02010555; + SET_IDREG(idregs, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -559,7 +557,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(idregs, ID_PFR0, 0x00001131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x02010555; + SET_IDREG(idregs, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -603,7 +601,7 @@ static void cortex_r5_initfn(Object *obj) cpu->midr =3D 0x411fc153; /* r1p3 */ SET_IDREG(idregs, ID_PFR0, 0x0131); SET_IDREG(idregs, ID_PFR1, 0x001); - cpu->isar.id_dfr0 =3D 0x010400; + SET_IDREG(idregs, ID_DFR0, 0x010400); cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -750,7 +748,7 @@ static void cortex_r52_initfn(Object *obj) cpu->reset_sctlr =3D 0x30c50838; SET_IDREG(idregs, ID_PFR0, 0x00000131); SET_IDREG(idregs, ID_PFR1, 0x10111001); - cpu->isar.id_dfr0 =3D 0x03010006; + SET_IDREG(idregs, ID_DFR0, 0x03010006); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -982,7 +980,7 @@ static void arm_max_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(idregs, ID_PFR0, 0x00000131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9caa18f0dc..aee36fabc1 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -77,7 +77,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->ctr =3D 0x84448004; SET_IDREG(idregs, ID_PFR0, 0x00000131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -251,7 +251,7 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(idregs, ID_DFR0, 0x04010088); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -317,7 +317,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(idregs, ID_PFR0, 0x00000131); SET_IDREG(idregs, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -378,7 +378,7 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(idregs, ID_DFR0, 0x04010088); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -620,7 +620,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(idregs, ID_DFR0, 0x04010088); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -696,7 +696,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled i= n later */ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x15011099; + SET_IDREG(idregs, ID_DFR0, 0x15011099); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -909,7 +909,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->revidr =3D 0; SET_IDREG(idregs, ID_PFR0, 0x21110131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ - cpu->isar.id_dfr0 =3D 0x16011099; + SET_IDREG(idregs, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -1009,7 +1009,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->revidr =3D 0; SET_IDREG(idregs, ID_PFR0, 0x21110131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ - cpu->isar.id_dfr0 =3D 0x16011099; + SET_IDREG(idregs, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=W2duqihuhZCnNBHkWzxpB9sv4Ywpu9y8vJy698H/nABLt/9p9pd5a82/BoKA3keNT77rkF ph2sGsy4LUrotSbXnT5flKeQg7wiIgQpPMLOLqTAUV7YrK3E7giSAgQBmDqCjONdYSqyr/ qNTPJuuJP/EVZ3UKO4SDWNICPU1gFxg= X-MC-Unique: -xe2m4d8Pj-Yne8xl6ULeA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 12/21] arm/cpu: Store id_mmfr0-5 into the idregs array Date: Fri, 25 Oct 2024 12:17:31 +0200 Message-ID: <20241025101959.601048-13-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-features.h | 18 ++++---- target/arm/cpu.h | 6 --- hw/intc/armv7m_nvic.c | 8 ++-- target/arm/cpu64.c | 16 +++---- target/arm/helper.c | 12 ++--- target/arm/kvm.c | 18 +++----- target/arm/tcg/cpu-v7m.c | 48 ++++++++++---------- target/arm/tcg/cpu32.c | 94 +++++++++++++++++++-------------------- target/arm/tcg/cpu64.c | 76 +++++++++++++++---------------- 9 files changed, 140 insertions(+), 156 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index bd8a24169a..93e5288539 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -282,17 +282,17 @@ static inline bool isar_feature_aa32_vminmaxnm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >=3D 4; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR0, VMSA) >=3D 4; } =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR3, PAN) !=3D 0; } =20 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR3, PAN) >=3D 2; } =20 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) @@ -318,32 +318,32 @@ static inline bool isar_feature_aa32_pmuv3p5(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, HPDS) !=3D 0; } =20 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, AC2) !=3D 0; } =20 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) !=3D 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, XNX) !=3D 0; } =20 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >=3D 1; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, EVT) >=3D 1; } =20 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >=3D 2; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, EVT) >=3D 2; } =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8fae42d5b9..30b265e9b0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1071,12 +1071,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_mmfr0; - uint32_t id_mmfr1; - uint32_t id_mmfr2; - uint32_t id_mmfr3; - uint32_t id_mmfr4; - uint32_t id_mmfr5; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 7a11322b2c..3ad4418302 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1284,22 +1284,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr0; + return GET_IDREG(idregs, ID_MMFR0); case 0xd54: /* MMFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr1; + return GET_IDREG(idregs, ID_MMFR1); case 0xd58: /* MMFR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr2; + return GET_IDREG(idregs, ID_MMFR2); case 0xd5c: /* MMFR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr3; + return GET_IDREG(idregs, ID_MMFR3); case 0xd60: /* ISAR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6b8fdd8678..57e73fdd38 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -615,10 +615,10 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10101105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -674,10 +674,10 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10101105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); diff --git a/target/arm/helper.c b/target/arm/helper.c index 81c2caee2c..978b9ed44a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8758,22 +8758,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr0 }, + .resetvalue =3D GET_IDREG(idregs, ID_MMFR0)}, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr1 }, + .resetvalue =3D GET_IDREG(idregs, ID_MMFR1)}, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr2 }, + .resetvalue =3D GET_IDREG(idregs, ID_MMFR2)}, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr3 }, + .resetvalue =3D GET_IDREG(idregs, ID_MMFR3)}, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8808,7 +8808,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr4 }, + .resetvalue =3D GET_IDREG(idregs, ID_MMFR4)}, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -9092,7 +9092,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_mmfr5 }, + .resetvalue =3D GET_IDREG(idregs, ID_MMFR5)}, { .name =3D "RES_0_C0_C3_7", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 144764cc54..bd53554832 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -360,14 +360,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1); err |=3D get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR0_EL1); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR0_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR1_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR2_EL1); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR3_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR0_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR1_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR2_EL1); @@ -375,8 +371,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR4_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR5_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR6_EL1); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR4_EL1); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); @@ -386,8 +381,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); + err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR5_EL1); =20 /* * DBGDIDR is a bit complicated because the kernel doesn't diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 369e3e4c59..cbf1c03d68 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -64,10 +64,10 @@ static void cortex_m0_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00000030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x00000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01141110); SET_IDREG(idregs, ID_ISAR1, 0x02111000); SET_IDREG(idregs, ID_ISAR2, 0x21112231); @@ -90,10 +90,10 @@ static void cortex_m3_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00000030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x00000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01141110); SET_IDREG(idregs, ID_ISAR1, 0x02111000); SET_IDREG(idregs, ID_ISAR2, 0x21112231); @@ -121,10 +121,10 @@ static void cortex_m4_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00000030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x00000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01141110); SET_IDREG(idregs, ID_ISAR1, 0x02111000); SET_IDREG(idregs, ID_ISAR2, 0x21112231); @@ -152,10 +152,10 @@ static void cortex_m7_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00100030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00100030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01101110); SET_IDREG(idregs, ID_ISAR1, 0x02112000); SET_IDREG(idregs, ID_ISAR2, 0x20232231); @@ -185,10 +185,10 @@ static void cortex_m33_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000210); SET_IDREG(idregs, ID_DFR0, 0x00200000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00101F40; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00101F40); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01101110); SET_IDREG(idregs, ID_ISAR1, 0x02212000); SET_IDREG(idregs, ID_ISAR2, 0x20232232); @@ -223,10 +223,10 @@ static void cortex_m55_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000230); SET_IDREG(idregs, ID_DFR0, 0x10200000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00111040; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000011; + SET_IDREG(idregs, ID_MMFR0, 0x00111040); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000011); SET_IDREG(idregs, ID_ISAR0, 0x01103110); SET_IDREG(idregs, ID_ISAR1, 0x02212000); SET_IDREG(idregs, ID_ISAR2, 0x20232232); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d1712216ff..6620260480 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -55,21 +55,17 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - cpu->isar.id_mmfr3 =3D t; + FIELD_DP32_IDREG(idregs, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ =20 - t =3D cpu->isar.id_mmfr4; + t =3D GET_IDREG(idregs, ID_MMFR4); t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ - cpu->isar.id_mmfr4 =3D t; + SET_IDREG(idregs, ID_MMFR4, t); =20 - t =3D cpu->isar.id_mmfr5; - t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - cpu->isar.id_mmfr5 =3D t; + FIELD_DP32_IDREG(idregs, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ =20 t =3D GET_IDREG(idregs, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ @@ -230,9 +226,9 @@ static void arm1136_r2_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x1); SET_IDREG(idregs, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; + SET_IDREG(idregs, ID_MMFR0, 0x01130003); + SET_IDREG(idregs, ID_MMFR1, 0x10030302); + SET_IDREG(idregs, ID_MMFR2, 0x01222110); SET_IDREG(idregs, ID_ISAR0, 0x00140011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11231111); @@ -262,9 +258,9 @@ static void arm1136_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x1); SET_IDREG(idregs, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; + SET_IDREG(idregs, ID_MMFR0, 0x01130003); + SET_IDREG(idregs, ID_MMFR1, 0x10030302); + SET_IDREG(idregs, ID_MMFR2, 0x01222110); SET_IDREG(idregs, ID_ISAR0, 0x00140011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11231111); @@ -295,9 +291,9 @@ static void arm1176_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x11); SET_IDREG(idregs, ID_DFR0, 0x33); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222100; + SET_IDREG(idregs, ID_MMFR0, 0x01130003); + SET_IDREG(idregs, ID_MMFR1, 0x10030302); + SET_IDREG(idregs, ID_MMFR2, 0x01222100); SET_IDREG(idregs, ID_ISAR0, 0x0140011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11231121); @@ -325,9 +321,9 @@ static void arm11mpcore_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x1); SET_IDREG(idregs, ID_DFR0, 0); cpu->id_afr0 =3D 0x2; - cpu->isar.id_mmfr0 =3D 0x01100103; - cpu->isar.id_mmfr1 =3D 0x10020302; - cpu->isar.id_mmfr2 =3D 0x01222000; + SET_IDREG(idregs, ID_MMFR0, 0x01100103); + SET_IDREG(idregs, ID_MMFR1, 0x10020302); + SET_IDREG(idregs, ID_MMFR2, 0x01222000); SET_IDREG(idregs, ID_ISAR0, 0x00100011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11221011); @@ -365,10 +361,10 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x11); SET_IDREG(idregs, ID_DFR0, 0x400); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x31100003; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01202000; - cpu->isar.id_mmfr3 =3D 0x11; + SET_IDREG(idregs, ID_MMFR0, 0x31100003); + SET_IDREG(idregs, ID_MMFR1, 0x20000000); + SET_IDREG(idregs, ID_MMFR2, 0x01202000); + SET_IDREG(idregs, ID_MMFR3, 0x11); SET_IDREG(idregs, ID_ISAR0, 0x00101111); SET_IDREG(idregs, ID_ISAR1, 0x12112111); SET_IDREG(idregs, ID_ISAR2, 0x21232031); @@ -441,10 +437,10 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x11); SET_IDREG(idregs, ID_DFR0, 0x000); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x00100103; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01230000; - cpu->isar.id_mmfr3 =3D 0x00002111; + SET_IDREG(idregs, ID_MMFR0, 0x00100103); + SET_IDREG(idregs, ID_MMFR1, 0x20000000); + SET_IDREG(idregs, ID_MMFR2, 0x01230000); + SET_IDREG(idregs, ID_MMFR3, 0x00002111); SET_IDREG(idregs, ID_ISAR0, 0x00101111); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232041); @@ -507,10 +503,10 @@ static void cortex_a7_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10101105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01240000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); /* * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. @@ -559,10 +555,10 @@ static void cortex_a15_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x20000000); + SET_IDREG(idregs, ID_MMFR2, 0x01240000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232041); @@ -603,10 +599,10 @@ static void cortex_r5_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x001); SET_IDREG(idregs, ID_DFR0, 0x010400); cpu->id_afr0 =3D 0x0; - cpu->isar.id_mmfr0 =3D 0x0210030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0x0211; + SET_IDREG(idregs, ID_MMFR0, 0x0210030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01200000); + SET_IDREG(idregs, ID_MMFR3, 0x0211); SET_IDREG(idregs, ID_ISAR0, 0x02101111); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232141); @@ -750,11 +746,11 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x10111001); SET_IDREG(idregs, ID_DFR0, 0x03010006); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00211040; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0xf0102211; - cpu->isar.id_mmfr4 =3D 0x00000010; + SET_IDREG(idregs, ID_MMFR0, 0x00211040); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01200000); + SET_IDREG(idregs, ID_MMFR3, 0xf0102211); + SET_IDREG(idregs, ID_MMFR4, 0x00000010); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232142); @@ -982,10 +978,10 @@ static void arm_max_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + ET_IDREG(idregs, ID_MMFR0, 0x10101105); + ET_IDREG(idregs, ID_MMFR1, 0x40000000); + ET_IDREG(idregs, ID_MMFR2, 0x01260000); + ET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index aee36fabc1..ac54fd2083 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -79,10 +79,10 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -259,11 +259,11 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00011142); SET_IDREG(idregs, ID_ISAR5, 0x01011121); SET_IDREG(idregs, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x00021110); SET_IDREG(idregs, ID_PFR0, 0x10010131); SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -319,10 +319,10 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -386,11 +386,11 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x01011121); SET_IDREG(idregs, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x00021110); SET_IDREG(idregs, ID_PFR0, 0x10010131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -628,11 +628,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x01011121); SET_IDREG(idregs, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x00021110); SET_IDREG(idregs, ID_PFR0, 0x10010131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -704,11 +704,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x11011121); SET_IDREG(idregs, ID_ISAR6, 0x01100111); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x01021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x01021110); SET_IDREG(idregs, ID_PFR0, 0x21110131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -911,17 +911,17 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); SET_IDREG(idregs, ID_ISAR3, 0x01112131); SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 =3D 0x21021110; + SET_IDREG(idregs, ID_MMFR4, 0x21021110); SET_IDREG(idregs, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; @@ -1011,17 +1011,17 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); SET_IDREG(idregs, ID_ISAR3, 0x01112131); SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 =3D 0x01021110; + SET_IDREG(idregs, ID_MMFR4, 0x01021110); SET_IDREG(idregs, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" The known ID regs are described in a new initialization function dubbed initialize_cpu_sysreg_properties(). That code will be automatically generated from linux arch/arm64/tools/sysreg. For the time being let's just describe a single id reg, CTR_EL0. In this description we only care about non RES/RAZ fields, ie. named fields. The registers are populated in a 3x8x8 array and their fields are added in a sorted list. Signed-off-by: Eric Auger --- target/arm/cpu-custom.h | 58 ++++++++++++++++++++++++++++++ target/arm/cpu-sysreg-properties.c | 41 +++++++++++++++++++++ target/arm/cpu64.c | 2 ++ target/arm/meson.build | 1 + 4 files changed, 102 insertions(+) create mode 100644 target/arm/cpu-custom.h create mode 100644 target/arm/cpu-sysreg-properties.c diff --git a/target/arm/cpu-custom.h b/target/arm/cpu-custom.h new file mode 100644 index 0000000000..1952095bf7 --- /dev/null +++ b/target/arm/cpu-custom.h @@ -0,0 +1,58 @@ +#ifndef ARM_CPU_CUSTOM_H +#define ARM_CPU_CUSTOM_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + int index; + int lower; + int upper; +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMSysReg *sysreg; + int index; + GList *fields; /* list of named fields, excluding RES* */ +} ARM64SysReg; + +void initialize_cpu_sysreg_properties(void); + +/* + * List of exposed ID regs (automatically populated from linux + * arch/arm64/tools/sysreg) + */ +extern ARM64SysReg arm64_id_regs[NR_ID_REGS]; + +/* Allocate a new field and insert it at the head of the @reg list */ +static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *= name, + uint8_t min, uint8_t max) { + + ARM64SysRegField *field =3D g_new0(ARM64SysRegField, 1); + + field->name =3D name; + field->lower =3D min; + field->upper =3D max; + field->index =3D reg->index; + + reg->fields =3D g_list_append(reg->fields, field); + return reg->fields; +} + +static inline ARM64SysReg * +arm64_sysreg_get(int op0, int op1, int crn, int crm, int op2) +{ + uint64_t index =3D ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op= 2); + ARM64SysReg *reg =3D &arm64_id_regs[index]; + + reg->index =3D index; + reg->sysreg =3D g_new(ARMSysReg, 1); + *reg->sysreg =3D sys_reg(op0, op1, crn, crm, op2); + return reg; +} + +#endif diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-pro= perties.c new file mode 100644 index 0000000000..753e7c9127 --- /dev/null +++ b/target/arm/cpu-sysreg-properties.c @@ -0,0 +1,41 @@ +/* + * QEMU ARM CPU SYSREG PROPERTIES + * to be generated from linux sysreg + * + * Copyright (c) 2024, Inc. 2024 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "cpu-custom.h" + +ARM64SysReg arm64_id_regs[NR_ID_REGS]; + +void initialize_cpu_sysreg_properties(void) +{ + memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NR_ID_REGS); + /* CTR_EL0 */ + ARM64SysReg *CTR_EL0 =3D arm64_sysreg_get(3, 3, 0, 0, 1); + CTR_EL0->name =3D "CTR_EL0"; + arm64_sysreg_add_field(CTR_EL0, "TMinline", 32, 37); + arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29); + arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28); + arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27); + arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23); + arm64_sysreg_add_field(CTR_EL0, "DMinLine", 16, 19); + arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); + arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); +} + diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 57e73fdd38..9f20886668 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,6 +34,7 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" +#include "cpu-custom.h" =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { @@ -844,6 +845,7 @@ static void aarch64_cpu_register_types(void) { size_t i; =20 + initialize_cpu_sysreg_properties(); type_register_static(&aarch64_cpu_type_info); =20 for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { diff --git a/target/arm/meson.build b/target/arm/meson.build index 2e10464dbb..9c7a04ee1b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -14,6 +14,7 @@ arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstu= b.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c', + 'cpu-sysreg-properties.c', )) =20 arm_system_ss =3D ss.source_set() --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851789; cv=none; d=zohomail.com; s=zohoarc; b=mqjfm1NjEUPPxfpXxDfdFq/PfezV/Aa6LfbO4WjE4whh73OHww5x0QvFONfhJ66xlahHDX3gy/NEZXKSm1dy+3+sR0XmseAnMTScQ+//PybNqHGNCz15xnpPxuK1PWqmy0GobF16HZB81EGPUcBSiXvAc8oPV5xsiDKtwAKBNbo= ARC-Message-Signature: i=1; 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charset="utf-8" Introduce scripts that automate the generation of system register definitions from a given linux source tree arch/arm64/tools/sysreg. Invocation of ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE in scripts directory do generate 2 qemu files: - target/arm/cpu-sysreg-properties.c - target/arm/cpu-sysregs.h cpu-sysregs.h creates defined for all system registers. However cpu-sysreg-properties.c only cares about feature ID registers. update-aarch64-sysreg-code.sh calls two awk scripts. gen-cpu-sysreg-properties.awk is inherited from kernel arch/arm64/tools/gen-sysreg.awk. All credits to Mark Rutland the original author of this script. Signed-off-by: Eric Auger --- scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++++++++++++++++ scripts/gen-cpu-sysregs-header.awk | 47 ++++ scripts/update-aarch64-sysreg-code.sh | 27 +++ 3 files changed, 399 insertions(+) create mode 100755 scripts/gen-cpu-sysreg-properties.awk create mode 100755 scripts/gen-cpu-sysregs-header.awk create mode 100755 scripts/update-aarch64-sysreg-code.sh diff --git a/scripts/gen-cpu-sysreg-properties.awk b/scripts/gen-cpu-sysreg= -properties.awk new file mode 100755 index 0000000000..b0ed55e059 --- /dev/null +++ b/scripts/gen-cpu-sysreg-properties.awk @@ -0,0 +1,325 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# gen-sysreg.awk: arm64 sysreg header generator +# +# Usage: awk -f gen-custom-sysreg.awk $LINUX_PATH/arch/arm64/tools/sysreg + +function block_current() { + return __current_block[__current_block_depth]; +} + +# Log an error and terminate +function fatal(msg) { + print "Error at " NR ": " msg > "/dev/stderr" + + printf "Current block nesting:" + + for (i =3D 0; i <=3D __current_block_depth; i++) { + printf " " __current_block[i] + } + printf "\n" + + exit 1 +} + +# Enter a new block, setting the active block to @block +function block_push(block) { + __current_block[++__current_block_depth] =3D block +} + +# Exit a block, setting the active block to the parent block +function block_pop() { + if (__current_block_depth =3D=3D 0) + fatal("error: block_pop() in root block") + + __current_block_depth--; +} + +# Sanity check the number of records for a field makes sense. If not, prod= uce +# an error and terminate. +function expect_fields(nf) { + if (NF !=3D nf) + fatal(NF " fields found where " nf " expected") +} + +# Print a CPP macro definition, padded with spaces so that the macro bodies +# line up in a column +function define(name, val) { + printf "%-56s%s\n", "#define " name, val +} + +# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field +function define_field(reg, field, msb, lsb, idreg) { + if (idreg) + print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "= msb");" +} + +# Print a field _SIGNED definition for a field +function define_field_sign(reg, field, sign, idreg) { + if (idreg) + print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "= msb");" +} + +# Parse a "[:]" string into the global variables @msb and @lsb +function parse_bitdef(reg, field, bitdef, _bits) +{ + if (bitdef ~ /^[0-9]+$/) { + msb =3D bitdef + lsb =3D bitdef + } else if (split(bitdef, _bits, ":") =3D=3D 2) { + msb =3D _bits[1] + lsb =3D _bits[2] + } else { + fatal("invalid bit-range definition '" bitdef "'") + } + + + if (msb !=3D next_bit) + fatal(reg "." field " starts at " msb " not " next_bit) + if (63 < msb || msb < 0) + fatal(reg "." field " invalid high bit in '" bitdef "'") + if (63 < lsb || lsb < 0) + fatal(reg "." field " invalid low bit in '" bitdef "'") + if (msb < lsb) + fatal(reg "." field " invalid bit-range '" bitdef "'") + if (low > high) + fatal(reg "." field " has invalid range " high "-" low) + + next_bit =3D lsb - 1 +} + +BEGIN { + print "#include \"cpu-custom.h\"" + print "" + print "ARM64SysReg arm64_id_regs[NR_ID_REGS];" + print "" + print "void initialize_cpu_sysreg_properties(void)" + print "{" + print " memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NR_ID_RE= GS);" + print "" + + __current_block_depth =3D 0 + __current_block[__current_block_depth] =3D "Root" +} + +END { + if (__current_block_depth !=3D 0) + fatal("Missing terminator for " block_current() " block") + + print "}" +} + +# skip blank lines and comment lines +/^$/ { next } +/^[\t ]*#/ { next } + +/^SysregFields/ && block_current() =3D=3D "Root" { + block_push("SysregFields") + + expect_fields(2) + + reg =3D $2 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + next_bit =3D 63 + + next +} + +/^EndSysregFields/ && block_current() =3D=3D "SysregFields" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + reg =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + block_pop() + next +} + +/^Sysreg/ && block_current() =3D=3D "Root" { + block_push("Sysreg") + + expect_fields(7) + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + if (op0 =3D=3D 3 && (op1>=3D0 && op1<=3D3) && crn=3D=3D0 && (crm>=3D0 && = crm<=3D7) && (op2>=3D0 && op2<=3D7)) { + idreg =3D 1 + } else { + idreg =3D 0 + } + + if (idreg =3D=3D 1) { + print " /* "reg" */" + print " ARM64SysReg *"reg" =3D arm64_sysreg_get("op0", "op1", "crn"= , "crm", "op2");" + print " "reg"->name =3D \""reg"\";" + } + + next_bit =3D 63 + + next +} + +/^EndSysreg/ && block_current() =3D=3D "Sysreg" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + reg =3D null + op0 =3D null + op1 =3D null + crn =3D null + crm =3D null + op2 =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + if (idreg=3D=3D1) + print "" + block_pop() + next +} + +# Currently this is effectivey a comment, in future we may want to emit +# defines for the fields. +/^Fields/ && block_current() =3D=3D "Sysreg" { + expect_fields(2) + + if (next_bit !=3D 63) + fatal("Some fields already defined for " reg) + + print "/* For " reg " fields see " $2 " */" + print "" + + next_bit =3D 0 + res0 =3D null + res1 =3D null + unkn =3D null + + next +} + + +/^Res0/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "RES0", $2) + field =3D "RES0_" msb "_" lsb + + res0 =3D res0 " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Res1/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "RES1", $2) + field =3D "RES1_" msb "_" lsb + + res1 =3D res1 " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Unkn/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "UNKN", $2) + field =3D "UNKN_" msb "_" lsb + + unkn =3D unkn " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Field/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sy= sregFields") { + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + + define_field(reg, field, msb, lsb, idreg) + + next +} + +/^Raz/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sysr= egFields") { + expect_fields(2) + parse_bitdef(reg, field, $2) + + next +} + +/^SignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + define_field_sign(reg, field, "true", idreg) + + next +} + +/^UnsignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + #define_field_sign(reg, field, "false", idreg) + + next +} + +/^Enum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + + next +} + +/^EndEnum/ && block_current() =3D=3D "Enum" { + + field =3D null + msb =3D null + lsb =3D null + + block_pop() + next +} + +/0b[01]+/ && block_current() =3D=3D "Enum" { + expect_fields(2) + val =3D $1 + name =3D $2 + + next +} + +# Any lines not handled by previous rules are unexpected +{ + fatal("unhandled statement") +} diff --git a/scripts/gen-cpu-sysregs-header.awk b/scripts/gen-cpu-sysregs-h= eader.awk new file mode 100755 index 0000000000..cdad686a53 --- /dev/null +++ b/scripts/gen-cpu-sysregs-header.awk @@ -0,0 +1,47 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# gen-sysreg.awk: arm64 sysreg header generator +# +# Usage: awk -f gen-custom-sysreg.awk $LINUX_PATH/arch/arm64/tools/sysreg + +# Sanity check the number of records for a field makes sense. If not, prod= uce +# an error and terminate. + +# Print a CPP macro definition, padded with spaces so that the macro bodies +# line up in a column +function define(name, val) { + printf "%-56s%s\n", "#define " name, val +} + +BEGIN { + print "#ifndef ARM_CPU_SYSREGS_H" + print "#define ARM_CPU_SYSREGS_H" + print "" + print "/* Generated file - do not edit */" + print "" +} END { + print "" + print "#endif /* ARM_CPU_SYSREGS_H */" +} + +# skip blank lines and comment lines +/^$/ { next } +/^[\t ]*#/ { next } + +/^Sysreg\t/ || /^Sysreg /{ + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") + next +} + +{ + /* skip all other lines */ + next +} diff --git a/scripts/update-aarch64-sysreg-code.sh b/scripts/update-aarch64= -sysreg-code.sh new file mode 100755 index 0000000000..e1fe40308b --- /dev/null +++ b/scripts/update-aarch64-sysreg-code.sh @@ -0,0 +1,27 @@ +#!/bin/sh -e +# +# Update target/arm/cpu-sysreg-properties.c and target/arm/cpu-sysregs.h +# from a linux source tree (arch/arm64/tools/sysreg) +# +# Copyright Red Hat, Inc. 2024 +# +# Authors: +# Eric Auger +# + +linux=3D"$1" +output=3D"$PWD" + +if [ -z "$linux" ] || ! [ -d "$linux" ]; then + cat << EOF +usage: update-aarch64-sysreg-code.sh LINUX_PATH + +LINUX_PATH Linux kernel directory to obtain the headers from +EOF + exit 1 +fi + +awk -f gen-cpu-sysregs-header.awk \ + $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysregs.h +awk -f gen-cpu-sysreg-properties.awk \ + $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysreg-propertie= s.c --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851834; cv=none; d=zohomail.com; s=zohoarc; b=WscMr+QMYUNCCQJ0mOJ7FMIxC46xoouC7rpU2tT4bqwGeODQ8/azuc/SSc6GepWpU6i2u9aajrZX+obdimAwR9MGwjLnv5CyxuolJfPzyHwy4h6/rC7qzJq0HnY1gZFgoE4yhwIVDZMldQuS1wN8AxWQ24JKArhDpcoaJdymzVo= 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b=OtYPeg50UQPiNY7i7s8Gooc0LBHJKGSDJN3i06TPI8DsPzBpgGadgCgaSjm57AOojSQn2h YTJjDm5z1zIdoJ2e0O3DK0frhzwVyFds3laZm1y+FIDvjIhnHkOyDcsgNZOeLOL5C8vuwG 4qv9TC+m88oisW50S5RQqHEbMeiPIDw= X-MC-Unique: SPgSnkA8Nn66a3U0MYOi7w-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 15/21] arm/cpu: Add generated files Date: Fri, 25 Oct 2024 12:17:34 +0200 Message-ID: <20241025101959.601048-16-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 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List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1729851835606116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Auger --- target/arm/cpu-sysregs.h | 142 +++++- target/arm/cpu-sysreg-properties.c | 689 ++++++++++++++++++++++++++++- 2 files changed, 791 insertions(+), 40 deletions(-) diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index f4b63a3af7..8c4cd0f2b4 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -1,24 +1,18 @@ #ifndef ARM_CPU_SYSREGS_H #define ARM_CPU_SYSREGS_H =20 -/* to be generated */ - -#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4= , 0) -#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4= , 1) -#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4= , 5) -#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5= , 0) -#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5= , 1) -#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6= , 0) -#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6= , 1) -#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6= , 2) -#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7= , 0) -#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7= , 1) -#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7= , 2) -#define SYS_ID_AA64MMFR3_EL1 sys_reg(3, 0, 0, 7= , 3) +/* Generated file - do not edit */ =20 +#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0= , 2) +#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2= , 0) +#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2= , 2) +#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3= , 2) +#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6= , 2) +#define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0= , 4) #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1= , 0) #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1= , 1) #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1= , 2) +#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1= , 3) #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1= , 4) #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1= , 5) #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1= , 6) @@ -29,14 +23,130 @@ #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2= , 3) #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2= , 4) #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2= , 5) -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2= , 6) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2= , 7) +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2= , 6) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3= , 0) #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3= , 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3= , 2) #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3= , 4) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3= , 5) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3= , 6) +#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4= , 0) +#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4= , 1) +#define SYS_ID_AA64PFR2_EL1 sys_reg(3, 0, 0, 4= , 2) #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4= , 4) +#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4= , 5) +#define SYS_ID_AA64FPFR0_EL1 sys_reg(3, 0, 0, 4= , 7) +#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5= , 0) +#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5= , 1) +#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5= , 4) +#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5= , 5) +#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6= , 0) +#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6= , 1) +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6= , 2) +#define SYS_ID_AA64ISAR3_EL1 sys_reg(3, 0, 0, 6= , 3) +#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7= , 0) +#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7= , 1) +#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7= , 2) +#define SYS_ID_AA64MMFR3_EL1 sys_reg(3, 0, 0, 7= , 3) +#define SYS_ID_AA64MMFR4_EL1 sys_reg(3, 0, 0, 7= , 4) +#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0= , 0) +#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0= , 2) +#define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2= , 4) +#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2= , 0) +#define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2= , 6) +#define SYS_GCSCR_EL1 sys_reg(3, 0, 2, 5= , 0) +#define SYS_GCSPR_EL1 sys_reg(3, 0, 2, 5= , 1) +#define SYS_GCSCRE0_EL1 sys_reg(3, 0, 2, 5= , 2) +#define SYS_ALLINT sys_reg(3, 0, 4, 3= , 0) +#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0= , 0) +#define SYS_PMICNTR_EL0 sys_reg(3, 3, 9, 4= , 0) +#define SYS_PMICFILTR_EL0 sys_reg(3, 3, 9, 6= , 0) +#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9= , 0) +#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9= , 1) +#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9= , 2) +#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9= , 3) +#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9= , 4) +#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9= , 5) +#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9= , 6) +#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9= , 7) +#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 1= 0, 0) +#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 1= 0, 1) +#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 1= 0, 3) +#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 1= 0, 7) +#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 1= 2, 5) +#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, = 0, 1) +#define SYS_RCWSMASK_EL1 sys_reg(3, 0, 13, = 0, 3) +#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, = 0, 4) +#define SYS_RCWMASK_EL1 sys_reg(3, 0, 13, = 0, 6) +#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, = 0, 7) +#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0= , 0) +#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0= , 1) +#define SYS_CCSIDR2_EL1 sys_reg(3, 1, 0, 0= , 2) +#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0= , 4) +#define SYS_SMIDR_EL1 sys_reg(3, 1, 0, 0= , 6) +#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0= , 0) +#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0= , 1) +#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0= , 7) +#define SYS_GCSPR_EL0 sys_reg(3, 3, 2, 5= , 1) +#define SYS_SVCR sys_reg(3, 3, 4, 2= , 2) +#define SYS_FPMR sys_reg(3, 3, 4, 4= , 2) +#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1= , 4) +#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1= , 5) +#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1= , 6) +#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1= , 4) +#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1= , 5) +#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1= , 6) +#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2= , 0) +#define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2= , 2) +#define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2= , 5) +#define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2= , 6) +#define SYS_GCSCR_EL2 sys_reg(3, 4, 2, 5= , 0) +#define SYS_GCSPR_EL2 sys_reg(3, 4, 2, 5= , 1) +#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0= , 0) +#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0= , 0) +#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9= , 0) +#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, = 0, 1) +#define SYS_CNTPOFF_EL2 sys_reg(3, 4, 14, = 0, 6) +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0= , 2) +#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2= , 0) +#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2= , 6) +#define SYS_GCSCR_EL12 sys_reg(3, 5, 2, 5= , 0) +#define SYS_GCSPR_EL12 sys_reg(3, 5, 2, 5= , 1) +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0= , 0) +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, = 0, 1) +#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0= , 0) +#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0= , 1) +#define SYS_TCR2_EL1 sys_reg(3, 0, 2, 0= , 3) +#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0= , 3) +#define SYS_TCR2_EL2 sys_reg(3, 4, 2, 0= , 3) +#define SYS_MAIR2_EL1 sys_reg(3, 0, 10, = 2, 1) +#define SYS_MAIR2_EL2 sys_reg(3, 4, 10, = 1, 1) +#define SYS_AMAIR2_EL1 sys_reg(3, 0, 10, = 3, 1) +#define SYS_AMAIR2_EL2 sys_reg(3, 4, 10, = 3, 1) +#define SYS_PIRE0_EL1 sys_reg(3, 0, 10, = 2, 2) +#define SYS_PIRE0_EL12 sys_reg(3, 5, 10, = 2, 2) +#define SYS_PIR_EL1 sys_reg(3, 0, 10, = 2, 3) +#define SYS_PIR_EL12 sys_reg(3, 5, 10, = 2, 3) +#define SYS_PIR_EL2 sys_reg(3, 4, 10, = 2, 3) +#define SYS_POR_EL0 sys_reg(3, 3, 10, = 2, 4) +#define SYS_POR_EL1 sys_reg(3, 0, 10, = 2, 4) +#define SYS_POR_EL12 sys_reg(3, 5, 10, = 2, 4) +#define SYS_S2POR_EL1 sys_reg(3, 0, 10, = 2, 5) +#define SYS_S2PIR_EL2 sys_reg(3, 4, 10, = 2, 5) +#define SYS_LORSA_EL1 sys_reg(3, 0, 10, = 4, 0) +#define SYS_LOREA_EL1 sys_reg(3, 0, 10, = 4, 1) +#define SYS_LORN_EL1 sys_reg(3, 0, 10, = 4, 2) +#define SYS_LORC_EL1 sys_reg(3, 0, 10, = 4, 3) +#define SYS_LORID_EL1 sys_reg(3, 0, 10, = 4, 7) +#define SYS_ISR_EL1 sys_reg(3, 0, 12, = 1, 0) +#define SYS_ICC_NMIAR1_EL1 sys_reg(3, 0, 12, = 9, 5) +#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 1= 1, 0) +#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 1= 1, 1) +#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 1= 1, 2) +#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 1= 1, 3) +#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 1= 1, 4) +#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 1= 1, 6) +#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 1= 1, 7) =20 -#endif +#endif /* ARM_CPU_SYSREGS_H */ diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-pro= perties.c index 753e7c9127..4a3106cc48 100644 --- a/target/arm/cpu-sysreg-properties.c +++ b/target/arm/cpu-sysreg-properties.c @@ -1,24 +1,3 @@ -/* - * QEMU ARM CPU SYSREG PROPERTIES - * to be generated from linux sysreg - * - * Copyright (c) 2024, Inc. 2024 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see - * - */ - #include "cpu-custom.h" =20 ARM64SysReg arm64_id_regs[NR_ID_REGS]; @@ -26,16 +5,678 @@ ARM64SysReg arm64_id_regs[NR_ID_REGS]; void initialize_cpu_sysreg_properties(void) { memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NR_ID_REGS); + + /* ID_PFR0_EL1 */ + ARM64SysReg *ID_PFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 0); + ID_PFR0_EL1->name =3D "ID_PFR0_EL1"; + arm64_sysreg_add_field(ID_PFR0_EL1, "RAS", 28, 31); + arm64_sysreg_add_field(ID_PFR0_EL1, "DIT", 24, 27); + arm64_sysreg_add_field(ID_PFR0_EL1, "AMU", 20, 23); + arm64_sysreg_add_field(ID_PFR0_EL1, "CSV2", 16, 19); + arm64_sysreg_add_field(ID_PFR0_EL1, "State3", 12, 15); + arm64_sysreg_add_field(ID_PFR0_EL1, "State2", 8, 11); + arm64_sysreg_add_field(ID_PFR0_EL1, "State1", 4, 7); + arm64_sysreg_add_field(ID_PFR0_EL1, "State0", 0, 3); + + /* ID_PFR1_EL1 */ + ARM64SysReg *ID_PFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 1); + ID_PFR1_EL1->name =3D "ID_PFR1_EL1"; + arm64_sysreg_add_field(ID_PFR1_EL1, "GIC", 28, 31); + arm64_sysreg_add_field(ID_PFR1_EL1, "Virt_frac", 24, 27); + arm64_sysreg_add_field(ID_PFR1_EL1, "Sec_frac", 20, 23); + arm64_sysreg_add_field(ID_PFR1_EL1, "GenTimer", 16, 19); + arm64_sysreg_add_field(ID_PFR1_EL1, "Virtualization", 12, 15); + arm64_sysreg_add_field(ID_PFR1_EL1, "MProgMod", 8, 11); + arm64_sysreg_add_field(ID_PFR1_EL1, "Security", 4, 7); + arm64_sysreg_add_field(ID_PFR1_EL1, "ProgMod", 0, 3); + + /* ID_DFR0_EL1 */ + ARM64SysReg *ID_DFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 2); + ID_DFR0_EL1->name =3D "ID_DFR0_EL1"; + arm64_sysreg_add_field(ID_DFR0_EL1, "TraceFilt", 28, 31); + arm64_sysreg_add_field(ID_DFR0_EL1, "PerfMon", 24, 27); + arm64_sysreg_add_field(ID_DFR0_EL1, "MProfDbg", 20, 23); + arm64_sysreg_add_field(ID_DFR0_EL1, "MMapTrc", 16, 19); + arm64_sysreg_add_field(ID_DFR0_EL1, "CopTrc", 12, 15); + arm64_sysreg_add_field(ID_DFR0_EL1, "MMapDbg", 8, 11); + arm64_sysreg_add_field(ID_DFR0_EL1, "CopSDbg", 4, 7); + arm64_sysreg_add_field(ID_DFR0_EL1, "CopDbg", 0, 3); + + /* ID_AFR0_EL1 */ + ARM64SysReg *ID_AFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 3); + ID_AFR0_EL1->name =3D "ID_AFR0_EL1"; + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF3", 12, 15); + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF2", 8, 11); + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF1", 4, 7); + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF0", 0, 3); + + /* ID_MMFR0_EL1 */ + ARM64SysReg *ID_MMFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 4); + ID_MMFR0_EL1->name =3D "ID_MMFR0_EL1"; + arm64_sysreg_add_field(ID_MMFR0_EL1, "InnerShr", 28, 31); + arm64_sysreg_add_field(ID_MMFR0_EL1, "FCSE", 24, 27); + arm64_sysreg_add_field(ID_MMFR0_EL1, "AuxReg", 20, 23); + arm64_sysreg_add_field(ID_MMFR0_EL1, "TCM", 16, 19); + arm64_sysreg_add_field(ID_MMFR0_EL1, "ShareLvl", 12, 15); + arm64_sysreg_add_field(ID_MMFR0_EL1, "OuterShr", 8, 11); + arm64_sysreg_add_field(ID_MMFR0_EL1, "PMSA", 4, 7); + arm64_sysreg_add_field(ID_MMFR0_EL1, "VMSA", 0, 3); + + /* ID_MMFR1_EL1 */ + ARM64SysReg *ID_MMFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 5); + ID_MMFR1_EL1->name =3D "ID_MMFR1_EL1"; + arm64_sysreg_add_field(ID_MMFR1_EL1, "BPred", 28, 31); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1TstCln", 24, 27); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1Uni", 20, 23); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1Hvd", 16, 19); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1UniSW", 12, 15); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1HvdSW", 8, 11); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1UniVA", 4, 7); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1HvdVA", 0, 3); + + /* ID_MMFR2_EL1 */ + ARM64SysReg *ID_MMFR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 6); + ID_MMFR2_EL1->name =3D "ID_MMFR2_EL1"; + arm64_sysreg_add_field(ID_MMFR2_EL1, "HWAccFlg", 28, 31); + arm64_sysreg_add_field(ID_MMFR2_EL1, "WFIStall", 24, 27); + arm64_sysreg_add_field(ID_MMFR2_EL1, "MemBarr", 20, 23); + arm64_sysreg_add_field(ID_MMFR2_EL1, "UniTLB", 16, 19); + arm64_sysreg_add_field(ID_MMFR2_EL1, "HvdTLB", 12, 15); + arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdRng", 8, 11); + arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdBG", 4, 7); + arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdFG", 0, 3); + + /* ID_MMFR3_EL1 */ + ARM64SysReg *ID_MMFR3_EL1 =3D arm64_sysreg_get(3, 0, 0, 1, 7); + ID_MMFR3_EL1->name =3D "ID_MMFR3_EL1"; + arm64_sysreg_add_field(ID_MMFR3_EL1, "Supersec", 28, 31); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CMemSz", 24, 27); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CohWalk", 20, 23); + arm64_sysreg_add_field(ID_MMFR3_EL1, "PAN", 16, 19); + arm64_sysreg_add_field(ID_MMFR3_EL1, "MaintBcst", 12, 15); + arm64_sysreg_add_field(ID_MMFR3_EL1, "BPMaint", 8, 11); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CMaintSW", 4, 7); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CMaintVA", 0, 3); + + /* ID_ISAR0_EL1 */ + ARM64SysReg *ID_ISAR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 0); + ID_ISAR0_EL1->name =3D "ID_ISAR0_EL1"; + arm64_sysreg_add_field(ID_ISAR0_EL1, "Divide", 24, 27); + arm64_sysreg_add_field(ID_ISAR0_EL1, "Debug", 20, 23); + arm64_sysreg_add_field(ID_ISAR0_EL1, "Coproc", 16, 19); + arm64_sysreg_add_field(ID_ISAR0_EL1, "CmpBranch", 12, 15); + arm64_sysreg_add_field(ID_ISAR0_EL1, "BitField", 8, 11); + arm64_sysreg_add_field(ID_ISAR0_EL1, "BitCount", 4, 7); + arm64_sysreg_add_field(ID_ISAR0_EL1, "Swap", 0, 3); + + /* ID_ISAR1_EL1 */ + ARM64SysReg *ID_ISAR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 1); + ID_ISAR1_EL1->name =3D "ID_ISAR1_EL1"; + arm64_sysreg_add_field(ID_ISAR1_EL1, "Jazelle", 28, 31); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Interwork", 24, 27); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Immediate", 20, 23); + arm64_sysreg_add_field(ID_ISAR1_EL1, "IfThen", 16, 19); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Extend", 12, 15); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Except_AR", 8, 11); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Except", 4, 7); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Endian", 0, 3); + + /* ID_ISAR2_EL1 */ + ARM64SysReg *ID_ISAR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 2); + ID_ISAR2_EL1->name =3D "ID_ISAR2_EL1"; + arm64_sysreg_add_field(ID_ISAR2_EL1, "Reversal", 28, 31); + arm64_sysreg_add_field(ID_ISAR2_EL1, "PSR_AR", 24, 27); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MultU", 20, 23); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MultS", 16, 19); + arm64_sysreg_add_field(ID_ISAR2_EL1, "Mult", 12, 15); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MultiAccessInt", 8, 11); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MemHint", 4, 7); + arm64_sysreg_add_field(ID_ISAR2_EL1, "LoadStore", 0, 3); + + /* ID_ISAR3_EL1 */ + ARM64SysReg *ID_ISAR3_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 3); + ID_ISAR3_EL1->name =3D "ID_ISAR3_EL1"; + arm64_sysreg_add_field(ID_ISAR3_EL1, "T32EE", 28, 31); + arm64_sysreg_add_field(ID_ISAR3_EL1, "TrueNOP", 24, 27); + arm64_sysreg_add_field(ID_ISAR3_EL1, "T32Copy", 20, 23); + arm64_sysreg_add_field(ID_ISAR3_EL1, "TabBranch", 16, 19); + arm64_sysreg_add_field(ID_ISAR3_EL1, "SynchPrim", 12, 15); + arm64_sysreg_add_field(ID_ISAR3_EL1, "SVC", 8, 11); + arm64_sysreg_add_field(ID_ISAR3_EL1, "SIMD", 4, 7); + arm64_sysreg_add_field(ID_ISAR3_EL1, "Saturate", 0, 3); + + /* ID_ISAR4_EL1 */ + ARM64SysReg *ID_ISAR4_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 4); + ID_ISAR4_EL1->name =3D "ID_ISAR4_EL1"; + arm64_sysreg_add_field(ID_ISAR4_EL1, "SWP_frac", 28, 31); + arm64_sysreg_add_field(ID_ISAR4_EL1, "PSR_M", 24, 27); + arm64_sysreg_add_field(ID_ISAR4_EL1, "SynchPrim_frac", 20, 23); + arm64_sysreg_add_field(ID_ISAR4_EL1, "Barrier", 16, 19); + arm64_sysreg_add_field(ID_ISAR4_EL1, "SMC", 12, 15); + arm64_sysreg_add_field(ID_ISAR4_EL1, "Writeback", 8, 11); + arm64_sysreg_add_field(ID_ISAR4_EL1, "WithShifts", 4, 7); + arm64_sysreg_add_field(ID_ISAR4_EL1, "Unpriv", 0, 3); + + /* ID_ISAR5_EL1 */ + ARM64SysReg *ID_ISAR5_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 5); + ID_ISAR5_EL1->name =3D "ID_ISAR5_EL1"; + arm64_sysreg_add_field(ID_ISAR5_EL1, "VCMA", 28, 31); + arm64_sysreg_add_field(ID_ISAR5_EL1, "RDM", 24, 27); + arm64_sysreg_add_field(ID_ISAR5_EL1, "CRC32", 16, 19); + arm64_sysreg_add_field(ID_ISAR5_EL1, "SHA2", 12, 15); + arm64_sysreg_add_field(ID_ISAR5_EL1, "SHA1", 8, 11); + arm64_sysreg_add_field(ID_ISAR5_EL1, "AES", 4, 7); + arm64_sysreg_add_field(ID_ISAR5_EL1, "SEVL", 0, 3); + + /* ID_ISAR6_EL1 */ + ARM64SysReg *ID_ISAR6_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 7); + ID_ISAR6_EL1->name =3D "ID_ISAR6_EL1"; + arm64_sysreg_add_field(ID_ISAR6_EL1, "I8MM", 24, 27); + arm64_sysreg_add_field(ID_ISAR6_EL1, "BF16", 20, 23); + arm64_sysreg_add_field(ID_ISAR6_EL1, "SPECRES", 16, 19); + arm64_sysreg_add_field(ID_ISAR6_EL1, "SB", 12, 15); + arm64_sysreg_add_field(ID_ISAR6_EL1, "FHM", 8, 11); + arm64_sysreg_add_field(ID_ISAR6_EL1, "DP", 4, 7); + arm64_sysreg_add_field(ID_ISAR6_EL1, "JSCVT", 0, 3); + + /* ID_MMFR4_EL1 */ + ARM64SysReg *ID_MMFR4_EL1 =3D arm64_sysreg_get(3, 0, 0, 2, 6); + ID_MMFR4_EL1->name =3D "ID_MMFR4_EL1"; + arm64_sysreg_add_field(ID_MMFR4_EL1, "EVT", 28, 31); + arm64_sysreg_add_field(ID_MMFR4_EL1, "CCIDX", 24, 27); + arm64_sysreg_add_field(ID_MMFR4_EL1, "LSM", 20, 23); + arm64_sysreg_add_field(ID_MMFR4_EL1, "HPDS", 16, 19); + arm64_sysreg_add_field(ID_MMFR4_EL1, "CnP", 12, 15); + arm64_sysreg_add_field(ID_MMFR4_EL1, "XNX", 8, 11); + arm64_sysreg_add_field(ID_MMFR4_EL1, "AC2", 4, 7); + arm64_sysreg_add_field(ID_MMFR4_EL1, "SpecSEI", 0, 3); + + /* MVFR0_EL1 */ + ARM64SysReg *MVFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 3, 0); + MVFR0_EL1->name =3D "MVFR0_EL1"; + arm64_sysreg_add_field(MVFR0_EL1, "FPRound", 28, 31); + arm64_sysreg_add_field(MVFR0_EL1, "FPShVec", 24, 27); + arm64_sysreg_add_field(MVFR0_EL1, "FPSqrt", 20, 23); + arm64_sysreg_add_field(MVFR0_EL1, "FPDivide", 16, 19); + arm64_sysreg_add_field(MVFR0_EL1, "FPTrap", 12, 15); + arm64_sysreg_add_field(MVFR0_EL1, "FPDP", 8, 11); + arm64_sysreg_add_field(MVFR0_EL1, "FPSP", 4, 7); + arm64_sysreg_add_field(MVFR0_EL1, "SIMDReg", 0, 3); + + /* MVFR1_EL1 */ + ARM64SysReg *MVFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 3, 1); + MVFR1_EL1->name =3D "MVFR1_EL1"; + arm64_sysreg_add_field(MVFR1_EL1, "SIMDFMAC", 28, 31); + arm64_sysreg_add_field(MVFR1_EL1, "FPHP", 24, 27); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDHP", 20, 23); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDSP", 16, 19); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDInt", 12, 15); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDLS", 8, 11); + arm64_sysreg_add_field(MVFR1_EL1, "FPDNaN", 4, 7); + arm64_sysreg_add_field(MVFR1_EL1, "FPFtZ", 0, 3); + + /* MVFR2_EL1 */ + ARM64SysReg *MVFR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 3, 2); + MVFR2_EL1->name =3D "MVFR2_EL1"; + arm64_sysreg_add_field(MVFR2_EL1, "FPMisc", 4, 7); + arm64_sysreg_add_field(MVFR2_EL1, "SIMDMisc", 0, 3); + + /* ID_PFR2_EL1 */ + ARM64SysReg *ID_PFR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 3, 4); + ID_PFR2_EL1->name =3D "ID_PFR2_EL1"; + arm64_sysreg_add_field(ID_PFR2_EL1, "RAS_frac", 8, 11); + arm64_sysreg_add_field(ID_PFR2_EL1, "SSBS", 4, 7); + arm64_sysreg_add_field(ID_PFR2_EL1, "CSV3", 0, 3); + + /* ID_DFR1_EL1 */ + ARM64SysReg *ID_DFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 3, 5); + ID_DFR1_EL1->name =3D "ID_DFR1_EL1"; + arm64_sysreg_add_field(ID_DFR1_EL1, "HPMN0", 4, 7); + arm64_sysreg_add_field(ID_DFR1_EL1, "MTPMU", 0, 3); + + /* ID_MMFR5_EL1 */ + ARM64SysReg *ID_MMFR5_EL1 =3D arm64_sysreg_get(3, 0, 0, 3, 6); + ID_MMFR5_EL1->name =3D "ID_MMFR5_EL1"; + arm64_sysreg_add_field(ID_MMFR5_EL1, "nTLBPA", 4, 7); + arm64_sysreg_add_field(ID_MMFR5_EL1, "ETS", 0, 3); + + /* ID_AA64PFR0_EL1 */ + ARM64SysReg *ID_AA64PFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 4, 0); + ID_AA64PFR0_EL1->name =3D "ID_AA64PFR0_EL1"; + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "CSV3", 60, 63); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "CSV2", 56, 59); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "RME", 52, 55); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "DIT", 48, 51); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AMU", 44, 47); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "MPAM", 40, 43); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "SEL2", 36, 39); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "SVE", 32, 35); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "RAS", 28, 31); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "GIC", 24, 27); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AdvSIMD", 20, 23); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AdvSIMD", 20, 23); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "FP", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "FP", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL3", 12, 15); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL2", 8, 11); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL1", 4, 7); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL0", 0, 3); + + /* ID_AA64PFR1_EL1 */ + ARM64SysReg *ID_AA64PFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 4, 1); + ID_AA64PFR1_EL1->name =3D "ID_AA64PFR1_EL1"; + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "PFAR", 60, 63); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "DF2", 56, 59); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTEX", 52, 55); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "THE", 48, 51); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "GCS", 44, 47); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTE_frac", 40, 43); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "NMI", 36, 39); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "CSV2_frac", 32, 35); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "RNDR_trap", 28, 31); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "SME", 24, 27); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MPAM_frac", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "RAS_frac", 12, 15); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTE", 8, 11); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "SSBS", 4, 7); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "BT", 0, 3); + + /* ID_AA64PFR2_EL1 */ + ARM64SysReg *ID_AA64PFR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 4, 2); + ID_AA64PFR2_EL1->name =3D "ID_AA64PFR2_EL1"; + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "FPMR", 32, 35); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTEFAR", 8, 11); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTESTOREONLY", 4, 7); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTEPERM", 0, 3); + + /* ID_AA64ZFR0_EL1 */ + ARM64SysReg *ID_AA64ZFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 4, 4); + ID_AA64ZFR0_EL1->name =3D "ID_AA64ZFR0_EL1"; + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F64MM", 56, 59); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F32MM", 52, 55); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "I8MM", 44, 47); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SM4", 40, 43); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SHA3", 32, 35); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "B16B16", 24, 27); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "BF16", 20, 23); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "BitPerm", 16, 19); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "AES", 4, 7); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SVEver", 0, 3); + + /* ID_AA64SMFR0_EL1 */ + ARM64SysReg *ID_AA64SMFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 4, 5); + ID_AA64SMFR0_EL1->name =3D "ID_AA64SMFR0_EL1"; + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "FA64", 63, 63); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "LUTv2", 60, 60); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SMEver", 56, 59); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I16I64", 52, 55); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F64F64", 48, 48); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I16I32", 44, 47); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "B16B16", 43, 43); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F16F16", 42, 42); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F8F16", 41, 41); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F8F32", 40, 40); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I8I32", 36, 39); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F16F32", 35, 35); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "B16F32", 34, 34); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "BI32I32", 33, 33); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F32F32", 32, 32); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8FMA", 30, 30); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8DP4", 29, 29); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8DP2", 28, 28); + + /* ID_AA64FPFR0_EL1 */ + ARM64SysReg *ID_AA64FPFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 4, 7); + ID_AA64FPFR0_EL1->name =3D "ID_AA64FPFR0_EL1"; + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8CVT", 31, 31); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8FMA", 30, 30); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8DP4", 29, 29); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8DP2", 28, 28); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8E4M3", 1, 1); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8E5M2", 0, 0); + + /* ID_AA64DFR0_EL1 */ + ARM64SysReg *ID_AA64DFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 5, 0); + ID_AA64DFR0_EL1->name =3D "ID_AA64DFR0_EL1"; + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "HPMN0", 60, 63); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "ExtTrcBuff", 56, 59); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "BRBE", 52, 55); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "MTPMU", 48, 51); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceBuffer", 44, 47); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceFilt", 40, 43); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "DoubleLock", 36, 39); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMSVer", 32, 35); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "CTX_CMPs", 28, 31); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "WRPs", 20, 23); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "BRPs", 12, 15); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMUVer", 8, 11); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceVer", 4, 7); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "DebugVer", 0, 3); + + /* ID_AA64DFR1_EL1 */ + ARM64SysReg *ID_AA64DFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 5, 1); + ID_AA64DFR1_EL1->name =3D "ID_AA64DFR1_EL1"; + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ABL_CMPs", 56, 63); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "DPFZS", 52, 55); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "EBEP", 48, 51); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ITE", 44, 47); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ABLE", 40, 43); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "PMICNTR", 36, 39); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "SPMU", 32, 35); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "CTX_CMPs", 24, 31); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "WRPs", 16, 23); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "BRPs", 8, 15); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "SYSPMUID", 0, 7); + + /* ID_AA64AFR0_EL1 */ + ARM64SysReg *ID_AA64AFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 5, 4); + ID_AA64AFR0_EL1->name =3D "ID_AA64AFR0_EL1"; + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF7", 28, 31); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF6", 24, 27); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF5", 20, 23); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF4", 16, 19); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF3", 12, 15); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF2", 8, 11); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF1", 4, 7); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF0", 0, 3); + + /* ID_AA64AFR1_EL1 */ + ARM64SysReg *ID_AA64AFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 5, 5); + ID_AA64AFR1_EL1->name =3D "ID_AA64AFR1_EL1"; + + /* ID_AA64ISAR0_EL1 */ + ARM64SysReg *ID_AA64ISAR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 6, 0); + ID_AA64ISAR0_EL1->name =3D "ID_AA64ISAR0_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "RNDR", 60, 63); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TLB", 56, 59); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TS", 52, 55); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "FHM", 48, 51); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "DP", 44, 47); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SM4", 40, 43); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SM3", 36, 39); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA3", 32, 35); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "RDM", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TME", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "ATOMIC", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "CRC32", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA2", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA1", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "AES", 4, 7); + + /* ID_AA64ISAR1_EL1 */ + ARM64SysReg *ID_AA64ISAR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 6, 1); + ID_AA64ISAR1_EL1->name =3D "ID_AA64ISAR1_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "LS64", 60, 63); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "XS", 56, 59); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "I8MM", 52, 55); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "DGH", 48, 51); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "BF16", 44, 47); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "SPECRES", 40, 43); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "SB", 36, 39); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "FRINTTS", 32, 35); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "GPI", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "GPA", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "LRCPC", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "FCMA", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "JSCVT", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "API", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "APA", 4, 7); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "DPB", 0, 3); + + /* ID_AA64ISAR2_EL1 */ + ARM64SysReg *ID_AA64ISAR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 6, 2); + ID_AA64ISAR2_EL1->name =3D "ID_AA64ISAR2_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "ATS1A", 60, 63); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "LUT", 56, 59); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "CSSC", 52, 55); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "RPRFM", 48, 51); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PRFMSLC", 40, 43); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "SYSINSTR_128", 36, 39); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "SYSREG_128", 32, 35); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "CLRBHB", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PAC_frac", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "BC", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "MOPS", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "APA3", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "GPA3", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "RPRES", 4, 7); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "WFxT", 0, 3); + + /* ID_AA64ISAR3_EL1 */ + ARM64SysReg *ID_AA64ISAR3_EL1 =3D arm64_sysreg_get(3, 0, 0, 6, 3); + ID_AA64ISAR3_EL1->name =3D "ID_AA64ISAR3_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "PACM", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "TLBIW", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "FAMINMAX", 4, 7); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "CPA", 0, 3); + + /* ID_AA64MMFR0_EL1 */ + ARM64SysReg *ID_AA64MMFR0_EL1 =3D arm64_sysreg_get(3, 0, 0, 7, 0); + ID_AA64MMFR0_EL1->name =3D "ID_AA64MMFR0_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "ECV", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "FGT", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "EXS", 44, 47); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4_2", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64_2", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN16_2", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN16", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "BIGENDEL0", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "SNSMEM", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "BIGEND", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "ASIDBITS", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "PARANGE", 0, 3); + + /* ID_AA64MMFR1_EL1 */ + ARM64SysReg *ID_AA64MMFR1_EL1 =3D arm64_sysreg_get(3, 0, 0, 7, 1); + ID_AA64MMFR1_EL1->name =3D "ID_AA64MMFR1_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "ECBHB", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "CMOW", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "TIDCP1", 52, 55); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "nTLBPA", 48, 51); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "AFP", 44, 47); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HCX", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "ETS", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "TWED", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "XNX", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "SpecSEI", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "PAN", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "LO", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HPDS", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "VH", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "VMIDBits", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HAFDBS", 0, 3); + + /* ID_AA64MMFR2_EL1 */ + ARM64SysReg *ID_AA64MMFR2_EL1 =3D arm64_sysreg_get(3, 0, 0, 7, 2); + ID_AA64MMFR2_EL1->name =3D "ID_AA64MMFR2_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "E0PD", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "EVT", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "BBM", 52, 55); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "TTL", 48, 51); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "FWB", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "IDS", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "AT", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "ST", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "NV", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "CCIDX", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "VARange", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "IESB", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "LSM", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "UAO", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "CnP", 0, 3); + + /* ID_AA64MMFR3_EL1 */ + ARM64SysReg *ID_AA64MMFR3_EL1 =3D arm64_sysreg_get(3, 0, 0, 7, 3); + ID_AA64MMFR3_EL1->name =3D "ID_AA64MMFR3_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "Spec_FPACC", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "ADERR", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SDERR", 52, 55); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "ANERR", 44, 47); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SNERR", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "D128_2", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "D128", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "MEC", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "AIE", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S2POE", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S1POE", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S2PIE", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S1PIE", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SCTLRX", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "TCRX", 0, 3); + + /* ID_AA64MMFR4_EL1 */ + ARM64SysReg *ID_AA64MMFR4_EL1 =3D arm64_sysreg_get(3, 0, 0, 7, 4); + ID_AA64MMFR4_EL1->name =3D "ID_AA64MMFR4_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E3DSE", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E2H0", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E2H0", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "NV_frac", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "FGWTE3", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "HACDBS", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "ASID2", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "EIESB", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "EIESB", 4, 7); + +/* For CPACR_EL1 fields see CPACR_ELx */ + +/* For ZCR_EL1 fields see ZCR_ELx */ + +/* For SMCR_EL1 fields see SMCR_ELx */ + +/* For GCSCR_EL1 fields see GCSCR_ELx */ + +/* For GCSPR_EL1 fields see GCSPR_ELx */ + +/* For CONTEXTIDR_EL1 fields see CONTEXTIDR_ELx */ + + /* CCSIDR_EL1 */ + ARM64SysReg *CCSIDR_EL1 =3D arm64_sysreg_get(3, 1, 0, 0, 0); + CCSIDR_EL1->name =3D "CCSIDR_EL1"; + arm64_sysreg_add_field(CCSIDR_EL1, "NumSets", 13, 27); + arm64_sysreg_add_field(CCSIDR_EL1, "Associativity", 3, 12); + arm64_sysreg_add_field(CCSIDR_EL1, "LineSize", 0, 2); + + /* CLIDR_EL1 */ + ARM64SysReg *CLIDR_EL1 =3D arm64_sysreg_get(3, 1, 0, 0, 1); + CLIDR_EL1->name =3D "CLIDR_EL1"; + arm64_sysreg_add_field(CLIDR_EL1, "Ttypen", 33, 46); + arm64_sysreg_add_field(CLIDR_EL1, "ICB", 30, 32); + arm64_sysreg_add_field(CLIDR_EL1, "LoUU", 27, 29); + arm64_sysreg_add_field(CLIDR_EL1, "LoC", 24, 26); + arm64_sysreg_add_field(CLIDR_EL1, "LoUIS", 21, 23); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype7", 18, 20); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype6", 15, 17); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype5", 12, 14); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype4", 9, 11); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype3", 6, 8); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype2", 3, 5); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype1", 0, 2); + + /* CCSIDR2_EL1 */ + ARM64SysReg *CCSIDR2_EL1 =3D arm64_sysreg_get(3, 1, 0, 0, 2); + CCSIDR2_EL1->name =3D "CCSIDR2_EL1"; + arm64_sysreg_add_field(CCSIDR2_EL1, "NumSets", 0, 23); + + /* GMID_EL1 */ + ARM64SysReg *GMID_EL1 =3D arm64_sysreg_get(3, 1, 0, 0, 4); + GMID_EL1->name =3D "GMID_EL1"; + arm64_sysreg_add_field(GMID_EL1, "BS", 0, 3); + + /* SMIDR_EL1 */ + ARM64SysReg *SMIDR_EL1 =3D arm64_sysreg_get(3, 1, 0, 0, 6); + SMIDR_EL1->name =3D "SMIDR_EL1"; + arm64_sysreg_add_field(SMIDR_EL1, "IMPLEMENTER", 24, 31); + arm64_sysreg_add_field(SMIDR_EL1, "REVISION", 16, 23); + arm64_sysreg_add_field(SMIDR_EL1, "SMPS", 15, 15); + arm64_sysreg_add_field(SMIDR_EL1, "AFFINITY", 0, 11); + + /* CSSELR_EL1 */ + ARM64SysReg *CSSELR_EL1 =3D arm64_sysreg_get(3, 2, 0, 0, 0); + CSSELR_EL1->name =3D "CSSELR_EL1"; + arm64_sysreg_add_field(CSSELR_EL1, "TnD", 4, 4); + arm64_sysreg_add_field(CSSELR_EL1, "Level", 1, 3); + arm64_sysreg_add_field(CSSELR_EL1, "InD", 0, 0); + /* CTR_EL0 */ ARM64SysReg *CTR_EL0 =3D arm64_sysreg_get(3, 3, 0, 0, 1); CTR_EL0->name =3D "CTR_EL0"; - arm64_sysreg_add_field(CTR_EL0, "TMinline", 32, 37); + arm64_sysreg_add_field(CTR_EL0, "TminLine", 32, 37); arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29); arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28); arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27); arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23); - arm64_sysreg_add_field(CTR_EL0, "DMinLine", 16, 19); + arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19); arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); -} =20 + /* DCZID_EL0 */ + ARM64SysReg *DCZID_EL0 =3D arm64_sysreg_get(3, 3, 0, 0, 7); + DCZID_EL0->name =3D "DCZID_EL0"; + arm64_sysreg_add_field(DCZID_EL0, "DZP", 4, 4); + arm64_sysreg_add_field(DCZID_EL0, "BS", 0, 3); + +/* For GCSPR_EL0 fields see GCSPR_ELx */ + +/* For HFGRTR_EL2 fields see HFGxTR_EL2 */ + +/* For HFGWTR_EL2 fields see HFGxTR_EL2 */ + +/* For ZCR_EL2 fields see ZCR_ELx */ + +/* For SMCR_EL2 fields see SMCR_ELx */ + +/* For GCSCR_EL2 fields see GCSCR_ELx */ + +/* For GCSPR_EL2 fields see GCSPR_ELx */ + +/* For CONTEXTIDR_EL2 fields see CONTEXTIDR_ELx */ + +/* For CPACR_EL12 fields see CPACR_ELx */ + +/* For ZCR_EL12 fields see ZCR_ELx */ + +/* For SMCR_EL12 fields see SMCR_ELx */ + +/* For GCSCR_EL12 fields see GCSCR_ELx */ + +/* For GCSPR_EL12 fields see GCSPR_ELx */ + +/* For CONTEXTIDR_EL12 fields see CONTEXTIDR_ELx */ + +/* For TTBR0_EL1 fields see TTBRx_EL1 */ + +/* For TTBR1_EL1 fields see TTBRx_EL1 */ + +/* For TCR2_EL1 fields see TCR2_EL1x */ + +/* For TCR2_EL12 fields see TCR2_EL1x */ + +/* For MAIR2_EL1 fields see MAIR2_ELx */ + +/* For MAIR2_EL2 fields see MAIR2_ELx */ + +/* For PIRE0_EL1 fields see PIRx_ELx */ + +/* For PIRE0_EL12 fields see PIRx_ELx */ + +/* For PIR_EL1 fields see PIRx_ELx */ + +/* For PIR_EL12 fields see PIRx_ELx */ + +/* For PIR_EL2 fields see PIRx_ELx */ + +/* For POR_EL0 fields see PIRx_ELx */ + +/* For POR_EL1 fields see PIRx_ELx */ + +/* For POR_EL12 fields see PIRx_ELx */ + +/* For S2POR_EL1 fields see PIRx_ELx */ + +/* For S2PIR_EL2 fields see PIRx_ELx */ + +} --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WasbB+l8Sq0E1hfncqKYkoiF7eukfetMDPKaKHIofd0=; b=eQP7YBYohLkYX/E1MjDdGAYffslMLAgWxJ/B5579URDh7TKWBY6b4vuTWSIlPl1ZyZyX5F D4fe3pzn2m26MDUIBKkzCSIUZeJXD5STHxTDzvno8VXDhmlHA9wJQPRDAEgznYVsJ+y1pE WlVh8/RpAP5DaG2P54LRnjivaWFr/hs= X-MC-Unique: Q9ZxuDlYMBW_Ha33cn8wwQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 16/21] arm/kvm: Allow reading all the writable ID registers Date: Fri, 25 Oct 2024 12:17:35 +0200 Message-ID: <20241025101959.601048-17-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" At the moment kvm_arm_get_host_cpu_features() reads a subset of the ID regs. As we want to introduce properties for all writable ID reg fields, we want more genericity and read more default host register values. Introduce a new get_host_cpu_idregs() helper and add a new exhaustive boolean parameter to kvm_arm_get_host_cpu_features() and kvm_arm_set_cpu_features_from_host() to select the right behavior. the host cpu model keeps the legacy behavior while the new custom model will read the legacy regs plus all the writable ones. This definitively brings some redundancy. A writable_map IdRegMap is introduced in the CPU object. A subsequent patch will populate it. Signed-off-by: Eric Auger --- target/arm/cpu.h | 3 +++ target/arm/kvm_arm.h | 9 +++++-- target/arm/cpu64.c | 4 ++-- target/arm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++--- target/arm/trace-events | 1 + 5 files changed, 63 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 30b265e9b0..96c42ac410 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1045,6 +1045,9 @@ struct ArchCPU { */ ARMIdRegsState writable_id_regs; =20 + /* ID reg writable bitmask (KVM only) */ + IdRegMap *writable_map; + /* QOM property to indicate we should use the back-compat CNTFRQ defau= lt */ bool backcompat_cntfrq; =20 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 9868065277..c2da1dffb2 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -143,8 +143,12 @@ uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu); * * Set up the ARMCPU struct fields up to match the information probed * from the host CPU. + * + * @cpu: cpu object + * @exhaustive: if true, all the feature ID regs are queried instead of + * a subset */ -void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, bool exhaustive); =20 /** * kvm_arm_add_vcpu_properties: @@ -245,7 +249,8 @@ static inline int kvm_arm_get_writable_id_regs(ARMCPU *= cpu, IdRegMap *idregmap) /* * These functions should never actually be called without KVM support. */ -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, + bool exhaustive) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9f20886668..86b0797d4b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -710,14 +710,14 @@ static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) ARMCPU *cpu =3D ARM_CPU(obj); - kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_set_cpu_features_from_host(cpu, false); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); aarch64_add_pauth_properties(obj); } #elif defined(CONFIG_HVF) ARMCPU *cpu =3D ARM_CPU(obj); - hvf_arm_set_cpu_features_from_host(cpu); + hvf_arm_set_cpu_features_from_host(cpu, false); aarch64_add_pauth_properties(obj); #else g_assert_not_reached(); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index bd53554832..a0daf4c382 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -40,6 +40,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" +#include "cpu-custom.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO @@ -255,8 +256,49 @@ static int get_host_cpu_reg64(int fd, ARMHostCPUFeatur= es *ahcf, ARMSysReg sr) return ret; } =20 +/* + * get_host_cpu_idregs: Read all the writable ID reg host values + * + * Need to be called once the writable mask has been populated + * Note we may want to read all the known id regs but some of them are not + * writable and return an error, hence the choice of reading only those wh= ich + * are writable. Those are aslo readable! + */ +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ah= cf) +{ + int err =3D 0; + int i; =20 -static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) + for (i =3D 0; i < NR_ID_REGS; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysReg *sysreg =3D sysregdesc->sysreg; + uint64_t writable_mask =3D cpu->writable_map->regs[i]; + uint64_t *reg; + int ret; + + if (!sysreg || !writable_mask) { + continue; + } + + reg =3D &ahcf->isar.idregs.regs[i]; + ret =3D read_sys_reg64(fd, reg, + ARM64_SYS_REG(sysreg->op0, sysreg->op1, + sysreg->crn, sysreg->crm, + sysreg->op2)); + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + err =3D ret; + } + } + return err; +} + +static bool +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf, + bool exhaustive) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -383,6 +425,11 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1); err |=3D get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR5_EL1); =20 + /* Make sure writable ID reg values are read */ + if (exhaustive) { + err |=3D get_host_cpu_idregs(cpu, fd, ahcf); + } + /* * DBGDIDR is a bit complicated because the kernel doesn't * provide an accessor for it in 64-bit mode, which is what this @@ -453,13 +500,13 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) return true; } =20 -void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, bool exhaustive) { CPUARMState *env =3D &cpu->env; =20 if (!arm_host_cpu_features.dtb_compatible) { if (!kvm_enabled() || - !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { + !kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features, ex= haustive)) { /* We can't report this error yet, so flag that we need to * in arm_cpu_realizefn(). */ diff --git a/target/arm/trace-events b/target/arm/trace-events index 4438dce7be..0df3bfafff 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,3 +13,4 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu gost v= alue for %s is 0x%"PRIx64 --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851729; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zbD69XCuYcyIs0z1Iu29EwF5abMuXv4H1xcBzN781Yc=; b=PTMqSo1EQqobM00GTZQEr2LM0Fwh1WKDPhrzI1izP2dhUb9h9TEbPBpUYE68byABge40mi NsJqhxUSrn4E0A+0uqhGEezxIjIi4XoYb6fZFaBA/VUXIBk2vX/mLKlBDVhHRdZy1kYqCw g/nprJcLUfdrfgsGCBD2dEAit//0CK8= X-MC-Unique: o-9TlUjEPHCugcPwj0ipvw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 17/21] arm/kvm: write back modified ID regs to KVM Date: Fri, 25 Oct 2024 12:17:36 +0200 Message-ID: <20241025101959.601048-18-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We want to give a chance to override the value of host ID regs. In a previous patch we made sure all their values could be fetched through kvm_get_one_reg() calls before their modification. After their potential modification we need to make sure we write back the values through kvm_set_one_reg() calls. Make sure the cpreg_list is modified with updated values and transfer those values back to kvm. Signed-off-by: Eric Auger --- target/arm/kvm.c | 36 +++++++++++++++++++++++++++++++++++- target/arm/trace-events | 1 + 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a0daf4c382..b63578789d 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1052,6 +1052,31 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu) } } =20 +static void kvm_arm_writable_idregs_to_cpreg_list(ARMCPU *cpu) +{ + for (int i =3D 0; i < NR_ID_REGS; i++) { + uint64_t writable_mask =3D cpu->writable_map->regs[i]; + uint64_t *cpreg; + + if (writable_mask) { + uint64_t regidx; + uint64_t previous, new; + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysReg *sr =3D sysregdesc->sysreg; + + regidx =3D ARM64_SYS_REG(sr->op0, sr->op1, sr->crn, sr->crm, s= r->op2); + cpreg =3D kvm_arm_get_cpreg_ptr(cpu, regidx); + previous =3D *cpreg; + new =3D cpu->isar.idregs.regs[i]; + if (previous !=3D new) { + *cpreg =3D new; + trace_kvm_arm_writable_idregs_to_cpreg_list(sysregdesc->na= me, + previous, new); + } + } + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -2019,7 +2044,16 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - return kvm_arm_init_cpreg_list(cpu); + ret =3D kvm_arm_init_cpreg_list(cpu); + if (ret) { + return ret; + } + /* overwrite writable ID regs with their updated property values */ + kvm_arm_writable_idregs_to_cpreg_list(cpu); + + write_list_to_kvmstate(cpu, 3); + + return 0; } =20 int kvm_arch_destroy_vcpu(CPUState *cs) diff --git a/target/arm/trace-events b/target/arm/trace-events index 0df3bfafff..668acf94ab 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -14,3 +14,4 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu gost v= alue for %s is 0x%"PRIx64 +kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851735; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bsJaZx9DYO0XWaGPB626qkTx5iT5IO+MbfgP/BEsPAA=; b=PPgm6rNJ9TkHpwMemlIIjXPrA+oAqg7ehMy4VIuul2KLX445OH6uN3UFagK49+au0daWZt jeBgmOZZUX12Nn17ekV+LooUI60KbzbMsk6GVTorofSTW9Mo/ZZxvTF8oguNZ43L/21ClB Cqu74fZeKpu9BAjZolmgbe/B+U5Jo+o= X-MC-Unique: uU8rs_HhMHOPDQJsPfQRpQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model Date: Fri, 25 Oct 2024 12:17:37 +0200 Message-ID: <20241025101959.601048-19-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This new cpu model takes by default the host cpu values. However it exposes uint64 SYSREG properties for writable ID reg fields exposed by the host kernel. Properties are named SYSREG__ with REG and FIELD being those used in linux arch/arm64/tools/sysreg. This done by matching the writable fields retrieved from the host kernel against the generated description of sysregs. An example of invocation is: -cpu custom,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 which sets DP field of ID_AA64ISAR0_EL1 to 0. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- At the moment, the custom model does not support legacy options of the host cpu model. We need to understand what we do with those latter (SVE, ...). This means that related KVM ioctl are not called yet. --- target/arm/cpu.c | 15 ++++ target/arm/cpu64.c | 153 ++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 6 ++ 3 files changed, 174 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 454d546feb..e5ac3c3e75 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1990,6 +1990,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 + /* + * If we failed to retrieve the set of writable ID registers for a "cu= stom" + * CPU model, report it here. + * In case we did get the set of writable ID registers, set the featur= es to + * the configured values here and perform some sanity checks. + */ + if (cpu->writable_id_regs =3D=3D WRITABLE_ID_REGS_NOT_DISCOVERABLE) { + error_setg(errp, "Host kernel does not support discovering " + "writable id registers"); + return; + } else if (cpu->writable_id_regs =3D=3D WRITABLE_ID_REGS_FAILED) { + error_setg(errp, "Failed to discover writable id registers"); + return; + } + if (!cpu->gt_cntfrq_hz) { /* * 0 means "the board didn't set a value, use the default". (We al= so diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 86b0797d4b..f10cc4ef8f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "cpu.h" #include "cpregs.h" #include "qemu/module.h" @@ -35,6 +36,8 @@ #include "cpu-features.h" #include "cpregs.h" #include "cpu-custom.h" +#include "cpu-sysregs.h" +#include "trace.h" =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { @@ -742,6 +745,153 @@ static void aarch64_max_initfn(Object *obj) } } =20 +#ifdef CONFIG_KVM + +static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) +{ + GList *l; + + for (l =3D reg->fields; l; l =3D l->next) { + ARM64SysRegField *field =3D (ARM64SysRegField *)l->data; + + if (i >=3D field->lower && i <=3D field->upper) { + return field; + } + } + return NULL; +} + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; + uint64_t old, value, mask; + int lower =3D field->lower; + int upper =3D field->upper; + int length =3D upper - lower + 1; + int index =3D field->index; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1 << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%lx) exceeds length of field (%d= )!", + name, value, length); + return; + } + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D value << lower; + old =3D idregs->regs[index]; + idregs->regs[index] =3D old & ~mask; + idregs->regs[index] |=3D value; + trace_set_sysreg_prop(name, old, mask, value, idregs->regs[index]); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + IdRegMap *idregs =3D &cpu->isar.idregs; + int index =3D field->index; + + error_report("%s %s", __func__, name); + visit_type_uint64(v, name, &idregs->regs[index], errp); + trace_get_sysreg_prop(name, idregs->regs[index]); +} + +/* + * decode_idreg_writemap: Generate props for writable fields + * + * @obj: CPU object + * @index: index of the sysreg + * @map: writable map for the sysreg + * @reg: description of the sysreg + */ +static int +decode_idreg_writemap(Object *obj, int index, uint64_t map, ARM64SysReg *r= eg) +{ + int i =3D ctz64(map); + int nb_sysreg_props =3D 0; + + while (map) { + ARM64SysRegField *field =3D get_field(i, reg); + int lower, upper; + uint64_t mask; + char *prop_name; + + if (!field) { + /* the field cannot be matched to any know id named field */ + warn_report("%s bit %d of %s is writable but cannot be matched= ", + __func__, i, reg->name); + warn_report("%s is cpu-sysreg-properties.c up to date?", __fun= c__); + map =3D map & ~BIT_ULL(i); + i =3D ctz64(map); + continue; + } + lower =3D field->lower; + upper =3D field->upper; + prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + trace_decode_idreg_writemap(field->name, lower, upper, prop_name); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + nb_sysreg_props++; + + mask =3D MAKE_64BIT_MASK(lower, upper - lower + 1); + map =3D map & ~mask; + i =3D ctz64(map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + +/* analyze the writable mask and generate properties for writable fields */ +static int expose_idreg_properties(Object *obj, IdRegMap *map, + ARM64SysReg *regs) +{ + int i; + + for (i =3D 0; i < NR_ID_REGS; i++) { + uint64_t mask =3D map->regs[i]; + + if (mask) { + /* reg @i has some writable fields, decode them */ + decode_idreg_writemap(obj, i, mask, ®s[i]); + } + } + return 0; +} + +static void aarch64_customcpu_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + int ret; + + cpu->writable_map =3D g_malloc(sizeof(IdRegMap)); + + /* discover via KVM_ARM_GET_REG_WRITABLE_MASKS */ + ret =3D kvm_arm_get_writable_id_regs(cpu, cpu->writable_map); + if (ret) { + /* function will have marked an error */ + return; + } + + /* populate from the host (exhaustive) , validate during realize */ + kvm_arm_set_cpu_features_from_host(cpu, true); + + /* generate SYSREG properties according to writable masks */ + expose_idreg_properties(obj, cpu->writable_map, arm64_id_regs); +} + +#endif + static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, @@ -749,6 +899,9 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, #endif +#ifdef CONFIG_KVM + { .name =3D "custom", .initfn =3D aarch64_customcpu_initfn= }, +#endif }; =20 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) diff --git a/target/arm/trace-events b/target/arm/trace-events index 668acf94ab..1b4bd5ab14 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,3 +15,9 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu gost v= alue for %s is 0x%"PRIx64 kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 + +# cpu64.c +decode_idreg_writemap(const char* name, int lower, int upper, char *prop_n= ame) "%s [%d:%d] is writable (prop %s)" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851741; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oe6BKi/vAtAI+FnjeShPy/q5uBG++u0rJX+QId15yp8=; b=YJ1V1jS9913B8cr0anFvNzAhTi6DRirhFLxFivGaj8AbctSTjBPiuCBphJa54ZAfoAYDPv yGk1doR1/1mcArrNz0dIj6x3uW/XmY3t95B0qvhB2X7a6t3x3IZ3FN4BHRpzoE0ZbHYH+G 42HQJZUB8qfCdwKb4RbxcD21UEf6MKE= X-MC-Unique: -TImg_t-Ofqy92fVKxNUJA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 19/21] virt: Allow custom vcpu model in arm virt Date: Fri, 25 Oct 2024 12:17:38 +0200 Message-ID: <20241025101959.601048-20-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Allowing the use of the custom vcpu model in ARM virt. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- hw/arm/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b0c68d66a3..edde4b5007 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3052,6 +3052,9 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) #if defined(CONFIG_KVM) || defined(CONFIG_HVF) ARM_CPU_TYPE_NAME("host"), #endif /* CONFIG_KVM || CONFIG_HVF */ +#ifdef CONFIG_KVM + ARM_CPU_TYPE_NAME("custom"), +#endif /* CONFIG_KVM */ #endif /* TARGET_AARCH64 */ ARM_CPU_TYPE_NAME("max"), NULL --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1729851848; cv=none; d=zohomail.com; s=zohoarc; b=V0HRL8Zqv6xQcM4WMj+4bunZnG43SVR7TVGx+DI6ISeMsDlrfWVpbjZsHc8r4SfpUc2t4SZk0POORAZVEgaJMt3KkIfqD4NGkpQmRjqRwSEOTSeCtJ5GuB59GYNXdKnH+ZzXqAUryC1U7VlQb/h6DzZxv5uPkk8PuHYVCHTTOfQ= ARC-Message-Signature: i=1; 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Fri, 25 Oct 2024 10:22:22 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.39.194.5]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id CF9C7196BB7D; Fri, 25 Oct 2024 10:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729851748; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8niAlscBVwwCSjLpFwC9rmVeWlBw2tXPGjOWbhlMyKg=; b=ORitAnYfUVIwf/JQm5+EcL0+r1lbhZg5UeuKb/eebMW2rzG+ZWtJvbu8+EdYEzslEaMMhj EJOcmX8Hl9x84huixqetsA+H4WwZ6GLQ1nQK9fIn0NYk/ooovzdkfMgi1sBf7LG0CEZ4Jt jvzmeQAISgx3dcYgzPm0GCPX3AtA9RY= X-MC-Unique: Jkhqw0YEO4OKyY_7Jxd8YA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 20/21] arm-qmp-cmds: introspection for custom model Date: Fri, 25 Oct 2024 12:17:39 +0200 Message-ID: <20241025101959.601048-21-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Implement the capability to query available options for the custom model. At the moment it only returns SYSREG_* options and values. Excerpt: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"custom"} {"return": {"model": {"name": "custom", "props": {"SYSREG_ID_AA64PFR0_EL1_EL3": 1224979098931106066, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, ../.. So this allows the upper stack to detect available writable ID regs and the "host passthrough model" values. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- TODO: Add the moment there is no way to test changing a given ID reg field value. ie: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"custom", "pro= p":{"SYSREG_ID_AA64ISAR0_EL1_DP":0x13}} --- target/arm/arm-qmp-cmds.c | 56 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 3cc8cc738b..4a3f0e6ac6 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "hw/boards.h" #include "kvm_arm.h" #include "qapi/error.h" @@ -98,6 +99,47 @@ static const char *cpu_model_advertised_features[] =3D { NULL }; =20 +static CpuModelExpansionInfo * +arm_query_custom_cpu_model_expansion(Object *obj, CpuModelExpansionType ty= pe, + CpuModelInfo *model, + Error **errp) +{ + /* returns id register map */ + CpuModelExpansionInfo *expansion_info; + ObjectProperty *prop; + ObjectPropertyIterator iter; + QDict *qdict_out; + + expansion_info =3D g_new0(CpuModelExpansionInfo, 1); + expansion_info->model =3D g_malloc0(sizeof(*expansion_info->model)); + expansion_info->model->name =3D g_strdup(model->name); + + qdict_out =3D qdict_new(); + + object_property_iter_init(&iter, obj); + + while ((prop =3D object_property_iter_next(&iter))) { + QObject *value; + + if (!g_str_has_prefix(prop->name, "SYSREG_")) { + continue; + } + value =3D object_property_get_qobject(obj, prop->name, &error_abor= t); + qdict_put_obj(qdict_out, prop->name, value); + } + + if (!qdict_size(qdict_out)) { + qobject_unref(qdict_out); + } else { + expansion_info->model->props =3D QOBJECT(qdict_out); + } + + object_unref(obj); + + + return expansion_info; +} + CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, CpuModelInfo *model, Error **errp) @@ -130,7 +172,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, if (kvm_enabled()) { bool supported =3D false; =20 - if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) { + if (!strcmp(model->name, "host") || !strcmp(model->name, "max") || + !strcmp(model->name, "custom")) { /* These are kvmarm's recommended cpu types */ supported =3D true; } else if (current_machine->cpu_type) { @@ -152,6 +195,17 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, =20 obj =3D object_new(object_class_get_name(oc)); =20 + /* The "custom" model is handled differently. */ + if (!strcmp(model->name, "custom")) { + expansion_info =3D arm_query_custom_cpu_model_expansion(obj, type,= model, + errp); + if (*errp) { + object_unref(obj); + return NULL; + } + return expansion_info; + } + if (model->props) { Visitor *visitor; Error *err =3D NULL; --=20 2.41.0 From nobody Sat Nov 23 17:46:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=MSq4ddAt9nr4en8DNlAY5G/Eg4aybTvpmc5alPxvkfilgwHie9dBRX87FsfIRMOlvly/V3 elBbVfpm5agAqGfoXarDChVjc1fJX8xJljU6FdVdx78GQ2WcN1x+w2DAP+QpPIhKmEYXy4 9EduQ6+oYCqf0AXA/GCCJMiOwTNNtZw= X-MC-Unique: V0zDiV5xMXC1QMg13lrBzg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 21/21] arm/cpu-features: Document custom vcpu model Date: Fri, 25 Oct 2024 12:17:40 +0200 Message-ID: <20241025101959.601048-22-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Add some documentation for the custom model. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- docs/system/arm/cpu-features.rst | 55 +++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index a5fb929243..962a2c6c26 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -2,7 +2,10 @@ Arm CPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 CPU features are optional features that a CPU of supporting type may -choose to implement or not. In QEMU, optional CPU features have +choose to implement or not. QEMU provides two different mechanisms +to configure those features: + +1. For most CPU models, optional CPU features may have corresponding boolean CPU proprieties that, when enabled, indicate that the feature is implemented, and, conversely, when disabled, indicate that it is not implemented. An example of an Arm CPU feature @@ -29,6 +32,16 @@ supports the feature. While ``aarch64`` currently only = works with KVM, it could work with TCG. CPU features that are specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 +2. Alternatively, the ``custom`` CPU model allows to configure optional +CPU features via the corresponding ID registers. The host kernel allows +to write a subset of ID register fields. The custom model exposes +properties for each write ID register fields. Those options are named +SYSREG__. IDREG and FIELD names are those used in the +ARM ARM Reference Manual. They can also be found in the linux +arch/arm64/tool/sysreg file which is used to automatically generate the +description for those registers and fields. The custom model is currently +only implemented for KVM. + CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -106,6 +119,10 @@ As expected they are now all ``false``. =20 Only the ``pmu`` CPU feature is available. =20 +Probing for the ``custom`` CPU model is working differently. CPU model +expansion will return the list of available SYSREG properties (matching +writable ID register fields) + A note about CPU feature dependencies ------------------------------------- =20 @@ -119,18 +136,30 @@ independently without error. For these reasons calle= rs should always attempt to make their desired changes all at once in order to ensure the collection is valid. =20 +When using the ``custom`` CPU model, the provided set of ID registers +is always evaluated as a whole. + A note about CPU models and KVM ------------------------------- =20 Named CPU models generally do not work with KVM. There are a few cases that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a -seattle host, but mostly if KVM is enabled the ``host`` CPU type must be -used. This means the guest is provided all the same CPU features as the -host CPU type has. And, for this reason, the ``host`` CPU type should -enable all CPU features that the host has by default. Indeed it's even -a bit strange to allow disabling CPU features that the host has when using -the ``host`` CPU type, but in the absence of CPU models it's the best we c= an -do if we want to launch guests without all the host's CPU features enabled. +seattle host, but mostly if KVM is enabled, either the ``host`` or the +``custom`` CPU types must be used. + +Using the ``host`` type means the guest is provided all the same CPU +features as the host CPU type has. And, for this reason, the ``host`` +CPU type should enable all CPU features that the host has by default. + +In case some features need to be hidden to the guest, ``custom`` model +shall be used instead. This is especially useful for migration purpose. + +The ``custom`` CPU model generally is the better choice if you want more +flexibility or stability across different machines or with different kernel +versions. However, even the ``custom`` CPU model will not allow configuring +an arbitrary set of features; the ID registers must describe a subset of t= he +host's features, and all differences to the host's configuration must actu= ally +be supported by the kernel to be deconfigured. =20 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. = The affect is not only limited to specific features, as pointed out in example @@ -167,6 +196,16 @@ disabling many SVE vector lengths would be quite verbo= se, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +The ``custom`` CPU model needs to be configured via individual ID register +field properties, for example:: + + $ qemu-system-aarch64 -M virt -cpu custom,SYSREG_ID_AA64ISAR0_EL1_DP=3D0= x0 + +This forces ID_AA64ISAR0_EL1 DP field to 0. + +Note that the other CPU feature properties are not supported when using +this model. + KVM VCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 --=20 2.41.0