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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a912d6545sm652536866b.31.2024.10.24.12.43.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Oct 2024 12:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1729798995; x=1730403795; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DQg34qAwXV1dkoltfasHGRhCwLkvl9EuX77LcykV+9c=; b=PD/Uw0x75AOlCgvZmnAHgZSmESOZjZFwt8MOJqrmdurAsV2DDyzddnewexiEQQQhCA NA5t44gcb6bRZG3eEyZuPWATFekeZeJ0q5HkIUbXrBLK4kkHdkO+CR80H3MPCfJ1kB+Q GpYhOWkQvumHPdv6IfKTWY3nSmlvuargfQrnvNxkkHWv4/SW+xmRsuJ9qkpp2mRtws7t SssufmJxbNRkiXXJut34+PVGtOZhoRFcAQ2l8ebgjTW8IZvj8SVxqq0vc+KRx9lUpnz8 3OUGHYls2c7OwbBpD1CIVV5AB7i+sLaPppbfKP9r/dtlUUlx6Pj3CpaWUR6DqVXfKZnR KoVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729798995; x=1730403795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DQg34qAwXV1dkoltfasHGRhCwLkvl9EuX77LcykV+9c=; b=HltpY2SYrtFcCOBZX/a3dl8QiKtPlIFsda43rgbwNKAW48eXqtRFIjH5F2IOPPy+dJ JCM49xu0ChTk7LTd2xe+EaGyuQDU+kZHIWU1eg5fy814eQkfwM0jYTgE7wj23Dio+R+R kXjH6yo8r7gsuzXUNZB+Nl/wmFbCYjXXEI7V8p6xyUuKfMYLlo3Sl4tQK9WtUDTbwKBC gzOXZpVxWPGcobDUV7L+wq6HXf0nu4kM7N5rkO7fLNJ0tW3qpB798trECYyUyF/jMrix U8e3IyasxovW16+1rjM+CF2WYOvQNlCRDnUC8m41ae4S05dtHbjv6l73rQUmIUrlffFs 8uxA== X-Gm-Message-State: AOJu0Yw0UBMEOtY9nOBILOb6cY/YfAMHKtkhG49Io0VexhrEtDTxUcM8 AtvT0+wmtlJZ0Ke1S3MSoJK5WmNOu8U4lPBjquKbcKP2nF23zCBzLmrfLd1Y8VWud7Z25l0kbwl ufg== X-Google-Smtp-Source: AGHT+IFa/c5x5Y4RpZADd72eqSIkPb0kJta9ubAFoaeky0eYE0NG+YFmMmwui8HaOrH5lLLZpt8d5w== X-Received: by 2002:a05:6512:3510:b0:53b:1fc6:3cf4 with SMTP id 2adb3069b0e04-53b1fc64039mr2620513e87.41.1729798994732; Thu, 24 Oct 2024 12:43:14 -0700 (PDT) From: Phil Dennis-Jordan To: qemu-devel@nongnu.org Cc: dirty@apple.com, rbolshakov@ddn.com, Phil Dennis-Jordan Subject: [PATCH 3/4] i386/hvf: Raise exception on error setting APICBASE Date: Thu, 24 Oct 2024 21:43:02 +0200 Message-Id: <20241024194303.32100-4-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20241024194303.32100-1-phil@philjordan.eu> References: <20241024194303.32100-1-phil@philjordan.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=2a00:1450:4864:20::133; envelope-from=phil@philjordan.eu; helo=mail-lf1-x133.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @philjordan-eu.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1729799065376116600 Content-Type: text/plain; charset="utf-8" When setting the APICBASE MSR to an illegal value, the APIC implementation will return an error. This change forwards that report to the guest as an exception rather than ignoring it when using the hvf accelerator. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/x86_emu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index be675bcfb71..015f760acb3 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -794,9 +794,16 @@ void simulate_wrmsr(CPUX86State *env) switch (msr) { case MSR_IA32_TSC: break; - case MSR_IA32_APICBASE: - cpu_set_apic_base(cpu->apic_state, data); + case MSR_IA32_APICBASE: { + int r; + + r =3D cpu_set_apic_base(cpu->apic_state, data); + if (r < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; --=20 2.39.3 (Apple Git-145)