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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a912d6545sm652536866b.31.2024.10.24.12.43.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Oct 2024 12:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1729798992; x=1730403792; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KTkxEBmFYjhTgE61q2Wuic/Pvst8IIWSyZemzZLXOhI=; b=s4YZ3OJxjn1rKhQETOH1KKUjkNkHWgU58ieAQvU+mr2MPqmrj2mAmBR0DIg73dRXYh 1xPaROULLSLjlg4U0Mbb70iWjkXpa8KB2UTWfz0z1b6H2oP7TI32y6Tr3wWjp7smqBcy mkv/V9StMiw9/jvFKDbZDvrvFAXbDPwWy3EEh/bn6b/zc1EyyQ7vz6rPtQX5ElZjKlri R02tXlZpvD6Inmo5MgQxXvfmeW4+QAZuDGeCzA7rxSn+pl2jYuOmqY/m66T0mKHwZjjM lG/uTsboJ2siwueBBjrWctSPWkUDk5prF7Eg36dOJKjFpEigDLj03npqXPYiWT115mni vxFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729798992; x=1730403792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KTkxEBmFYjhTgE61q2Wuic/Pvst8IIWSyZemzZLXOhI=; b=GfNxJmulh3aNzbpkrJ6689+pdTLR75BFdATxawcaNra+aznqiESfOuiN8sOh0Jdrg0 Q1K1my19i5bJVUqTOVo62FtqdY5JoMx7sbXP2mDW1xteSIOsbARI7YmSc+J12eXhePlY N24r/V8PgvivMsjF2JVqabYrmE2BzJ54uWNNWIWAwjQbufKl5ndHf47rH0RUKScqux7L aRnjWRE4JhA3SBTvQk2XW8++6tPrVuAGSmU9OKuAPOVLo+XqYJ5lxQlJuer1wohpdsM1 2neLnRDUkb/sO7NMzdL3u/mY/6N05qXeapsu0ccoPpx9dE49t2JYOIV8Zj8yPIuAxeZR nfXQ== X-Gm-Message-State: AOJu0Yyc1uo0cd9CzuM85mLt3XGDPE7lZVXgy1Y7VkMF0pmLCfdGBa14 9nrMI30UnBWtCIZBNsKgIpc6amAJSzPYtnAaXPTmClT2VkSirDLTXy9HYXkZwQ+XisDf/16lbl5 ayw== X-Google-Smtp-Source: AGHT+IHRayTsrm/xDVgQ3GClezAuv3usuxaXuzfPFbr7p8hDS25sTiuC41GxBcIKLqFSOPiFzbOBkQ== X-Received: by 2002:adf:8bdd:0:b0:37c:cdbf:2cc0 with SMTP id ffacd0b85a97d-37efcf8d06cmr5662201f8f.53.1729798992157; Thu, 24 Oct 2024 12:43:12 -0700 (PDT) From: Phil Dennis-Jordan To: qemu-devel@nongnu.org Cc: dirty@apple.com, rbolshakov@ddn.com, Phil Dennis-Jordan Subject: [PATCH 1/4] i386/hvf: Integrates x2APIC support with hvf accel Date: Thu, 24 Oct 2024 21:43:00 +0200 Message-Id: <20241024194303.32100-2-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20241024194303.32100-1-phil@philjordan.eu> References: <20241024194303.32100-1-phil@philjordan.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=2a00:1450:4864:20::435; envelope-from=phil@philjordan.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @philjordan-eu.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1729799044007116600 Support for x2APIC mode was recently introduced in the software emulated APIC implementation for TCG. Enabling it when using macOS=E2=80=99s hvf accelerator is useful and significantly helps performance, as Qemu currently uses the emulated APIC when running on hvf as well. This change wires up the read & write operations for the MSR VM exits and allow-lists the CPUID flag in the x86 hvf runtime. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/x86_cpuid.c | 4 ++-- target/i386/hvf/x86_emu.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index e56cd8411ba..4f260d46a81 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -64,8 +64,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t = idx, CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS; ecx &=3D CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | - CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | - CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE | + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_S= SE41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND; ecx |=3D CPUID_EXT_HYPERVISOR; diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 38c782b8e3b..be675bcfb71 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,6 +663,15 @@ static void exec_lods(CPUX86State *env, struct x86_dec= ode *decode) env->eip +=3D decode->len; } =20 +static void raise_exception(CPUX86State *env, int exception_index, + int error_code) +{ + env->exception_nr =3D exception_index; + env->error_code =3D error_code; + env->has_error_code =3D true; + env->exception_injected =3D 1; +} + void simulate_rdmsr(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); @@ -677,6 +686,17 @@ void simulate_rdmsr(CPUX86State *env) case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(cpu->apic_state); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + ret =3D apic_msr_read(index, &val); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + + break; + } case MSR_IA32_UCODE_REV: val =3D cpu->ucode_rev; break; @@ -777,6 +797,17 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_APICBASE: cpu_set_apic_base(cpu->apic_state, data); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + ret =3D apic_msr_write(index, data); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + + break; + } case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; --=20 2.39.3 (Apple Git-145)