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Thu, 24 Oct 2024 05:35:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGElUTr29IYXjOtHvrb+2JXgBpV6sHTF+rf7RUz4hleS5Pdbm3Za7Js2aez5VfU2Ocu//S9tg== X-Received: by 2002:a05:600c:45cd:b0:431:55bf:fe4 with SMTP id 5b1f17b1804b1-4318c75557cmr16380645e9.24.1729773313023; Thu, 24 Oct 2024 05:35:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Guenter Roeck , qemu-stable@nongnu.org Subject: [PULL 6/8] target/i386: fix CPUID check for LFENCE and SFENCE Date: Thu, 24 Oct 2024 14:34:57 +0200 Message-ID: <20241024123459.59350-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241024123459.59350-1-pbonzini@redhat.com> References: <20241024123459.59350-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.263, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.697, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1729773404621116600 Content-Type: text/plain; charset="utf-8" LFENCE and SFENCE were introduced with the original SSE instruction set; marking them incorrectly as cpuid(SSE2) causes failures for CPU models that lack SSE2, for example pentium3. Reported-by: Guenter Roeck Tested-by: Guenter Roeck Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 1f193716468..48bf730cd3e 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -345,9 +345,9 @@ static void decode_group15(DisasContext *s, CPUX86State= *env, X86OpEntry *entry, [1] =3D X86_OP_ENTRYw(RDxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_= f3), [2] =3D X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_= f3 zextT0), [3] =3D X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_= f3 zextT0), - [5] =3D X86_OP_ENTRY0(LFENCE, cpuid(SSE2) p_00), + [5] =3D X86_OP_ENTRY0(LFENCE, cpuid(SSE) p_00), [6] =3D X86_OP_ENTRY0(MFENCE, cpuid(SSE2) p_00), - [7] =3D X86_OP_ENTRY0(SFENCE, cpuid(SSE2) p_00), + [7] =3D X86_OP_ENTRY0(SFENCE, cpuid(SSE) p_00), }; =20 static const X86OpEntry group15_mem[8] =3D { --=20 2.47.0