From nobody Sat Nov 23 20:58:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729763146095200.28658862929228; Thu, 24 Oct 2024 02:45:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3uOk-00045A-4Q; Thu, 24 Oct 2024 05:44:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3uOh-00043s-Te for qemu-devel@nongnu.org; Thu, 24 Oct 2024 05:44:51 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3uOe-0002Yz-OV for qemu-devel@nongnu.org; Thu, 24 Oct 2024 05:44:51 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxTOIJFxpnGG4KAA--.23946S3; Thu, 24 Oct 2024 17:44:41 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxPMICFxpnHi0PAA--.1186S5; Thu, 24 Oct 2024 17:44:39 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 3/6] target/loongarch/kvm: Implement LoongArch PMU extension Date: Thu, 24 Oct 2024 17:26:22 +0800 Message-Id: <20241024092626.1328049-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20241024092626.1328049-1-gaosong@loongson.cn> References: <20241024092626.1328049-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxPMICFxpnHi0PAA--.1186S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1729763196366116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao Implement PMU extension for LoongArch kvm mode. Use OnOffAuto type variable pmu to check the PMU feature. If the PMU Feature is not supported with KVM host, it reports error if there is pmu=3Don command line. If there is no any command line about pmu parameter, it checks whether KVM host supports the PMU Feature and set the corresponding value in cpucfg. This patch is based on lbt patch located at https://lore.kernel.org/qemu-devel/20240904061859.86615-1-maobibo@loongso= n.cn Co-developed-by: Song Gao Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-Id: <20240918082315.2345034-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.c | 19 +++++++++++++ target/loongarch/cpu.h | 2 ++ target/loongarch/kvm/kvm.c | 41 +++++++++++++++++++++++++++ target/loongarch/loongarch-qmp-cmds.c | 2 +- 4 files changed, 63 insertions(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 29577e6b71..57cc4f314b 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -676,6 +676,18 @@ static void loongarch_set_lbt(Object *obj, bool value,= Error **errp) cpu->lbt =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; } =20 +static bool loongarch_get_pmu(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->pmu !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_pmu(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + cpu->pmu =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; +} + void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -691,6 +703,13 @@ void loongarch_cpu_post_init(Object *obj) loongarch_set_lbt); object_property_set_description(obj, "lbt", "Set off to disable Binary Tranlation."= ); + + cpu->pmu =3D ON_OFF_AUTO_AUTO; + object_property_add_bool(obj, "pmu", loongarch_get_pmu, + loongarch_set_pmu); + object_property_set_description(obj, "pmu", + "Set off to performance monitor unit."); + } else { cpu->lbt =3D ON_OFF_AUTO_OFF; } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 136866b7b8..95be58dd66 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -284,6 +284,7 @@ typedef struct LoongArchTLB LoongArchTLB; =20 enum loongarch_features { LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ + LOONGARCH_FEATURE_PMU, }; =20 typedef struct LoongArchBT { @@ -399,6 +400,7 @@ struct ArchCPU { QEMUTimer timer; uint32_t phy_id; OnOffAuto lbt; + OnOffAuto pmu; =20 /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 40115aff56..8bda8ae540 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -750,9 +750,18 @@ static bool kvm_feature_supported(CPUState *cs, enum l= oongarch_features feature) attr.attr =3D KVM_LOONGARCH_VM_FEAT_MIPSBT; ret |=3D kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); return (ret =3D=3D 0); + + case LOONGARCH_FEATURE_PMU: + attr.group =3D KVM_LOONGARCH_VM_FEAT_CTRL; + attr.attr =3D KVM_LOONGARCH_VM_FEAT_PMU; + ret =3D kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); + return (ret =3D=3D 0); + default: return false; } + + return false; } =20 static int kvm_cpu_check_lbt(CPUState *cs, Error **errp) @@ -776,6 +785,32 @@ static int kvm_cpu_check_lbt(CPUState *cs, Error **err= p) return 0; } =20 +static int kvm_cpu_check_pmu(CPUState *cs, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D cpu_env(cs); + bool kvm_supported; + + kvm_supported =3D kvm_feature_supported(cs, LOONGARCH_FEATURE_PMU); + if (cpu->pmu =3D=3D ON_OFF_AUTO_ON) { + if (!kvm_supported) { + error_setg(errp, "'pmu' feature not supported by KVM on the ho= st"); + return -ENOTSUP; + } + } else if (cpu->pmu !=3D ON_OFF_AUTO_AUTO) { + /* disable pmu if ON_OFF_AUTO_OFF is set */ + kvm_supported =3D false; + } + + if (kvm_supported) { + env->cpucfg[6] =3D FIELD_DP32(env->cpucfg[6], CPUCFG6, PMP, 1); + env->cpucfg[6] =3D FIELD_DP32(env->cpucfg[6], CPUCFG6, PMNUM, 3); + env->cpucfg[6] =3D FIELD_DP32(env->cpucfg[6], CPUCFG6, PMBITS, 63); + env->cpucfg[6] =3D FIELD_DP32(env->cpucfg[6], CPUCFG6, UPM, 1); + } + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { uint64_t val; @@ -793,6 +828,12 @@ int kvm_arch_init_vcpu(CPUState *cs) if (ret < 0) { error_report_err(local_err); } + + ret =3D kvm_cpu_check_pmu(cs, &local_err); + if (ret < 0) { + error_report_err(local_err); + } + return ret; } =20 diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loong= arch-qmp-cmds.c index c6f6e1ef85..782fd511fd 100644 --- a/target/loongarch/loongarch-qmp-cmds.c +++ b/target/loongarch/loongarch-qmp-cmds.c @@ -40,7 +40,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **= errp) } =20 static const char *cpu_model_advertised_features[] =3D { - "lsx", "lasx", "lbt", NULL + "lsx", "lasx", "lbt", "pmu", NULL }; =20 CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, --=20 2.34.1