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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729751731; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vgvXZXqOU4Mf2FXVpLUnht9rnZecqWcc79dctE4trk4=; b=f9Btf19gXZuqPf2uB/7/C+UtDmMDz0QOXzC3c1LPeausV3B18/qlMX0WAshl8+4BMyQDnu YsovkzTKxN+t8KF/x32Xhf40V64pSLOi1CGwskGgQGzMe+PqoATsqmhtLHd2XJCtacW8l2 eQGvo11s3UA4Q1rdOLcABy/moV+f7pE= X-MC-Unique: nmYO2sYSMtapAJSYGC9lxg-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/17] hw/gpio/aspeed: Support different memory region ops Date: Thu, 24 Oct 2024 08:34:53 +0200 Message-ID: <20241024063507.1585765-4-clg@redhat.com> In-Reply-To: <20241024063507.1585765-1-clg@redhat.com> References: <20241024063507.1585765-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.263, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1729751824841116600 From: Jamin Lin It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST260= 0. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change in AST2700. Each GPIO pin has their own control register. In other words, users are abl= e to set one GPIO pin=E2=80=99s direction, interrupt enable, input mask and so on in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions are not compatible AST2700. Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and use it in aspeed_gpio_realize function. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/gpio/aspeed_gpio.h | 1 + hw/gpio/aspeed_gpio.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 8cd2ff54968c..e1e6c543339e 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -77,6 +77,7 @@ struct AspeedGPIOClass { const AspeedGPIOReg *reg_table; unsigned reg_table_count; uint64_t mem_size; + const MemoryRegionOps *reg_ops; }; =20 struct AspeedGPIOState { diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 564459ad4f07..8725606aecae 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -1046,7 +1046,7 @@ static void aspeed_gpio_realize(DeviceState *dev, Err= or **errp) } } =20 - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, + memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, TYPE_ASPEED_GPIO, agc->mem_size); =20 sysbus_init_mmio(sbd, &s->iomem); @@ -1131,6 +1131,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClas= s *klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) @@ -1143,6 +1144,7 @@ static void aspeed_gpio_2500_class_init(ObjectClass *= klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *= data) @@ -1155,6 +1157,7 @@ static void aspeed_gpio_ast2600_3_3v_class_init(Objec= tClass *klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x800; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *= data) @@ -1167,6 +1170,7 @@ static void aspeed_gpio_ast2600_1_8v_class_init(Objec= tClass *klass, void *data) agc->reg_table =3D aspeed_1_8v_gpios; agc->reg_table_count =3D GPIO_1_8V_REG_ARRAY_SIZE; agc->mem_size =3D 0x800; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) @@ -1179,6 +1183,7 @@ static void aspeed_gpio_1030_class_init(ObjectClass *= klass, void *data) agc->reg_table =3D aspeed_3_3v_gpios; agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_gpio_ops; } =20 static const TypeInfo aspeed_gpio_info =3D { --=20 2.47.0