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This reverts commit d0f0cd5b1f7e9780753344548e17ad4df9fcf5d8. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 - meson.build | 24 - hw/arm/Kconfig | 30 +- rust/Kconfig | 1 - rust/hw/Kconfig | 2 - rust/hw/char/Kconfig | 3 - rust/hw/char/meson.build | 1 - rust/hw/char/pl011/.gitignore | 2 - rust/hw/char/pl011/Cargo.lock | 134 ----- rust/hw/char/pl011/Cargo.toml | 26 - rust/hw/char/pl011/README.md | 31 -- rust/hw/char/pl011/meson.build | 26 - rust/hw/char/pl011/src/device.rs | 599 -----------------= ---- rust/hw/char/pl011/src/device_class.rs | 70 --- rust/hw/char/pl011/src/lib.rs | 586 -----------------= --- rust/hw/char/pl011/src/memory_ops.rs | 59 -- rust/hw/meson.build | 1 - rust/meson.build | 2 - scripts/archive-source.sh | 4 +- scripts/make-release | 4 +- scripts/rust/rust_root_crate.sh | 13 - subprojects/.gitignore | 7 - subprojects/arbitrary-int-1-rs.wrap | 7 - subprojects/bilge-0.2-rs.wrap | 7 - subprojects/bilge-impl-0.2-rs.wrap | 7 - subprojects/either-1-rs.wrap | 7 - subprojects/itertools-0.11-rs.wrap | 7 - .../packagefiles/arbitrary-int-1-rs/meson.build | 19 - subprojects/packagefiles/bilge-0.2-rs/meson.build | 29 - .../packagefiles/bilge-impl-0.2-rs/meson.build | 45 -- subprojects/packagefiles/either-1-rs/meson.build | 24 - .../packagefiles/itertools-0.11-rs/meson.build | 30 -- .../packagefiles/proc-macro-error-1-rs/meson.build | 40 -- .../proc-macro-error-attr-1-rs/meson.build | 32 -- .../packagefiles/unicode-ident-1-rs/meson.build | 20 - subprojects/proc-macro-error-1-rs.wrap | 7 - subprojects/proc-macro-error-attr-1-rs.wrap | 7 - 37 files changed, 12 insertions(+), 1906 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c3bfa132fd6ecd61dd733b760a5e1ccd39613455..793c683aa6cccafca9c98b74b9a= 20d84211f041b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1137,11 +1137,6 @@ F: include/hw/*/microbit*.h F: tests/qtest/microbit-test.c F: docs/system/arm/nrf.rst =20 -ARM PL011 Rust device -M: Manos Pitsidianakis -S: Maintained -F: rust/hw/char/pl011/ - AVR Machines ------------- =20 diff --git a/meson.build b/meson.build index c26c417de16ad9256a019a90fd89ea990bb3f948..0d617c551e61c90c7c357c62ff5= da34437723947 100644 --- a/meson.build +++ b/meson.build @@ -3520,7 +3520,6 @@ qom_ss =3D ss.source_set() system_ss =3D ss.source_set() specific_fuzz_ss =3D ss.source_set() specific_ss =3D ss.source_set() -rust_devices_ss =3D ss.source_set() stub_ss =3D ss.source_set() trace_ss =3D ss.source_set() user_ss =3D ss.source_set() @@ -4068,29 +4067,6 @@ foreach target : target_dirs arch_srcs +=3D target_specific.sources() arch_deps +=3D target_specific.dependencies() =20 - if have_rust and have_system - target_rust =3D rust_devices_ss.apply(config_target, strict: false) - crates =3D [] - foreach dep : target_rust.dependencies() - crates +=3D dep.get_variable('crate') - endforeach - if crates.length() > 0 - rlib_rs =3D custom_target('rust_' + target.underscorify() + '.rs', - output: 'rust_' + target.underscorify() + '.= rs', - command: [find_program('scripts/rust/rust_ro= ot_crate.sh')] + crates, - capture: true, - build_by_default: true, - build_always_stale: true) - rlib =3D static_library('rust_' + target.underscorify(), - rlib_rs, - dependencies: target_rust.dependencies(), - override_options: ['rust_std=3D2021', 'build.r= ust_std=3D2021'], - rust_args: rustc_args, - rust_abi: 'c') - arch_deps +=3D declare_dependency(link_whole: [rlib]) - endif - endif - # allow using headers from the dependencies but do not include the sourc= es, # because this emulator only needs those in "objects". For external # dependencies, the full dependency is included below in the executable. diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e7fd9338d11dadb7a18032c674927db3d9887bdd..53eb7bb3d0157bb6e8e078fe73e= c66015ae0fe13 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -20,8 +20,7 @@ config ARM_VIRT select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL031 # RTC select PL061 # GPIO select GPIO_PWR @@ -74,8 +73,7 @@ config HIGHBANK select AHCI select ARM_TIMER # sp804 select ARM_V7M - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL022 # SPI select PL031 # RTC select PL061 # GPIO @@ -88,8 +86,7 @@ config INTEGRATOR depends on TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL031 # RTC select PL041 # audio select PL050 # keyboard/mouse @@ -107,8 +104,7 @@ config MUSCA default y depends on TCG && ARM select ARMSSE - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 select PL031 select SPLIT_IRQ select UNIMP @@ -172,8 +168,7 @@ config REALVIEW select WM8750 # audio codec select LSI_SCSI_PCI select PCI - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL031 # RTC select PL041 # audio codec select PL050 # keyboard/mouse @@ -198,8 +193,7 @@ config SBSA_REF select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL031 # RTC select PL061 # GPIO select USB_XHCI_SYSBUS @@ -223,8 +217,7 @@ config STELLARIS select ARM_V7M select CMSDK_APB_WATCHDOG select I2C - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL022 # SPI select PL061 # GPIO select SSD0303 # OLED display @@ -284,8 +277,7 @@ config VEXPRESS select ARM_TIMER # sp804 select LAN9118 select PFLASH_CFI01 - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select PL041 # audio codec select PL181 # display select REALVIEW @@ -370,8 +362,7 @@ config RASPI default y depends on TCG && ARM select FRAMEBUFFER - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 # UART select SDHCI select USB_DWC2 select BCM2835_SPI @@ -447,8 +438,7 @@ config XLNX_VERSAL select ARM_GIC select CPU_CLUSTER select DEVICE_TREE - select PL011 if !HAVE_RUST # UART - select X_PL011_RUST if HAVE_RUST # UART + select PL011 select CADENCE select VIRTIO_MMIO select UNIMP diff --git a/rust/Kconfig b/rust/Kconfig index f9f5c3909887451f71360a7986d79e57fdb43c91..e69de29bb2d1d6434b8b29ae775= ad8c2e48c5391 100644 --- a/rust/Kconfig +++ b/rust/Kconfig @@ -1 +0,0 @@ -source hw/Kconfig diff --git a/rust/hw/Kconfig b/rust/hw/Kconfig deleted file mode 100644 index 4d934f30afe13ddff418db8ec9e8b8eb25a9e8d0..000000000000000000000000000= 0000000000000 --- a/rust/hw/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -# devices Kconfig -source char/Kconfig diff --git a/rust/hw/char/Kconfig b/rust/hw/char/Kconfig deleted file mode 100644 index a1732a9e97fe3211547e30bc9319382e6394ed5b..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config X_PL011_RUST - bool - default y if HAVE_RUST diff --git a/rust/hw/char/meson.build b/rust/hw/char/meson.build deleted file mode 100644 index 5716dc43ef6facdcf1cc963108347bbf4d12cf0e..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/meson.build +++ /dev/null @@ -1 +0,0 @@ -subdir('pl011') diff --git a/rust/hw/char/pl011/.gitignore b/rust/hw/char/pl011/.gitignore deleted file mode 100644 index 71eaff2035d5a65b57ae32dfeecf3d87bbc7b396..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# Ignore generated bindings file overrides. -src/bindings.rs.inc diff --git a/rust/hw/char/pl011/Cargo.lock b/rust/hw/char/pl011/Cargo.lock deleted file mode 100644 index b58cebb186e99efe184117bb931a341543d4466b..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/Cargo.lock +++ /dev/null @@ -1,134 +0,0 @@ -# This file is automatically @generated by Cargo. -# It is not intended for manual editing. -version =3D 3 - -[[package]] -name =3D "arbitrary-int" -version =3D "1.2.7" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b1d= f46d" - -[[package]] -name =3D "bilge" -version =3D "0.2.0" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512e6= 7b57" -dependencies =3D [ - "arbitrary-int", - "bilge-impl", -] - -[[package]] -name =3D "bilge-impl" -version =3D "0.2.0" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "feb11e002038ad243af39c2068c8a72bcf147acf05025dcdb916fcc000ad= b2d8" -dependencies =3D [ - "itertools", - "proc-macro-error", - "proc-macro2", - "quote", - "syn", -] - -[[package]] -name =3D "either" -version =3D "1.12.0" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "3dca9240753cf90908d7e4aac30f630662b02aebaa1b58a3cadabdb23385= b58b" - -[[package]] -name =3D "itertools" -version =3D "0.11.0" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "b1c173a5686ce8bfa551b3563d0c2170bf24ca44da99c7ca4bfdab5418c3= fe57" -dependencies =3D [ - "either", -] - -[[package]] -name =3D "pl011" -version =3D "0.1.0" -dependencies =3D [ - "bilge", - "bilge-impl", - "qemu_api", - "qemu_api_macros", -] - -[[package]] -name =3D "proc-macro-error" -version =3D "1.0.4" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5c= e38c" -dependencies =3D [ - "proc-macro-error-attr", - "proc-macro2", - "quote", - "version_check", -] - -[[package]] -name =3D "proc-macro-error-attr" -version =3D "1.0.4" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35= f869" -dependencies =3D [ - "proc-macro2", - "quote", - "version_check", -] - -[[package]] -name =3D "proc-macro2" -version =3D "1.0.84" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "ec96c6a92621310b51366f1e28d05ef11489516e93be030060e5fc12024a= 49d6" -dependencies =3D [ - "unicode-ident", -] - -[[package]] -name =3D "qemu_api" -version =3D "0.1.0" - -[[package]] -name =3D "qemu_api_macros" -version =3D "0.1.0" -dependencies =3D [ - "proc-macro2", - "quote", - "syn", -] - -[[package]] -name =3D "quote" -version =3D "1.0.36" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208ac= aca7" -dependencies =3D [ - "proc-macro2", -] - -[[package]] -name =3D "syn" -version =3D "2.0.66" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cd= cff5" -dependencies =3D [ - "proc-macro2", - "quote", - "unicode-ident", -] - -[[package]] -name =3D "unicode-ident" -version =3D "1.0.12" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" - -[[package]] -name =3D "version_check" -version =3D "0.9.4" -source =3D "registry+https://github.com/rust-lang/crates.io-index" -checksum =3D "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e= 483f" diff --git a/rust/hw/char/pl011/Cargo.toml b/rust/hw/char/pl011/Cargo.toml deleted file mode 100644 index b089e3dded623131ee13b4af8145b84388755df7..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/Cargo.toml +++ /dev/null @@ -1,26 +0,0 @@ -[package] -name =3D "pl011" -version =3D "0.1.0" -edition =3D "2021" -authors =3D ["Manos Pitsidianakis "] -license =3D "GPL-2.0-or-later" -readme =3D "README.md" -homepage =3D "https://www.qemu.org" -description =3D "pl011 device model for QEMU" -repository =3D "https://gitlab.com/epilys/rust-for-qemu" -resolver =3D "2" -publish =3D false -keywords =3D [] -categories =3D [] - -[lib] -crate-type =3D ["staticlib"] - -[dependencies] -bilge =3D { version =3D "0.2.0" } -bilge-impl =3D { version =3D "0.2.0" } -qemu_api =3D { path =3D "../../../qemu-api" } -qemu_api_macros =3D { path =3D "../../../qemu-api-macros" } - -# Do not include in any global workspace -[workspace] diff --git a/rust/hw/char/pl011/README.md b/rust/hw/char/pl011/README.md deleted file mode 100644 index cd7dea31634241cbf96b0be13f21d52bbd8ae750..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/README.md +++ /dev/null @@ -1,31 +0,0 @@ -# PL011 QEMU Device Model - -This library implements a device model for the PrimeCell=C2=AE UART (PL011) -device in QEMU. - -## Build static lib - -Host build target must be explicitly specified: - -```sh -cargo build --target x86_64-unknown-linux-gnu -``` - -Replace host target triplet if necessary. - -## Generate Rust documentation - -To generate docs for this crate, including private items: - -```sh -cargo doc --no-deps --document-private-items --target x86_64-unknown-linux= -gnu -``` - -To include direct dependencies like `bilge` (bitmaps for register types): - -```sh -cargo tree --depth 1 -e normal --prefix none \ - | cut -d' ' -f1 \ - | xargs printf -- '-p %s\n' \ - | xargs cargo doc --no-deps --document-private-items --target x86_64-unkn= own-linux-gnu -``` diff --git a/rust/hw/char/pl011/meson.build b/rust/hw/char/pl011/meson.build deleted file mode 100644 index 547cca5a96f7eef284caf1949380b65f7d015d92..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/meson.build +++ /dev/null @@ -1,26 +0,0 @@ -subproject('bilge-0.2-rs', required: true) -subproject('bilge-impl-0.2-rs', required: true) - -bilge_dep =3D dependency('bilge-0.2-rs') -bilge_impl_dep =3D dependency('bilge-impl-0.2-rs') - -_libpl011_rs =3D static_library( - 'pl011', - files('src/lib.rs'), - override_options: ['rust_std=3D2021', 'build.rust_std=3D2021'], - rust_abi: 'rust', - dependencies: [ - bilge_dep, - bilge_impl_dep, - qemu_api, - qemu_api_macros, - ], -) - -rust_devices_ss.add(when: 'CONFIG_X_PL011_RUST', if_true: [declare_depende= ncy( - link_whole: [_libpl011_rs], - # Putting proc macro crates in `dependencies` is necessary for Meson to = find - # them when compiling the root per-target static rust lib. - dependencies: [bilge_impl_dep, qemu_api_macros], - variables: {'crate': 'pl011'}, -)]) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs deleted file mode 100644 index c7193b41beec0b177dbc75ac0e43fcfea4c82bfb..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/src/device.rs +++ /dev/null @@ -1,599 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -use core::{ - ffi::{c_int, c_uchar, c_uint, c_void, CStr}, - ptr::{addr_of, addr_of_mut, NonNull}, -}; - -use qemu_api::{ - bindings::{self, *}, - definitions::ObjectImpl, -}; - -use crate::{ - memory_ops::PL011_OPS, - registers::{self, Interrupt}, - RegisterOffset, -}; - -static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; - -const DATA_BREAK: u32 =3D 1 << 10; - -/// QEMU sourced constant. -pub const PL011_FIFO_DEPTH: usize =3D 16_usize; - -#[repr(C)] -#[derive(Debug, qemu_api_macros::Object)] -/// PL011 Device Model in QEMU -pub struct PL011State { - pub parent_obj: SysBusDevice, - pub iomem: MemoryRegion, - #[doc(alias =3D "fr")] - pub flags: registers::Flags, - #[doc(alias =3D "lcr")] - pub line_control: registers::LineControl, - #[doc(alias =3D "rsr")] - pub receive_status_error_clear: registers::ReceiveStatusErrorClear, - #[doc(alias =3D "cr")] - pub control: registers::Control, - pub dmacr: u32, - pub int_enabled: u32, - pub int_level: u32, - pub read_fifo: [u32; PL011_FIFO_DEPTH], - pub ilpr: u32, - pub ibrd: u32, - pub fbrd: u32, - pub ifl: u32, - pub read_pos: usize, - pub read_count: usize, - pub read_trigger: usize, - #[doc(alias =3D "chr")] - pub char_backend: CharBackend, - /// QEMU interrupts - /// - /// ```text - /// * sysbus MMIO region 0: device registers - /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) - /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) - /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) - /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) - /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) - /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) - /// ``` - #[doc(alias =3D "irq")] - pub interrupts: [qemu_irq; 6usize], - #[doc(alias =3D "clk")] - pub clock: NonNull, - #[doc(alias =3D "migrate_clk")] - pub migrate_clock: bool, -} - -impl ObjectImpl for PL011State { - type Class =3D PL011Class; - const TYPE_INFO: qemu_api::bindings::TypeInfo =3D qemu_api::type_info!= { Self }; - const TYPE_NAME: &'static CStr =3D crate::TYPE_PL011; - const PARENT_TYPE_NAME: Option<&'static CStr> =3D Some(TYPE_SYS_BUS_DE= VICE); - const ABSTRACT: bool =3D false; - const INSTANCE_INIT: Option = =3D Some(pl011_init); - const INSTANCE_POST_INIT: Option =3D None; - const INSTANCE_FINALIZE: Option =3D None; -} - -#[repr(C)] -pub struct PL011Class { - _inner: [u8; 0], -} - -impl qemu_api::definitions::Class for PL011Class { - const CLASS_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), - > =3D Some(crate::device_class::pl011_class_init); - const CLASS_BASE_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), - > =3D None; -} - -#[used] -pub static CLK_NAME: &CStr =3D c"clk"; - -impl PL011State { - /// Initializes a pre-allocated, unitialized instance of `PL011State`. - /// - /// # Safety - /// - /// `self` must point to a correctly sized and aligned location for the - /// `PL011State` type. It must not be called more than once on the same - /// location/instance. All its fields are expected to hold unitialized - /// values with the sole exception of `parent_obj`. - pub unsafe fn init(&mut self) { - let dev =3D addr_of_mut!(*self).cast::(); - // SAFETY: - // - // self and self.iomem are guaranteed to be valid at this point si= nce callers - // must make sure the `self` reference is valid. - unsafe { - memory_region_init_io( - addr_of_mut!(self.iomem), - addr_of_mut!(*self).cast::(), - &PL011_OPS, - addr_of_mut!(*self).cast::(), - Self::TYPE_INFO.name, - 0x1000, - ); - let sbd =3D addr_of_mut!(*self).cast::(); - sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); - for irq in self.interrupts.iter_mut() { - sysbus_init_irq(sbd, irq); - } - } - // SAFETY: - // - // self.clock is not initialized at this point; but since `NonNull= <_>` is Copy, - // we can overwrite the undefined value without side effects. This= is - // safe since all PL011State instances are created by QOM code whi= ch - // calls this function to initialize the fields; therefore no code= is - // able to access an invalid self.clock value. - unsafe { - self.clock =3D NonNull::new(qdev_init_clock_in( - dev, - CLK_NAME.as_ptr(), - None, /* pl011_clock_update */ - addr_of_mut!(*self).cast::(), - ClockEvent::ClockUpdate.0, - )) - .unwrap(); - } - } - - pub fn read( - &mut self, - offset: hwaddr, - _size: core::ffi::c_uint, - ) -> std::ops::ControlFlow { - use RegisterOffset::*; - - std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset= ) { - Err(v) if (0x3f8..0x400).contains(&v) =3D> { - u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) - } - Err(_) =3D> { - // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); - 0 - } - Ok(DR) =3D> { - // s->flags &=3D ~PL011_FLAG_RXFF; - self.flags.set_receive_fifo_full(false); - let c =3D self.read_fifo[self.read_pos]; - if self.read_count > 0 { - self.read_count -=3D 1; - self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); - } - if self.read_count =3D=3D 0 { - // self.flags |=3D PL011_FLAG_RXFE; - self.flags.set_receive_fifo_empty(true); - } - if self.read_count + 1 =3D=3D self.read_trigger { - //self.int_level &=3D ~ INT_RX; - self.int_level &=3D !registers::INT_RX; - } - // Update error bits. - self.receive_status_error_clear =3D c.to_be_bytes()[3].int= o(); - self.update(); - // Must call qemu_chr_fe_accept_input, so return Continue: - return std::ops::ControlFlow::Continue(c.into()); - } - Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(), - Ok(FR) =3D> u16::from(self.flags).into(), - Ok(FBRD) =3D> self.fbrd.into(), - Ok(ILPR) =3D> self.ilpr.into(), - Ok(IBRD) =3D> self.ibrd.into(), - Ok(LCR_H) =3D> u16::from(self.line_control).into(), - Ok(CR) =3D> { - // We exercise our self-control. - u16::from(self.control).into() - } - Ok(FLS) =3D> self.ifl.into(), - Ok(IMSC) =3D> self.int_enabled.into(), - Ok(RIS) =3D> self.int_level.into(), - Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), - Ok(ICR) =3D> { - // "The UARTICR Register is the interrupt clear register a= nd is write-only" - // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR - 0 - } - Ok(DMACR) =3D> self.dmacr.into(), - }) - } - - pub fn write(&mut self, offset: hwaddr, value: u64) { - // eprintln!("write offset {offset} value {value}"); - use RegisterOffset::*; - let value: u32 =3D value as u32; - match RegisterOffset::try_from(offset) { - Err(_bad_offset) =3D> { - eprintln!("write bad offset {offset} value {value}"); - } - Ok(DR) =3D> { - // ??? Check if transmitter is enabled. - let ch: u8 =3D value as u8; - // XXX this blocks entire thread. Rewrite to use - // qemu_chr_fe_write and background I/O callbacks - - // SAFETY: self.char_backend is a valid CharBackend instan= ce after it's been - // initialized in realize(). - unsafe { - qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),= &ch, 1); - } - self.loopback_tx(value); - self.int_level |=3D registers::INT_TX; - self.update(); - } - Ok(RSR) =3D> { - self.receive_status_error_clear =3D 0.into(); - } - Ok(FR) =3D> { - // flag writes are ignored - } - Ok(ILPR) =3D> { - self.ilpr =3D value; - } - Ok(IBRD) =3D> { - self.ibrd =3D value; - } - Ok(FBRD) =3D> { - self.fbrd =3D value; - } - Ok(LCR_H) =3D> { - let value =3D value as u16; - let new_val: registers::LineControl =3D value.into(); - // Reset the FIFO state on FIFO enable or disable - if bool::from(self.line_control.fifos_enabled()) - ^ bool::from(new_val.fifos_enabled()) - { - self.reset_fifo(); - } - if self.line_control.send_break() ^ new_val.send_break() { - let mut break_enable: c_int =3D new_val.send_break().i= nto(); - // SAFETY: self.char_backend is a valid CharBackend in= stance after it's been - // initialized in realize(). - unsafe { - qemu_chr_fe_ioctl( - addr_of_mut!(self.char_backend), - CHR_IOCTL_SERIAL_SET_BREAK as i32, - addr_of_mut!(break_enable).cast::(), - ); - } - self.loopback_break(break_enable > 0); - } - self.line_control =3D new_val; - self.set_read_trigger(); - } - Ok(CR) =3D> { - // ??? Need to implement the enable bit. - let value =3D value as u16; - self.control =3D value.into(); - self.loopback_mdmctrl(); - } - Ok(FLS) =3D> { - self.ifl =3D value; - self.set_read_trigger(); - } - Ok(IMSC) =3D> { - self.int_enabled =3D value; - self.update(); - } - Ok(RIS) =3D> {} - Ok(MIS) =3D> {} - Ok(ICR) =3D> { - self.int_level &=3D !value; - self.update(); - } - Ok(DMACR) =3D> { - self.dmacr =3D value; - if value & 3 > 0 { - // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); - eprintln!("pl011: DMA not implemented"); - } - } - } - } - - #[inline] - fn loopback_tx(&mut self, value: u32) { - if !self.loopback_enabled() { - return; - } - - // Caveat: - // - // In real hardware, TX loopback happens at the serial-bit level - // and then reassembled by the RX logics back into bytes and placed - // into the RX fifo. That is, loopback happens after TX fifo. - // - // Because the real hardware TX fifo is time-drained at the frame - // rate governed by the configured serial format, some loopback - // bytes in TX fifo may still be able to get into the RX fifo - // that could be full at times while being drained at software - // pace. - // - // In such scenario, the RX draining pace is the major factor - // deciding which loopback bytes get into the RX fifo, unless - // hardware flow-control is enabled. - // - // For simplicity, the above described is not emulated. - self.put_fifo(value); - } - - fn loopback_mdmctrl(&mut self) { - if !self.loopback_enabled() { - return; - } - - /* - * Loopback software-driven modem control outputs to modem status = inputs: - * FR.RI <=3D CR.Out2 - * FR.DCD <=3D CR.Out1 - * FR.CTS <=3D CR.RTS - * FR.DSR <=3D CR.DTR - * - * The loopback happens immediately even if this call is triggered - * by setting only CR.LBE. - * - * CTS/RTS updates due to enabled hardware flow controls are not - * dealt with here. - */ - - //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | - // PL011_FLAG_DSR | PL011_FLAG_CTS); - //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; - //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; - //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; - //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; - // - self.flags.set_ring_indicator(self.control.out_2()); - self.flags.set_data_carrier_detect(self.control.out_1()); - self.flags.set_clear_to_send(self.control.request_to_send()); - self.flags - .set_data_set_ready(self.control.data_transmit_ready()); - - // Change interrupts based on updated FR - let mut il =3D self.int_level; - - il &=3D !Interrupt::MS; - //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; - //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; - //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; - //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; - - if self.flags.data_set_ready() { - il |=3D Interrupt::DSR as u32; - } - if self.flags.data_carrier_detect() { - il |=3D Interrupt::DCD as u32; - } - if self.flags.clear_to_send() { - il |=3D Interrupt::CTS as u32; - } - if self.flags.ring_indicator() { - il |=3D Interrupt::RI as u32; - } - self.int_level =3D il; - self.update(); - } - - fn loopback_break(&mut self, enable: bool) { - if enable { - self.loopback_tx(DATA_BREAK); - } - } - - fn set_read_trigger(&mut self) { - self.read_trigger =3D 1; - } - - pub fn realize(&mut self) { - // SAFETY: self.char_backend has the correct size and alignment fo= r a - // CharBackend object, and its callbacks are of the correct types. - unsafe { - qemu_chr_fe_set_handlers( - addr_of_mut!(self.char_backend), - Some(pl011_can_receive), - Some(pl011_receive), - Some(pl011_event), - None, - addr_of_mut!(*self).cast::(), - core::ptr::null_mut(), - true, - ); - } - } - - pub fn reset(&mut self) { - self.line_control.reset(); - self.receive_status_error_clear.reset(); - self.dmacr =3D 0; - self.int_enabled =3D 0; - self.int_level =3D 0; - self.ilpr =3D 0; - self.ibrd =3D 0; - self.fbrd =3D 0; - self.read_trigger =3D 1; - self.ifl =3D 0x12; - self.control.reset(); - self.flags =3D 0.into(); - self.reset_fifo(); - } - - pub fn reset_fifo(&mut self) { - self.read_count =3D 0; - self.read_pos =3D 0; - - /* Reset FIFO flags */ - self.flags.reset(); - } - - pub fn can_receive(&self) -> bool { - // trace_pl011_can_receive(s->lcr, s->read_count, r); - self.read_count < self.fifo_depth() - } - - pub fn event(&mut self, event: QEMUChrEvent) { - if event =3D=3D bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.f= ifo_enabled() { - self.put_fifo(DATA_BREAK); - self.receive_status_error_clear.set_break_error(true); - } - } - - #[inline] - pub fn fifo_enabled(&self) -> bool { - matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) - } - - #[inline] - pub fn loopback_enabled(&self) -> bool { - self.control.enable_loopback() - } - - #[inline] - pub fn fifo_depth(&self) -> usize { - // Note: FIFO depth is expected to be power-of-2 - if self.fifo_enabled() { - return PL011_FIFO_DEPTH; - } - 1 - } - - pub fn put_fifo(&mut self, value: c_uint) { - let depth =3D self.fifo_depth(); - assert!(depth > 0); - let slot =3D (self.read_pos + self.read_count) & (depth - 1); - self.read_fifo[slot] =3D value; - self.read_count +=3D 1; - // s->flags &=3D ~PL011_FLAG_RXFE; - self.flags.set_receive_fifo_empty(false); - if self.read_count =3D=3D depth { - //s->flags |=3D PL011_FLAG_RXFF; - self.flags.set_receive_fifo_full(true); - } - - if self.read_count =3D=3D self.read_trigger { - self.int_level |=3D registers::INT_RX; - self.update(); - } - } - - pub fn update(&self) { - let flags =3D self.int_level & self.int_enabled; - for (irq, i) in self.interrupts.iter().zip(IRQMASK) { - // SAFETY: self.interrupts have been initialized in init(). - unsafe { qemu_set_irq(*irq, i32::from(flags & i !=3D 0)) }; - } - } -} - -/// Which bits in the interrupt status matter for each outbound IRQ line ? -pub const IRQMASK: [u32; 6] =3D [ - /* combined IRQ */ - Interrupt::E - | Interrupt::MS - | Interrupt::RT as u32 - | Interrupt::TX as u32 - | Interrupt::RX as u32, - Interrupt::RX as u32, - Interrupt::TX as u32, - Interrupt::RT as u32, - Interrupt::MS, - Interrupt::E, -]; - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { - unsafe { - debug_assert!(!opaque.is_null()); - let state =3D NonNull::new_unchecked(opaque.cast::()); - state.as_ref().can_receive().into() - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -/// -/// The buffer and size arguments must also be valid. -#[no_mangle] -pub unsafe extern "C" fn pl011_receive( - opaque: *mut core::ffi::c_void, - buf: *const u8, - size: core::ffi::c_int, -) { - unsafe { - debug_assert!(!opaque.is_null()); - let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); - if state.as_ref().loopback_enabled() { - return; - } - if size > 0 { - debug_assert!(!buf.is_null()); - state.as_mut().put_fifo(c_uint::from(buf.read_volatile())) - } - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { - unsafe { - debug_assert!(!opaque.is_null()); - let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); - state.as_mut().event(event) - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer for `c= hr`. -#[no_mangle] -pub unsafe extern "C" fn pl011_create( - addr: u64, - irq: qemu_irq, - chr: *mut Chardev, -) -> *mut DeviceState { - unsafe { - let dev: *mut DeviceState =3D qdev_new(PL011State::TYPE_INFO.name); - let sysbus: *mut SysBusDevice =3D dev.cast::(); - - qdev_prop_set_chr(dev, bindings::TYPE_CHARDEV.as_ptr(), chr); - sysbus_realize_and_unref(sysbus, addr_of!(error_fatal) as *mut *mu= t Error); - sysbus_mmio_map(sysbus, 0, addr); - sysbus_connect_irq(sysbus, 0, irq); - dev - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_init(obj: *mut Object) { - unsafe { - debug_assert!(!obj.is_null()); - let mut state =3D NonNull::new_unchecked(obj.cast::()); - state.as_mut().init(); - } -} diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr= c/device_class.rs deleted file mode 100644 index b7ab31af02d7bb50ae94be0b153baafc7ccfa375..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/src/device_class.rs +++ /dev/null @@ -1,70 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -use core::ptr::NonNull; - -use qemu_api::{bindings::*, definitions::ObjectImpl}; - -use crate::device::PL011State; - -#[used] -pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { - name: PL011State::TYPE_INFO.name, - unmigratable: true, - ..unsafe { ::core::mem::MaybeUninit::::zeroed().as= sume_init() } -}; - -qemu_api::declare_properties! { - PL011_PROPERTIES, - qemu_api::define_property!( - c"chardev", - PL011State, - char_backend, - unsafe { &qdev_prop_chr }, - CharBackend - ), - qemu_api::define_property!( - c"migrate-clk", - PL011State, - migrate_clock, - unsafe { &qdev_prop_bool }, - bool - ), -} - -qemu_api::device_class_init! { - pl011_class_init, - props =3D> PL011_PROPERTIES, - realize_fn =3D> Some(pl011_realize), - legacy_reset_fn =3D> Some(pl011_reset), - vmsd =3D> VMSTATE_PL011, -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { - unsafe { - assert!(!dev.is_null()); - let mut state =3D NonNull::new_unchecked(dev.cast::()); - state.as_mut().realize(); - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { - unsafe { - assert!(!dev.is_null()); - let mut state =3D NonNull::new_unchecked(dev.cast::()); - state.as_mut().reset(); - } -} diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs deleted file mode 100644 index 2939ee50c99ceaacf6ec68127272d58814e33679..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/src/lib.rs +++ /dev/null @@ -1,586 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later -// -// PL011 QEMU Device Model -// -// This library implements a device model for the PrimeCell=C2=AE UART (PL= 011) -// device in QEMU. -// -#![doc =3D include_str!("../README.md")] -//! # Library crate -//! -//! See [`PL011State`](crate::device::PL011State) for the device model typ= e and -//! the [`registers`] module for register types. - -#![deny( - rustdoc::broken_intra_doc_links, - rustdoc::redundant_explicit_links, - clippy::correctness, - clippy::suspicious, - clippy::complexity, - clippy::perf, - clippy::cargo, - clippy::nursery, - clippy::style, - // restriction group - clippy::dbg_macro, - clippy::as_underscore, - clippy::assertions_on_result_states, - // pedantic group - clippy::doc_markdown, - clippy::borrow_as_ptr, - clippy::cast_lossless, - clippy::option_if_let_else, - clippy::missing_const_for_fn, - clippy::cognitive_complexity, - clippy::missing_safety_doc, - )] - -extern crate bilge; -extern crate bilge_impl; -extern crate qemu_api; - -pub mod device; -pub mod device_class; -pub mod memory_ops; - -pub const TYPE_PL011: &::core::ffi::CStr =3D c"pl011"; - -/// Offset of each register from the base memory address of the device. -/// -/// # Source -/// ARM DDI 0183G, Table 3-1 p.3-3 -#[doc(alias =3D "offset")] -#[allow(non_camel_case_types)] -#[repr(u64)] -#[derive(Debug)] -pub enum RegisterOffset { - /// Data Register - /// - /// A write to this register initiates the actual data transmission - #[doc(alias =3D "UARTDR")] - DR =3D 0x000, - /// Receive Status Register or Error Clear Register - #[doc(alias =3D "UARTRSR")] - #[doc(alias =3D "UARTECR")] - RSR =3D 0x004, - /// Flag Register - /// - /// A read of this register shows if transmission is complete - #[doc(alias =3D "UARTFR")] - FR =3D 0x018, - /// Fractional Baud Rate Register - /// - /// responsible for baud rate speed - #[doc(alias =3D "UARTFBRD")] - FBRD =3D 0x028, - /// `IrDA` Low-Power Counter Register - #[doc(alias =3D "UARTILPR")] - ILPR =3D 0x020, - /// Integer Baud Rate Register - /// - /// Responsible for baud rate speed - #[doc(alias =3D "UARTIBRD")] - IBRD =3D 0x024, - /// line control register (data frame format) - #[doc(alias =3D "UARTLCR_H")] - LCR_H =3D 0x02C, - /// Toggle UART, transmission or reception - #[doc(alias =3D "UARTCR")] - CR =3D 0x030, - /// Interrupt FIFO Level Select Register - #[doc(alias =3D "UARTIFLS")] - FLS =3D 0x034, - /// Interrupt Mask Set/Clear Register - #[doc(alias =3D "UARTIMSC")] - IMSC =3D 0x038, - /// Raw Interrupt Status Register - #[doc(alias =3D "UARTRIS")] - RIS =3D 0x03C, - /// Masked Interrupt Status Register - #[doc(alias =3D "UARTMIS")] - MIS =3D 0x040, - /// Interrupt Clear Register - #[doc(alias =3D "UARTICR")] - ICR =3D 0x044, - /// DMA control Register - #[doc(alias =3D "UARTDMACR")] - DMACR =3D 0x048, - ///// Reserved, offsets `0x04C` to `0x07C`. - //Reserved =3D 0x04C, -} - -impl core::convert::TryFrom for RegisterOffset { - type Error =3D u64; - - fn try_from(value: u64) -> Result { - macro_rules! case { - ($($discriminant:ident),*$(,)*) =3D> { - /* check that matching on all macro arguments compiles, wh= ich means we are not - * missing any enum value; if the type definition ever cha= nges this will stop - * compiling. - */ - const fn _assert_exhaustive(val: RegisterOffset) { - match val { - $(RegisterOffset::$discriminant =3D> (),)* - } - } - - match value { - $(x if x =3D=3D Self::$discriminant as u64 =3D> Ok(Sel= f::$discriminant),)* - _ =3D> Err(value), - } - } - } - case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, = MIS, ICR, DMACR } - } -} - -pub mod registers { - //! Device registers exposed as typed structs which are backed by arbi= trary - //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. - //! - //! All PL011 registers are essentially 32-bit wide, but are typed her= e as - //! bitmaps with only the necessary width. That is, if a struct bitmap - //! in this module is for example 16 bits long, it should be conceived - //! as a 32-bit register where the unmentioned higher bits are always - //! unused thus treated as zero when read or written. - use bilge::prelude::*; - - // TODO: FIFO Mode has different semantics - /// Data Register, `UARTDR` - /// - /// The `UARTDR` register is the data register. - /// - /// For words to be transmitted: - /// - /// - if the FIFOs are enabled, data written to this location is pushe= d onto - /// the transmit - /// FIFO - /// - if the FIFOs are not enabled, data is stored in the transmitter - /// holding register (the - /// bottom word of the transmit FIFO). - /// - /// The write operation initiates transmission from the UART. The data= is - /// prefixed with a start bit, appended with the appropriate parity bit - /// (if parity is enabled), and a stop bit. The resultant word is then - /// transmitted. - /// - /// For received words: - /// - /// - if the FIFOs are enabled, the data byte and the 4-bit status (br= eak, - /// frame, parity, - /// and overrun) is pushed onto the 12-bit wide receive FIFO - /// - if the FIFOs are not enabled, the data byte and status are store= d in - /// the receiving - /// holding register (the bottom word of the receive FIFO). - /// - /// The received data byte is read by performing reads from the `UARTD= R` - /// register along with the corresponding status information. The stat= us - /// information can also be read by a read of the `UARTRSR/UARTECR` - /// register. - /// - /// # Note - /// - /// You must disable the UART before any of the control registers are - /// reprogrammed. When the UART is disabled in the middle of - /// transmission or reception, it completes the current character befo= re - /// stopping. - /// - /// # Source - /// ARM DDI 0183G 3.3.1 Data Register, UARTDR - #[bitsize(16)] - #[derive(Clone, Copy, DebugBits, FromBits)] - #[doc(alias =3D "UARTDR")] - pub struct Data { - _reserved: u4, - pub data: u8, - pub framing_error: bool, - pub parity_error: bool, - pub break_error: bool, - pub overrun_error: bool, - } - - // TODO: FIFO Mode has different semantics - /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` - /// - /// The UARTRSR/UARTECR register is the receive status register/error = clear - /// register. Receive status can also be read from the `UARTRSR` - /// register. If the status is read from this register, then the status - /// information for break, framing and parity corresponds to the - /// data character read from the [Data register](Data), `UARTDR` prior= to - /// reading the UARTRSR register. The status information for overrun is - /// set immediately when an overrun condition occurs. - /// - /// - /// # Note - /// The received data character must be read first from the [Data - /// Register](Data), `UARTDR` before reading the error status associat= ed - /// with that data character from the `UARTRSR` register. This read - /// sequence cannot be reversed, because the `UARTRSR` register is - /// updated only when a read occurs from the `UARTDR` register. Howeve= r, - /// the status information can also be obtained by reading the `UARTDR` - /// register - /// - /// # Source - /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, - /// UARTRSR/UARTECR - #[bitsize(8)] - #[derive(Clone, Copy, DebugBits, FromBits)] - pub struct ReceiveStatusErrorClear { - pub framing_error: bool, - pub parity_error: bool, - pub break_error: bool, - pub overrun_error: bool, - _reserved_unpredictable: u4, - } - - impl ReceiveStatusErrorClear { - pub fn reset(&mut self) { - // All the bits are cleared to 0 on reset. - *self =3D 0.into(); - } - } - - impl Default for ReceiveStatusErrorClear { - fn default() -> Self { - 0.into() - } - } - - #[bitsize(16)] - #[derive(Clone, Copy, DebugBits, FromBits)] - /// Flag Register, `UARTFR` - #[doc(alias =3D "UARTFR")] - pub struct Flags { - /// CTS Clear to send. This bit is the complement of the UART clea= r to - /// send, `nUARTCTS`, modem status input. That is, the bit is 1 - /// when `nUARTCTS` is LOW. - pub clear_to_send: bool, - /// DSR Data set ready. This bit is the complement of the UART dat= a set - /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 w= hen - /// `nUARTDSR` is LOW. - pub data_set_ready: bool, - /// DCD Data carrier detect. This bit is the complement of the UAR= T data - /// carrier detect, `nUARTDCD`, modem status input. That is, the b= it is - /// 1 when `nUARTDCD` is LOW. - pub data_carrier_detect: bool, - /// BUSY UART busy. If this bit is set to 1, the UART is busy - /// transmitting data. This bit remains set until the complete - /// byte, including all the stop bits, has been sent from the - /// shift register. This bit is set as soon as the transmit FIFO - /// becomes non-empty, regardless of whether the UART is enabled - /// or not. - pub busy: bool, - /// RXFE Receive FIFO empty. The meaning of this bit depends on the - /// state of the FEN bit in the UARTLCR_H register. If the FIFO - /// is disabled, this bit is set when the receive holding - /// register is empty. If the FIFO is enabled, the RXFE bit is - /// set when the receive FIFO is empty. - pub receive_fifo_empty: bool, - /// TXFF Transmit FIFO full. The meaning of this bit depends on the - /// state of the FEN bit in the UARTLCR_H register. If the FIFO - /// is disabled, this bit is set when the transmit holding - /// register is full. If the FIFO is enabled, the TXFF bit is - /// set when the transmit FIFO is full. - pub transmit_fifo_full: bool, - /// RXFF Receive FIFO full. The meaning of this bit depends on the= state - /// of the FEN bit in the UARTLCR_H register. If the FIFO is - /// disabled, this bit is set when the receive holding register - /// is full. If the FIFO is enabled, the RXFF bit is set when - /// the receive FIFO is full. - pub receive_fifo_full: bool, - /// Transmit FIFO empty. The meaning of this bit depends on the st= ate of - /// the FEN bit in the [Line Control register](LineControl), - /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the - /// transmit holding register is empty. If the FIFO is enabled, - /// the TXFE bit is set when the transmit FIFO is empty. This - /// bit does not indicate if there is data in the transmit shift - /// register. - pub transmit_fifo_empty: bool, - /// `RI`, is `true` when `nUARTRI` is `LOW`. - pub ring_indicator: bool, - _reserved_zero_no_modify: u7, - } - - impl Flags { - pub fn reset(&mut self) { - // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a= re 1 - self.set_receive_fifo_full(false); - self.set_transmit_fifo_full(false); - self.set_busy(false); - self.set_receive_fifo_empty(true); - self.set_transmit_fifo_empty(true); - } - } - - impl Default for Flags { - fn default() -> Self { - let mut ret: Self =3D 0.into(); - ret.reset(); - ret - } - } - - #[bitsize(16)] - #[derive(Clone, Copy, DebugBits, FromBits)] - /// Line Control Register, `UARTLCR_H` - #[doc(alias =3D "UARTLCR_H")] - pub struct LineControl { - /// 15:8 - Reserved, do not modify, read as zero. - _reserved_zero_no_modify: u8, - /// 7 SPS Stick parity select. - /// 0 =3D stick parity is disabled - /// 1 =3D either: - /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked - /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is - /// transmitted and checked as a 0. This bit has no effect when - /// the PEN bit disables parity checking and generation. See Table= 3-11 - /// on page 3-14 for the parity truth table. - pub sticky_parity: bool, - /// WLEN Word length. These bits indicate the number of data bits - /// transmitted or received in a frame as follows: b11 =3D 8 bits - /// b10 =3D 7 bits - /// b01 =3D 6 bits - /// b00 =3D 5 bits. - pub word_length: WordLength, - /// FEN Enable FIFOs: - /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome - /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO - /// buffers are enabled (FIFO mode). - pub fifos_enabled: Mode, - /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits - /// are transmitted at the end of the frame. The receive - /// logic does not check for two stop bits being received. - pub two_stops_bits: bool, - /// EPS Even parity select. Controls the type of parity the UART u= ses - /// during transmission and reception: - /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of - /// 1s in the data and parity bits. - /// - 1 =3D even parity. The UART generates or checks for an even = number - /// of 1s in the data and parity bits. - /// This bit has no effect when the `PEN` bit disables parity chec= king - /// and generation. See Table 3-11 on page 3-14 for the parity - /// truth table. - pub parity: Parity, - /// 1 PEN Parity enable: - /// - /// - 0 =3D parity is disabled and no parity bit added to the data= frame - /// - 1 =3D parity checking and generation is enabled. - /// - /// See Table 3-11 on page 3-14 for the parity truth table. - pub parity_enabled: bool, - /// BRK Send break. - /// - /// If this bit is set to `1`, a low-level is continually output o= n the - /// `UARTTXD` output, after completing transmission of the - /// current character. For the proper execution of the break comma= nd, - /// the software must set this bit for at least two complete - /// frames. For normal use, this bit must be cleared to `0`. - pub send_break: bool, - } - - impl LineControl { - pub fn reset(&mut self) { - // All the bits are cleared to 0 when reset. - *self =3D 0.into(); - } - } - - impl Default for LineControl { - fn default() -> Self { - 0.into() - } - } - - #[bitsize(1)] - #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] - /// `EPS` "Even parity select", field of [Line Control - /// register](LineControl). - pub enum Parity { - /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of - /// 1s in the data and parity bits. - Odd =3D 0, - /// - 1 =3D even parity. The UART generates or checks for an even = number - /// of 1s in the data and parity bits. - Even =3D 1, - } - - #[bitsize(1)] - #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] - /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control - /// register](LineControl). - pub enum Mode { - /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome - /// 1-byte-deep holding registers - Character =3D 0, - /// 1 =3D transmit and receive FIFO buffers are enabled (FIFO mode= ). - FIFO =3D 1, - } - - impl From for bool { - fn from(val: Mode) -> Self { - matches!(val, Mode::FIFO) - } - } - - #[bitsize(2)] - #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] - /// `WLEN` Word length, field of [Line Control register](LineControl). - /// - /// These bits indicate the number of data bits transmitted or receive= d in a - /// frame as follows: - pub enum WordLength { - /// b11 =3D 8 bits - _8Bits =3D 0b11, - /// b10 =3D 7 bits - _7Bits =3D 0b10, - /// b01 =3D 6 bits - _6Bits =3D 0b01, - /// b00 =3D 5 bits. - _5Bits =3D 0b00, - } - - /// Control Register, `UARTCR` - /// - /// The `UARTCR` register is the control register. All the bits are cl= eared - /// to `0` on reset except for bits `9` and `8` that are set to `1`. - /// - /// # Source - /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 - #[bitsize(16)] - #[doc(alias =3D "UARTCR")] - #[derive(Clone, Copy, DebugBits, FromBits)] - pub struct Control { - /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is d= isabled - /// in the middle of transmission or reception, it completes the c= urrent - /// character before stopping. 1 =3D the UART is enabled. Data - /// transmission and reception occurs for either UART signals or S= IR - /// signals depending on the setting of the SIREN bit. - pub enable_uart: bool, - /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIRO= UT` - /// remains LOW (no light pulse generated), and signal transitions= on - /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is - /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains= HIGH, - /// in the marking state. Signal transitions on UARTRXD or modem s= tatus - /// inputs have no effect. This bit has no effect if the UARTEN bit - /// disables the UART. - pub enable_sir: bool, - /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA enc= oding - /// mode. If this bit is cleared to 0, low-level bits are transmit= ted as - /// an active high pulse with a width of 3/ 16th of the bit period= . If - /// this bit is set to 1, low-level bits are transmitted with a pu= lse - /// width that is 3 times the period of the IrLPBaud16 input signa= l, - /// regardless of the selected bit rate. Setting this bit uses less - /// power, but might reduce transmission distances. - pub sir_lowpower_irda_mode: u1, - /// Reserved, do not modify, read as zero. - _reserved_zero_no_modify: u4, - /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN b= it is - /// set to 1 and the SIRTEST bit in the Test Control register, UAR= TTCR - /// on page 4-5 is set to 1, then the nSIROUT path is inverted, an= d fed - /// through to the SIRIN path. The SIRTEST bit in the test registe= r must - /// be set to 1 to override the normal half-duplex SIR operation. = This - /// must be the requirement for accessing the test registers during - /// normal operation, and SIRTEST must be cleared to 0 when loopba= ck - /// testing is finished. This feature reduces the amount of extern= al - /// coupling required during system test. If this bit is set to 1,= and - /// the SIRTEST bit is set to 0, the UARTTXD path is fed through t= o the - /// UARTRXD path. In either SIR mode or UART mode, when this bit i= s set, - /// the modem outputs are also fed through to the modem inputs. Th= is bit - /// is cleared to 0 on reset, to disable loopback. - pub enable_loopback: bool, - /// `TXE` Transmit enable. If this bit is set to 1, the transmit s= ection - /// of the UART is enabled. Data transmission occurs for either UA= RT - /// signals, or SIR signals depending on the setting of the SIREN = bit. - /// When the UART is disabled in the middle of transmission, it - /// completes the current character before stopping. - pub enable_transmit: bool, - /// `RXE` Receive enable. If this bit is set to 1, the receive sec= tion - /// of the UART is enabled. Data reception occurs for either UART - /// signals or SIR signals depending on the setting of the SIREN b= it. - /// When the UART is disabled in the middle of reception, it compl= etes - /// the current character before stopping. - pub enable_receive: bool, - /// `DTR` Data transmit ready. This bit is the complement of the U= ART - /// data transmit ready, `nUARTDTR`, modem status output. That is,= when - /// the bit is programmed to a 1 then `nUARTDTR` is LOW. - pub data_transmit_ready: bool, - /// `RTS` Request to send. This bit is the complement of the UART - /// request to send, `nUARTRTS`, modem status output. That is, whe= n the - /// bit is programmed to a 1 then `nUARTRTS` is LOW. - pub request_to_send: bool, - /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1= `) - /// modem status output. That is, when the bit is programmed to a = 1 the - /// output is 0. For DTE this can be used as Data Carrier Detect (= DCD). - pub out_1: bool, - /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2= `) - /// modem status output. That is, when the bit is programmed to a = 1, the - /// output is 0. For DTE this can be used as Ring Indicator (RI). - pub out_2: bool, - /// `RTSEn` RTS hardware flow control enable. If this bit is set t= o 1, - /// RTS hardware flow control is enabled. Data is only requested w= hen - /// there is space in the receive FIFO for it to be received. - pub rts_hardware_flow_control_enable: bool, - /// `CTSEn` CTS hardware flow control enable. If this bit is set t= o 1, - /// CTS hardware flow control is enabled. Data is only transmitted= when - /// the `nUARTCTS` signal is asserted. - pub cts_hardware_flow_control_enable: bool, - } - - impl Control { - pub fn reset(&mut self) { - *self =3D 0.into(); - self.set_enable_receive(true); - self.set_enable_transmit(true); - } - } - - impl Default for Control { - fn default() -> Self { - let mut ret: Self =3D 0.into(); - ret.reset(); - ret - } - } - - /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC - pub const INT_OE: u32 =3D 1 << 10; - pub const INT_BE: u32 =3D 1 << 9; - pub const INT_PE: u32 =3D 1 << 8; - pub const INT_FE: u32 =3D 1 << 7; - pub const INT_RT: u32 =3D 1 << 6; - pub const INT_TX: u32 =3D 1 << 5; - pub const INT_RX: u32 =3D 1 << 4; - pub const INT_DSR: u32 =3D 1 << 3; - pub const INT_DCD: u32 =3D 1 << 2; - pub const INT_CTS: u32 =3D 1 << 1; - pub const INT_RI: u32 =3D 1 << 0; - pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; - pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; - - #[repr(u32)] - pub enum Interrupt { - OE =3D 1 << 10, - BE =3D 1 << 9, - PE =3D 1 << 8, - FE =3D 1 << 7, - RT =3D 1 << 6, - TX =3D 1 << 5, - RX =3D 1 << 4, - DSR =3D 1 << 3, - DCD =3D 1 << 2, - CTS =3D 1 << 1, - RI =3D 1 << 0, - } - - impl Interrupt { - pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; - pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; - } -} - -// TODO: You must disable the UART before any of the control registers are -// reprogrammed. When the UART is disabled in the middle of transmission or -// reception, it completes the current character before stopping diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/= memory_ops.rs deleted file mode 100644 index 8d066ebf6d016fa30db004933751a854d7e59117..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/src/memory_ops.rs +++ /dev/null @@ -1,59 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -use core::{mem::MaybeUninit, ptr::NonNull}; - -use qemu_api::bindings::*; - -use crate::device::PL011State; - -pub static PL011_OPS: MemoryRegionOps =3D MemoryRegionOps { - read: Some(pl011_read), - write: Some(pl011_write), - read_with_attrs: None, - write_with_attrs: None, - endianness: device_endian::DEVICE_NATIVE_ENDIAN, - valid: unsafe { MaybeUninit::::zeroed()= .assume_init() }, - impl_: MemoryRegionOps__bindgen_ty_2 { - min_access_size: 4, - max_access_size: 4, - ..unsafe { MaybeUninit::::zeroed().= assume_init() } - }, -}; - -#[no_mangle] -unsafe extern "C" fn pl011_read( - opaque: *mut core::ffi::c_void, - addr: hwaddr, - size: core::ffi::c_uint, -) -> u64 { - assert!(!opaque.is_null()); - let mut state =3D unsafe { NonNull::new_unchecked(opaque.cast::()) }; - let val =3D unsafe { state.as_mut().read(addr, size) }; - match val { - std::ops::ControlFlow::Break(val) =3D> val, - std::ops::ControlFlow::Continue(val) =3D> { - // SAFETY: self.char_backend is a valid CharBackend instance a= fter it's been - // initialized in realize(). - let cb_ptr =3D unsafe { core::ptr::addr_of_mut!(state.as_mut()= .char_backend) }; - unsafe { qemu_chr_fe_accept_input(cb_ptr) }; - - val - } - } -} - -#[no_mangle] -unsafe extern "C" fn pl011_write( - opaque: *mut core::ffi::c_void, - addr: hwaddr, - data: u64, - _size: core::ffi::c_uint, -) { - unsafe { - assert!(!opaque.is_null()); - let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); - state.as_mut().write(addr, data) - } -} diff --git a/rust/hw/meson.build b/rust/hw/meson.build deleted file mode 100644 index 860196645e719624d2e2e6bc301b62b81ab2e19b..000000000000000000000000000= 0000000000000 --- a/rust/hw/meson.build +++ /dev/null @@ -1 +0,0 @@ -subdir('char') diff --git a/rust/meson.build b/rust/meson.build index def77389cddc52f5d4503840e9bdfb1207586fa2..7a32b1b195083571931ad589965= c10ddaf6383b1 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -1,4 +1,2 @@ subdir('qemu-api-macros') subdir('qemu-api') - -subdir('hw') diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh index 30677c3ec9032ea01090f74602d839d1c571d012..62a2cf45d28ed5565076443b9f9= 31a647d395542 100755 --- a/scripts/archive-source.sh +++ b/scripts/archive-source.sh @@ -27,9 +27,7 @@ sub_file=3D"${sub_tdir}/submodule.tar" # in their checkout, because the build environment is completely # different to the host OS. subprojects=3D"keycodemapdb libvfio-user berkeley-softfloat-3 - berkeley-testfloat-3 arbitrary-int-1-rs bilge-0.2-rs - bilge-impl-0.2-rs either-1-rs itertools-0.11-rs proc-macro2-1-rs - proc-macro-error-1-rs proc-macro-error-attr-1-rs quote-1-rs + berkeley-testfloat-3 proc-macro2-1-rs quote-1-rs syn-2-rs unicode-ident-1-rs" sub_deinit=3D"" =20 diff --git a/scripts/make-release b/scripts/make-release index 8dc939124c4fd4abf3509c3b64c0588bc8810962..cf7d694ef73ba1c6c5afad5d211= a42f6a6fe1577 100755 --- a/scripts/make-release +++ b/scripts/make-release @@ -18,9 +18,7 @@ fi =20 # Only include wraps that are invoked with subproject() SUBPROJECTS=3D"libvfio-user keycodemapdb berkeley-softfloat-3 - berkeley-testfloat-3 arbitrary-int-1-rs bilge-0.2-rs - bilge-impl-0.2-rs either-1-rs itertools-0.11-rs proc-macro2-1-rs - proc-macro-error-1-rs proc-macro-error-attr-1-rs quote-1-rs + berkeley-testfloat-3 proc-macro2-1-rs quote-1-rs syn-2-rs unicode-ident-1-rs" =20 src=3D"$1" diff --git a/scripts/rust/rust_root_crate.sh b/scripts/rust/rust_root_crate= .sh deleted file mode 100755 index 975bddf7f1a4c6ca7770f800bdc894cdff1f3ab1..000000000000000000000000000= 0000000000000 --- a/scripts/rust/rust_root_crate.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -set -eu - -cat < (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778707012498.2805729750172; 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778708315116600 This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=3Daarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device Co-authored-by: Junjie Mao Co-authored-by: Paolo Bonzini Signed-off-by: Junjie Mao Signed-off-by: Paolo Bonzini Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 + meson.build | 24 + hw/arm/Kconfig | 30 +- rust/Kconfig | 1 + rust/hw/Kconfig | 2 + rust/hw/char/Kconfig | 3 + rust/hw/char/meson.build | 1 + rust/hw/char/pl011/.gitignore | 2 + rust/hw/char/pl011/Cargo.lock | 134 +++++ rust/hw/char/pl011/Cargo.toml | 26 + rust/hw/char/pl011/README.md | 31 ++ rust/hw/char/pl011/meson.build | 26 + rust/hw/char/pl011/src/device.rs | 599 +++++++++++++++++= ++++ rust/hw/char/pl011/src/device_class.rs | 70 +++ rust/hw/char/pl011/src/lib.rs | 586 +++++++++++++++++= +++ rust/hw/char/pl011/src/memory_ops.rs | 59 ++ rust/hw/meson.build | 1 + rust/meson.build | 2 + scripts/archive-source.sh | 4 +- scripts/make-release | 4 +- scripts/rust/rust_root_crate.sh | 13 + subprojects/.gitignore | 7 + subprojects/arbitrary-int-1-rs.wrap | 7 + subprojects/bilge-0.2-rs.wrap | 7 + subprojects/bilge-impl-0.2-rs.wrap | 7 + subprojects/either-1-rs.wrap | 7 + subprojects/itertools-0.11-rs.wrap | 7 + .../packagefiles/arbitrary-int-1-rs/meson.build | 19 + subprojects/packagefiles/bilge-0.2-rs/meson.build | 29 + .../packagefiles/bilge-impl-0.2-rs/meson.build | 45 ++ subprojects/packagefiles/either-1-rs/meson.build | 24 + .../packagefiles/itertools-0.11-rs/meson.build | 30 ++ .../packagefiles/proc-macro-error-1-rs/meson.build | 40 ++ .../proc-macro-error-attr-1-rs/meson.build | 32 ++ .../packagefiles/unicode-ident-1-rs/meson.build | 20 + subprojects/proc-macro-error-1-rs.wrap | 7 + subprojects/proc-macro-error-attr-1-rs.wrap | 7 + 37 files changed, 1906 insertions(+), 12 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 793c683aa6cccafca9c98b74b9a20d84211f041b..c3bfa132fd6ecd61dd733b760a5= e1ccd39613455 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1137,6 +1137,11 @@ F: include/hw/*/microbit*.h F: tests/qtest/microbit-test.c F: docs/system/arm/nrf.rst =20 +ARM PL011 Rust device +M: Manos Pitsidianakis +S: Maintained +F: rust/hw/char/pl011/ + AVR Machines ------------- =20 diff --git a/meson.build b/meson.build index 0d617c551e61c90c7c357c62ff5da34437723947..c26c417de16ad9256a019a90fd8= 9ea990bb3f948 100644 --- a/meson.build +++ b/meson.build @@ -3520,6 +3520,7 @@ qom_ss =3D ss.source_set() system_ss =3D ss.source_set() specific_fuzz_ss =3D ss.source_set() specific_ss =3D ss.source_set() +rust_devices_ss =3D ss.source_set() stub_ss =3D ss.source_set() trace_ss =3D ss.source_set() user_ss =3D ss.source_set() @@ -4067,6 +4068,29 @@ foreach target : target_dirs arch_srcs +=3D target_specific.sources() arch_deps +=3D target_specific.dependencies() =20 + if have_rust and have_system + target_rust =3D rust_devices_ss.apply(config_target, strict: false) + crates =3D [] + foreach dep : target_rust.dependencies() + crates +=3D dep.get_variable('crate') + endforeach + if crates.length() > 0 + rlib_rs =3D custom_target('rust_' + target.underscorify() + '.rs', + output: 'rust_' + target.underscorify() + '.= rs', + command: [find_program('scripts/rust/rust_ro= ot_crate.sh')] + crates, + capture: true, + build_by_default: true, + build_always_stale: true) + rlib =3D static_library('rust_' + target.underscorify(), + rlib_rs, + dependencies: target_rust.dependencies(), + override_options: ['rust_std=3D2021', 'build.r= ust_std=3D2021'], + rust_args: rustc_args, + rust_abi: 'c') + arch_deps +=3D declare_dependency(link_whole: [rlib]) + endif + endif + # allow using headers from the dependencies but do not include the sourc= es, # because this emulator only needs those in "objects". For external # dependencies, the full dependency is included below in the executable. diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 53eb7bb3d0157bb6e8e078fe73ec66015ae0fe13..e7fd9338d11dadb7a18032c6749= 27db3d9887bdd 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -20,7 +20,8 @@ config ARM_VIRT select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL061 # GPIO select GPIO_PWR @@ -73,7 +74,8 @@ config HIGHBANK select AHCI select ARM_TIMER # sp804 select ARM_V7M - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL022 # SPI select PL031 # RTC select PL061 # GPIO @@ -86,7 +88,8 @@ config INTEGRATOR depends on TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL041 # audio select PL050 # keyboard/mouse @@ -104,7 +107,8 @@ config MUSCA default y depends on TCG && ARM select ARMSSE - select PL011 + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 select SPLIT_IRQ select UNIMP @@ -168,7 +172,8 @@ config REALVIEW select WM8750 # audio codec select LSI_SCSI_PCI select PCI - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL041 # audio codec select PL050 # keyboard/mouse @@ -193,7 +198,8 @@ config SBSA_REF select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL061 # GPIO select USB_XHCI_SYSBUS @@ -217,7 +223,8 @@ config STELLARIS select ARM_V7M select CMSDK_APB_WATCHDOG select I2C - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL022 # SPI select PL061 # GPIO select SSD0303 # OLED display @@ -277,7 +284,8 @@ config VEXPRESS select ARM_TIMER # sp804 select LAN9118 select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL041 # audio codec select PL181 # display select REALVIEW @@ -362,7 +370,8 @@ config RASPI default y depends on TCG && ARM select FRAMEBUFFER - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select SDHCI select USB_DWC2 select BCM2835_SPI @@ -438,7 +447,8 @@ config XLNX_VERSAL select ARM_GIC select CPU_CLUSTER select DEVICE_TREE - select PL011 + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select CADENCE select VIRTIO_MMIO select UNIMP diff --git a/rust/Kconfig b/rust/Kconfig index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..f9f5c3909887451f71360a7986d= 79e57fdb43c91 100644 --- a/rust/Kconfig +++ b/rust/Kconfig @@ -0,0 +1 @@ +source hw/Kconfig diff --git a/rust/hw/Kconfig b/rust/hw/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..4d934f30afe13ddff418db8ec9e= 8b8eb25a9e8d0 --- /dev/null +++ b/rust/hw/Kconfig @@ -0,0 +1,2 @@ +# devices Kconfig +source char/Kconfig diff --git a/rust/hw/char/Kconfig b/rust/hw/char/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..a1732a9e97fe3211547e30bc931= 9382e6394ed5b --- /dev/null +++ b/rust/hw/char/Kconfig @@ -0,0 +1,3 @@ +config X_PL011_RUST + bool + default y if HAVE_RUST diff --git a/rust/hw/char/meson.build b/rust/hw/char/meson.build new file mode 100644 index 0000000000000000000000000000000000000000..5716dc43ef6facdcf1cc9631083= 47bbf4d12cf0e --- /dev/null +++ b/rust/hw/char/meson.build @@ -0,0 +1 @@ +subdir('pl011') diff --git a/rust/hw/char/pl011/.gitignore b/rust/hw/char/pl011/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..71eaff2035d5a65b57ae32dfeec= f3d87bbc7b396 --- /dev/null +++ b/rust/hw/char/pl011/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/hw/char/pl011/Cargo.lock b/rust/hw/char/pl011/Cargo.lock new file mode 100644 index 0000000000000000000000000000000000000000..b58cebb186e99efe184117bb931= a341543d4466b --- /dev/null +++ b/rust/hw/char/pl011/Cargo.lock @@ -0,0 +1,134 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "arbitrary-int" +version =3D "1.2.7" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b1d= f46d" + +[[package]] +name =3D "bilge" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512e6= 7b57" +dependencies =3D [ + "arbitrary-int", + "bilge-impl", +] + +[[package]] +name =3D "bilge-impl" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "feb11e002038ad243af39c2068c8a72bcf147acf05025dcdb916fcc000ad= b2d8" +dependencies =3D [ + "itertools", + "proc-macro-error", + "proc-macro2", + "quote", + "syn", +] + +[[package]] +name =3D "either" +version =3D "1.12.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3dca9240753cf90908d7e4aac30f630662b02aebaa1b58a3cadabdb23385= b58b" + +[[package]] +name =3D "itertools" +version =3D "0.11.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "b1c173a5686ce8bfa551b3563d0c2170bf24ca44da99c7ca4bfdab5418c3= fe57" +dependencies =3D [ + "either", +] + +[[package]] +name =3D "pl011" +version =3D "0.1.0" +dependencies =3D [ + "bilge", + "bilge-impl", + "qemu_api", + "qemu_api_macros", +] + +[[package]] +name =3D "proc-macro-error" +version =3D "1.0.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5c= e38c" +dependencies =3D [ + "proc-macro-error-attr", + "proc-macro2", + "quote", + "version_check", +] + +[[package]] +name =3D "proc-macro-error-attr" +version =3D "1.0.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35= f869" +dependencies =3D [ + "proc-macro2", + "quote", + "version_check", +] + +[[package]] +name =3D "proc-macro2" +version =3D "1.0.84" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "ec96c6a92621310b51366f1e28d05ef11489516e93be030060e5fc12024a= 49d6" +dependencies =3D [ + "unicode-ident", +] + +[[package]] +name =3D "qemu_api" +version =3D "0.1.0" + +[[package]] +name =3D "qemu_api_macros" +version =3D "0.1.0" +dependencies =3D [ + "proc-macro2", + "quote", + "syn", +] + +[[package]] +name =3D "quote" +version =3D "1.0.36" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208ac= aca7" +dependencies =3D [ + "proc-macro2", +] + +[[package]] +name =3D "syn" +version =3D "2.0.66" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cd= cff5" +dependencies =3D [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name =3D "unicode-ident" +version =3D "1.0.12" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" + +[[package]] +name =3D "version_check" +version =3D "0.9.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e= 483f" diff --git a/rust/hw/char/pl011/Cargo.toml b/rust/hw/char/pl011/Cargo.toml new file mode 100644 index 0000000000000000000000000000000000000000..b089e3dded623131ee13b4af814= 5b84388755df7 --- /dev/null +++ b/rust/hw/char/pl011/Cargo.toml @@ -0,0 +1,26 @@ +[package] +name =3D "pl011" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "pl011 device model for QEMU" +repository =3D "https://gitlab.com/epilys/rust-for-qemu" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[lib] +crate-type =3D ["staticlib"] + +[dependencies] +bilge =3D { version =3D "0.2.0" } +bilge-impl =3D { version =3D "0.2.0" } +qemu_api =3D { path =3D "../../../qemu-api" } +qemu_api_macros =3D { path =3D "../../../qemu-api-macros" } + +# Do not include in any global workspace +[workspace] diff --git a/rust/hw/char/pl011/README.md b/rust/hw/char/pl011/README.md new file mode 100644 index 0000000000000000000000000000000000000000..cd7dea31634241cbf96b0be13f2= 1d52bbd8ae750 --- /dev/null +++ b/rust/hw/char/pl011/README.md @@ -0,0 +1,31 @@ +# PL011 QEMU Device Model + +This library implements a device model for the PrimeCell=C2=AE UART (PL011) +device in QEMU. + +## Build static lib + +Host build target must be explicitly specified: + +```sh +cargo build --target x86_64-unknown-linux-gnu +``` + +Replace host target triplet if necessary. + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items --target x86_64-unknown-linux= -gnu +``` + +To include direct dependencies like `bilge` (bitmaps for register types): + +```sh +cargo tree --depth 1 -e normal --prefix none \ + | cut -d' ' -f1 \ + | xargs printf -- '-p %s\n' \ + | xargs cargo doc --no-deps --document-private-items --target x86_64-unkn= own-linux-gnu +``` diff --git a/rust/hw/char/pl011/meson.build b/rust/hw/char/pl011/meson.build new file mode 100644 index 0000000000000000000000000000000000000000..547cca5a96f7eef284caf194938= 0b65f7d015d92 --- /dev/null +++ b/rust/hw/char/pl011/meson.build @@ -0,0 +1,26 @@ +subproject('bilge-0.2-rs', required: true) +subproject('bilge-impl-0.2-rs', required: true) + +bilge_dep =3D dependency('bilge-0.2-rs') +bilge_impl_dep =3D dependency('bilge-impl-0.2-rs') + +_libpl011_rs =3D static_library( + 'pl011', + files('src/lib.rs'), + override_options: ['rust_std=3D2021', 'build.rust_std=3D2021'], + rust_abi: 'rust', + dependencies: [ + bilge_dep, + bilge_impl_dep, + qemu_api, + qemu_api_macros, + ], +) + +rust_devices_ss.add(when: 'CONFIG_X_PL011_RUST', if_true: [declare_depende= ncy( + link_whole: [_libpl011_rs], + # Putting proc macro crates in `dependencies` is necessary for Meson to = find + # them when compiling the root per-target static rust lib. + dependencies: [bilge_impl_dep, qemu_api_macros], + variables: {'crate': 'pl011'}, +)]) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs new file mode 100644 index 0000000000000000000000000000000000000000..c7193b41beec0b177dbc75ac0e4= 3fcfea4c82bfb --- /dev/null +++ b/rust/hw/char/pl011/src/device.rs @@ -0,0 +1,599 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::{ + ffi::{c_int, c_uchar, c_uint, c_void, CStr}, + ptr::{addr_of, addr_of_mut, NonNull}, +}; + +use qemu_api::{ + bindings::{self, *}, + definitions::ObjectImpl, +}; + +use crate::{ + memory_ops::PL011_OPS, + registers::{self, Interrupt}, + RegisterOffset, +}; + +static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; + +const DATA_BREAK: u32 =3D 1 << 10; + +/// QEMU sourced constant. +pub const PL011_FIFO_DEPTH: usize =3D 16_usize; + +#[repr(C)] +#[derive(Debug, qemu_api_macros::Object)] +/// PL011 Device Model in QEMU +pub struct PL011State { + pub parent_obj: SysBusDevice, + pub iomem: MemoryRegion, + #[doc(alias =3D "fr")] + pub flags: registers::Flags, + #[doc(alias =3D "lcr")] + pub line_control: registers::LineControl, + #[doc(alias =3D "rsr")] + pub receive_status_error_clear: registers::ReceiveStatusErrorClear, + #[doc(alias =3D "cr")] + pub control: registers::Control, + pub dmacr: u32, + pub int_enabled: u32, + pub int_level: u32, + pub read_fifo: [u32; PL011_FIFO_DEPTH], + pub ilpr: u32, + pub ibrd: u32, + pub fbrd: u32, + pub ifl: u32, + pub read_pos: usize, + pub read_count: usize, + pub read_trigger: usize, + #[doc(alias =3D "chr")] + pub char_backend: CharBackend, + /// QEMU interrupts + /// + /// ```text + /// * sysbus MMIO region 0: device registers + /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) + /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) + /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) + /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) + /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) + /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) + /// ``` + #[doc(alias =3D "irq")] + pub interrupts: [qemu_irq; 6usize], + #[doc(alias =3D "clk")] + pub clock: NonNull, + #[doc(alias =3D "migrate_clk")] + pub migrate_clock: bool, +} + +impl ObjectImpl for PL011State { + type Class =3D PL011Class; + const TYPE_INFO: qemu_api::bindings::TypeInfo =3D qemu_api::type_info!= { Self }; + const TYPE_NAME: &'static CStr =3D crate::TYPE_PL011; + const PARENT_TYPE_NAME: Option<&'static CStr> =3D Some(TYPE_SYS_BUS_DE= VICE); + const ABSTRACT: bool =3D false; + const INSTANCE_INIT: Option = =3D Some(pl011_init); + const INSTANCE_POST_INIT: Option =3D None; + const INSTANCE_FINALIZE: Option =3D None; +} + +#[repr(C)] +pub struct PL011Class { + _inner: [u8; 0], +} + +impl qemu_api::definitions::Class for PL011Class { + const CLASS_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), + > =3D Some(crate::device_class::pl011_class_init); + const CLASS_BASE_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), + > =3D None; +} + +#[used] +pub static CLK_NAME: &CStr =3D c"clk"; + +impl PL011State { + /// Initializes a pre-allocated, unitialized instance of `PL011State`. + /// + /// # Safety + /// + /// `self` must point to a correctly sized and aligned location for the + /// `PL011State` type. It must not be called more than once on the same + /// location/instance. All its fields are expected to hold unitialized + /// values with the sole exception of `parent_obj`. + pub unsafe fn init(&mut self) { + let dev =3D addr_of_mut!(*self).cast::(); + // SAFETY: + // + // self and self.iomem are guaranteed to be valid at this point si= nce callers + // must make sure the `self` reference is valid. + unsafe { + memory_region_init_io( + addr_of_mut!(self.iomem), + addr_of_mut!(*self).cast::(), + &PL011_OPS, + addr_of_mut!(*self).cast::(), + Self::TYPE_INFO.name, + 0x1000, + ); + let sbd =3D addr_of_mut!(*self).cast::(); + sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); + for irq in self.interrupts.iter_mut() { + sysbus_init_irq(sbd, irq); + } + } + // SAFETY: + // + // self.clock is not initialized at this point; but since `NonNull= <_>` is Copy, + // we can overwrite the undefined value without side effects. This= is + // safe since all PL011State instances are created by QOM code whi= ch + // calls this function to initialize the fields; therefore no code= is + // able to access an invalid self.clock value. + unsafe { + self.clock =3D NonNull::new(qdev_init_clock_in( + dev, + CLK_NAME.as_ptr(), + None, /* pl011_clock_update */ + addr_of_mut!(*self).cast::(), + ClockEvent::ClockUpdate.0, + )) + .unwrap(); + } + } + + pub fn read( + &mut self, + offset: hwaddr, + _size: core::ffi::c_uint, + ) -> std::ops::ControlFlow { + use RegisterOffset::*; + + std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset= ) { + Err(v) if (0x3f8..0x400).contains(&v) =3D> { + u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) + } + Err(_) =3D> { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + 0 + } + Ok(DR) =3D> { + // s->flags &=3D ~PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(false); + let c =3D self.read_fifo[self.read_pos]; + if self.read_count > 0 { + self.read_count -=3D 1; + self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); + } + if self.read_count =3D=3D 0 { + // self.flags |=3D PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(true); + } + if self.read_count + 1 =3D=3D self.read_trigger { + //self.int_level &=3D ~ INT_RX; + self.int_level &=3D !registers::INT_RX; + } + // Update error bits. + self.receive_status_error_clear =3D c.to_be_bytes()[3].int= o(); + self.update(); + // Must call qemu_chr_fe_accept_input, so return Continue: + return std::ops::ControlFlow::Continue(c.into()); + } + Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(), + Ok(FR) =3D> u16::from(self.flags).into(), + Ok(FBRD) =3D> self.fbrd.into(), + Ok(ILPR) =3D> self.ilpr.into(), + Ok(IBRD) =3D> self.ibrd.into(), + Ok(LCR_H) =3D> u16::from(self.line_control).into(), + Ok(CR) =3D> { + // We exercise our self-control. + u16::from(self.control).into() + } + Ok(FLS) =3D> self.ifl.into(), + Ok(IMSC) =3D> self.int_enabled.into(), + Ok(RIS) =3D> self.int_level.into(), + Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), + Ok(ICR) =3D> { + // "The UARTICR Register is the interrupt clear register a= nd is write-only" + // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR + 0 + } + Ok(DMACR) =3D> self.dmacr.into(), + }) + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + // eprintln!("write offset {offset} value {value}"); + use RegisterOffset::*; + let value: u32 =3D value as u32; + match RegisterOffset::try_from(offset) { + Err(_bad_offset) =3D> { + eprintln!("write bad offset {offset} value {value}"); + } + Ok(DR) =3D> { + // ??? Check if transmitter is enabled. + let ch: u8 =3D value as u8; + // XXX this blocks entire thread. Rewrite to use + // qemu_chr_fe_write and background I/O callbacks + + // SAFETY: self.char_backend is a valid CharBackend instan= ce after it's been + // initialized in realize(). + unsafe { + qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),= &ch, 1); + } + self.loopback_tx(value); + self.int_level |=3D registers::INT_TX; + self.update(); + } + Ok(RSR) =3D> { + self.receive_status_error_clear =3D 0.into(); + } + Ok(FR) =3D> { + // flag writes are ignored + } + Ok(ILPR) =3D> { + self.ilpr =3D value; + } + Ok(IBRD) =3D> { + self.ibrd =3D value; + } + Ok(FBRD) =3D> { + self.fbrd =3D value; + } + Ok(LCR_H) =3D> { + let value =3D value as u16; + let new_val: registers::LineControl =3D value.into(); + // Reset the FIFO state on FIFO enable or disable + if bool::from(self.line_control.fifos_enabled()) + ^ bool::from(new_val.fifos_enabled()) + { + self.reset_fifo(); + } + if self.line_control.send_break() ^ new_val.send_break() { + let mut break_enable: c_int =3D new_val.send_break().i= nto(); + // SAFETY: self.char_backend is a valid CharBackend in= stance after it's been + // initialized in realize(). + unsafe { + qemu_chr_fe_ioctl( + addr_of_mut!(self.char_backend), + CHR_IOCTL_SERIAL_SET_BREAK as i32, + addr_of_mut!(break_enable).cast::(), + ); + } + self.loopback_break(break_enable > 0); + } + self.line_control =3D new_val; + self.set_read_trigger(); + } + Ok(CR) =3D> { + // ??? Need to implement the enable bit. + let value =3D value as u16; + self.control =3D value.into(); + self.loopback_mdmctrl(); + } + Ok(FLS) =3D> { + self.ifl =3D value; + self.set_read_trigger(); + } + Ok(IMSC) =3D> { + self.int_enabled =3D value; + self.update(); + } + Ok(RIS) =3D> {} + Ok(MIS) =3D> {} + Ok(ICR) =3D> { + self.int_level &=3D !value; + self.update(); + } + Ok(DMACR) =3D> { + self.dmacr =3D value; + if value & 3 > 0 { + // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); + eprintln!("pl011: DMA not implemented"); + } + } + } + } + + #[inline] + fn loopback_tx(&mut self, value: u32) { + if !self.loopback_enabled() { + return; + } + + // Caveat: + // + // In real hardware, TX loopback happens at the serial-bit level + // and then reassembled by the RX logics back into bytes and placed + // into the RX fifo. That is, loopback happens after TX fifo. + // + // Because the real hardware TX fifo is time-drained at the frame + // rate governed by the configured serial format, some loopback + // bytes in TX fifo may still be able to get into the RX fifo + // that could be full at times while being drained at software + // pace. + // + // In such scenario, the RX draining pace is the major factor + // deciding which loopback bytes get into the RX fifo, unless + // hardware flow-control is enabled. + // + // For simplicity, the above described is not emulated. + self.put_fifo(value); + } + + fn loopback_mdmctrl(&mut self) { + if !self.loopback_enabled() { + return; + } + + /* + * Loopback software-driven modem control outputs to modem status = inputs: + * FR.RI <=3D CR.Out2 + * FR.DCD <=3D CR.Out1 + * FR.CTS <=3D CR.RTS + * FR.DSR <=3D CR.DTR + * + * The loopback happens immediately even if this call is triggered + * by setting only CR.LBE. + * + * CTS/RTS updates due to enabled hardware flow controls are not + * dealt with here. + */ + + //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | + // PL011_FLAG_DSR | PL011_FLAG_CTS); + //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; + //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; + //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; + //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; + // + self.flags.set_ring_indicator(self.control.out_2()); + self.flags.set_data_carrier_detect(self.control.out_1()); + self.flags.set_clear_to_send(self.control.request_to_send()); + self.flags + .set_data_set_ready(self.control.data_transmit_ready()); + + // Change interrupts based on updated FR + let mut il =3D self.int_level; + + il &=3D !Interrupt::MS; + //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; + //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; + //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; + //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; + + if self.flags.data_set_ready() { + il |=3D Interrupt::DSR as u32; + } + if self.flags.data_carrier_detect() { + il |=3D Interrupt::DCD as u32; + } + if self.flags.clear_to_send() { + il |=3D Interrupt::CTS as u32; + } + if self.flags.ring_indicator() { + il |=3D Interrupt::RI as u32; + } + self.int_level =3D il; + self.update(); + } + + fn loopback_break(&mut self, enable: bool) { + if enable { + self.loopback_tx(DATA_BREAK); + } + } + + fn set_read_trigger(&mut self) { + self.read_trigger =3D 1; + } + + pub fn realize(&mut self) { + // SAFETY: self.char_backend has the correct size and alignment fo= r a + // CharBackend object, and its callbacks are of the correct types. + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + pub fn reset(&mut self) { + self.line_control.reset(); + self.receive_status_error_clear.reset(); + self.dmacr =3D 0; + self.int_enabled =3D 0; + self.int_level =3D 0; + self.ilpr =3D 0; + self.ibrd =3D 0; + self.fbrd =3D 0; + self.read_trigger =3D 1; + self.ifl =3D 0x12; + self.control.reset(); + self.flags =3D 0.into(); + self.reset_fifo(); + } + + pub fn reset_fifo(&mut self) { + self.read_count =3D 0; + self.read_pos =3D 0; + + /* Reset FIFO flags */ + self.flags.reset(); + } + + pub fn can_receive(&self) -> bool { + // trace_pl011_can_receive(s->lcr, s->read_count, r); + self.read_count < self.fifo_depth() + } + + pub fn event(&mut self, event: QEMUChrEvent) { + if event =3D=3D bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.f= ifo_enabled() { + self.put_fifo(DATA_BREAK); + self.receive_status_error_clear.set_break_error(true); + } + } + + #[inline] + pub fn fifo_enabled(&self) -> bool { + matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) + } + + #[inline] + pub fn loopback_enabled(&self) -> bool { + self.control.enable_loopback() + } + + #[inline] + pub fn fifo_depth(&self) -> usize { + // Note: FIFO depth is expected to be power-of-2 + if self.fifo_enabled() { + return PL011_FIFO_DEPTH; + } + 1 + } + + pub fn put_fifo(&mut self, value: c_uint) { + let depth =3D self.fifo_depth(); + assert!(depth > 0); + let slot =3D (self.read_pos + self.read_count) & (depth - 1); + self.read_fifo[slot] =3D value; + self.read_count +=3D 1; + // s->flags &=3D ~PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(false); + if self.read_count =3D=3D depth { + //s->flags |=3D PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(true); + } + + if self.read_count =3D=3D self.read_trigger { + self.int_level |=3D registers::INT_RX; + self.update(); + } + } + + pub fn update(&self) { + let flags =3D self.int_level & self.int_enabled; + for (irq, i) in self.interrupts.iter().zip(IRQMASK) { + // SAFETY: self.interrupts have been initialized in init(). + unsafe { qemu_set_irq(*irq, i32::from(flags & i !=3D 0)) }; + } + } +} + +/// Which bits in the interrupt status matter for each outbound IRQ line ? +pub const IRQMASK: [u32; 6] =3D [ + /* combined IRQ */ + Interrupt::E + | Interrupt::MS + | Interrupt::RT as u32 + | Interrupt::TX as u32 + | Interrupt::RX as u32, + Interrupt::RX as u32, + Interrupt::TX as u32, + Interrupt::RT as u32, + Interrupt::MS, + Interrupt::E, +]; + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { + unsafe { + debug_assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().can_receive().into() + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +/// +/// The buffer and size arguments must also be valid. +#[no_mangle] +pub unsafe extern "C" fn pl011_receive( + opaque: *mut core::ffi::c_void, + buf: *const u8, + size: core::ffi::c_int, +) { + unsafe { + debug_assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); + if state.as_ref().loopback_enabled() { + return; + } + if size > 0 { + debug_assert!(!buf.is_null()); + state.as_mut().put_fifo(c_uint::from(buf.read_volatile())) + } + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { + unsafe { + debug_assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); + state.as_mut().event(event) + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer for `c= hr`. +#[no_mangle] +pub unsafe extern "C" fn pl011_create( + addr: u64, + irq: qemu_irq, + chr: *mut Chardev, +) -> *mut DeviceState { + unsafe { + let dev: *mut DeviceState =3D qdev_new(PL011State::TYPE_INFO.name); + let sysbus: *mut SysBusDevice =3D dev.cast::(); + + qdev_prop_set_chr(dev, bindings::TYPE_CHARDEV.as_ptr(), chr); + sysbus_realize_and_unref(sysbus, addr_of!(error_fatal) as *mut *mu= t Error); + sysbus_mmio_map(sysbus, 0, addr); + sysbus_connect_irq(sysbus, 0, irq); + dev + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_init(obj: *mut Object) { + unsafe { + debug_assert!(!obj.is_null()); + let mut state =3D NonNull::new_unchecked(obj.cast::()); + state.as_mut().init(); + } +} diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr= c/device_class.rs new file mode 100644 index 0000000000000000000000000000000000000000..b7ab31af02d7bb50ae94be0b153= baafc7ccfa375 --- /dev/null +++ b/rust/hw/char/pl011/src/device_class.rs @@ -0,0 +1,70 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::ptr::NonNull; + +use qemu_api::{bindings::*, definitions::ObjectImpl}; + +use crate::device::PL011State; + +#[used] +pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { + name: PL011State::TYPE_INFO.name, + unmigratable: true, + ..unsafe { ::core::mem::MaybeUninit::::zeroed().as= sume_init() } +}; + +qemu_api::declare_properties! { + PL011_PROPERTIES, + qemu_api::define_property!( + c"chardev", + PL011State, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + qemu_api::define_property!( + c"migrate-clk", + PL011State, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), +} + +qemu_api::device_class_init! { + pl011_class_init, + props =3D> PL011_PROPERTIES, + realize_fn =3D> Some(pl011_realize), + legacy_reset_fn =3D> Some(pl011_reset), + vmsd =3D> VMSTATE_PL011, +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { + unsafe { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().realize(); + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { + unsafe { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().reset(); + } +} diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs new file mode 100644 index 0000000000000000000000000000000000000000..2939ee50c99ceaacf6ec6812727= 2d58814e33679 --- /dev/null +++ b/rust/hw/char/pl011/src/lib.rs @@ -0,0 +1,586 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later +// +// PL011 QEMU Device Model +// +// This library implements a device model for the PrimeCell=C2=AE UART (PL= 011) +// device in QEMU. +// +#![doc =3D include_str!("../README.md")] +//! # Library crate +//! +//! See [`PL011State`](crate::device::PL011State) for the device model typ= e and +//! the [`registers`] module for register types. + +#![deny( + rustdoc::broken_intra_doc_links, + rustdoc::redundant_explicit_links, + clippy::correctness, + clippy::suspicious, + clippy::complexity, + clippy::perf, + clippy::cargo, + clippy::nursery, + clippy::style, + // restriction group + clippy::dbg_macro, + clippy::as_underscore, + clippy::assertions_on_result_states, + // pedantic group + clippy::doc_markdown, + clippy::borrow_as_ptr, + clippy::cast_lossless, + clippy::option_if_let_else, + clippy::missing_const_for_fn, + clippy::cognitive_complexity, + clippy::missing_safety_doc, + )] + +extern crate bilge; +extern crate bilge_impl; +extern crate qemu_api; + +pub mod device; +pub mod device_class; +pub mod memory_ops; + +pub const TYPE_PL011: &::core::ffi::CStr =3D c"pl011"; + +/// Offset of each register from the base memory address of the device. +/// +/// # Source +/// ARM DDI 0183G, Table 3-1 p.3-3 +#[doc(alias =3D "offset")] +#[allow(non_camel_case_types)] +#[repr(u64)] +#[derive(Debug)] +pub enum RegisterOffset { + /// Data Register + /// + /// A write to this register initiates the actual data transmission + #[doc(alias =3D "UARTDR")] + DR =3D 0x000, + /// Receive Status Register or Error Clear Register + #[doc(alias =3D "UARTRSR")] + #[doc(alias =3D "UARTECR")] + RSR =3D 0x004, + /// Flag Register + /// + /// A read of this register shows if transmission is complete + #[doc(alias =3D "UARTFR")] + FR =3D 0x018, + /// Fractional Baud Rate Register + /// + /// responsible for baud rate speed + #[doc(alias =3D "UARTFBRD")] + FBRD =3D 0x028, + /// `IrDA` Low-Power Counter Register + #[doc(alias =3D "UARTILPR")] + ILPR =3D 0x020, + /// Integer Baud Rate Register + /// + /// Responsible for baud rate speed + #[doc(alias =3D "UARTIBRD")] + IBRD =3D 0x024, + /// line control register (data frame format) + #[doc(alias =3D "UARTLCR_H")] + LCR_H =3D 0x02C, + /// Toggle UART, transmission or reception + #[doc(alias =3D "UARTCR")] + CR =3D 0x030, + /// Interrupt FIFO Level Select Register + #[doc(alias =3D "UARTIFLS")] + FLS =3D 0x034, + /// Interrupt Mask Set/Clear Register + #[doc(alias =3D "UARTIMSC")] + IMSC =3D 0x038, + /// Raw Interrupt Status Register + #[doc(alias =3D "UARTRIS")] + RIS =3D 0x03C, + /// Masked Interrupt Status Register + #[doc(alias =3D "UARTMIS")] + MIS =3D 0x040, + /// Interrupt Clear Register + #[doc(alias =3D "UARTICR")] + ICR =3D 0x044, + /// DMA control Register + #[doc(alias =3D "UARTDMACR")] + DMACR =3D 0x048, + ///// Reserved, offsets `0x04C` to `0x07C`. + //Reserved =3D 0x04C, +} + +impl core::convert::TryFrom for RegisterOffset { + type Error =3D u64; + + fn try_from(value: u64) -> Result { + macro_rules! case { + ($($discriminant:ident),*$(,)*) =3D> { + /* check that matching on all macro arguments compiles, wh= ich means we are not + * missing any enum value; if the type definition ever cha= nges this will stop + * compiling. + */ + const fn _assert_exhaustive(val: RegisterOffset) { + match val { + $(RegisterOffset::$discriminant =3D> (),)* + } + } + + match value { + $(x if x =3D=3D Self::$discriminant as u64 =3D> Ok(Sel= f::$discriminant),)* + _ =3D> Err(value), + } + } + } + case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, = MIS, ICR, DMACR } + } +} + +pub mod registers { + //! Device registers exposed as typed structs which are backed by arbi= trary + //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. + //! + //! All PL011 registers are essentially 32-bit wide, but are typed her= e as + //! bitmaps with only the necessary width. That is, if a struct bitmap + //! in this module is for example 16 bits long, it should be conceived + //! as a 32-bit register where the unmentioned higher bits are always + //! unused thus treated as zero when read or written. + use bilge::prelude::*; + + // TODO: FIFO Mode has different semantics + /// Data Register, `UARTDR` + /// + /// The `UARTDR` register is the data register. + /// + /// For words to be transmitted: + /// + /// - if the FIFOs are enabled, data written to this location is pushe= d onto + /// the transmit + /// FIFO + /// - if the FIFOs are not enabled, data is stored in the transmitter + /// holding register (the + /// bottom word of the transmit FIFO). + /// + /// The write operation initiates transmission from the UART. The data= is + /// prefixed with a start bit, appended with the appropriate parity bit + /// (if parity is enabled), and a stop bit. The resultant word is then + /// transmitted. + /// + /// For received words: + /// + /// - if the FIFOs are enabled, the data byte and the 4-bit status (br= eak, + /// frame, parity, + /// and overrun) is pushed onto the 12-bit wide receive FIFO + /// - if the FIFOs are not enabled, the data byte and status are store= d in + /// the receiving + /// holding register (the bottom word of the receive FIFO). + /// + /// The received data byte is read by performing reads from the `UARTD= R` + /// register along with the corresponding status information. The stat= us + /// information can also be read by a read of the `UARTRSR/UARTECR` + /// register. + /// + /// # Note + /// + /// You must disable the UART before any of the control registers are + /// reprogrammed. When the UART is disabled in the middle of + /// transmission or reception, it completes the current character befo= re + /// stopping. + /// + /// # Source + /// ARM DDI 0183G 3.3.1 Data Register, UARTDR + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + #[doc(alias =3D "UARTDR")] + pub struct Data { + _reserved: u4, + pub data: u8, + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + } + + // TODO: FIFO Mode has different semantics + /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` + /// + /// The UARTRSR/UARTECR register is the receive status register/error = clear + /// register. Receive status can also be read from the `UARTRSR` + /// register. If the status is read from this register, then the status + /// information for break, framing and parity corresponds to the + /// data character read from the [Data register](Data), `UARTDR` prior= to + /// reading the UARTRSR register. The status information for overrun is + /// set immediately when an overrun condition occurs. + /// + /// + /// # Note + /// The received data character must be read first from the [Data + /// Register](Data), `UARTDR` before reading the error status associat= ed + /// with that data character from the `UARTRSR` register. This read + /// sequence cannot be reversed, because the `UARTRSR` register is + /// updated only when a read occurs from the `UARTDR` register. Howeve= r, + /// the status information can also be obtained by reading the `UARTDR` + /// register + /// + /// # Source + /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, + /// UARTRSR/UARTECR + #[bitsize(8)] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct ReceiveStatusErrorClear { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + + impl ReceiveStatusErrorClear { + pub fn reset(&mut self) { + // All the bits are cleared to 0 on reset. + *self =3D 0.into(); + } + } + + impl Default for ReceiveStatusErrorClear { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Flag Register, `UARTFR` + #[doc(alias =3D "UARTFR")] + pub struct Flags { + /// CTS Clear to send. This bit is the complement of the UART clea= r to + /// send, `nUARTCTS`, modem status input. That is, the bit is 1 + /// when `nUARTCTS` is LOW. + pub clear_to_send: bool, + /// DSR Data set ready. This bit is the complement of the UART dat= a set + /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 w= hen + /// `nUARTDSR` is LOW. + pub data_set_ready: bool, + /// DCD Data carrier detect. This bit is the complement of the UAR= T data + /// carrier detect, `nUARTDCD`, modem status input. That is, the b= it is + /// 1 when `nUARTDCD` is LOW. + pub data_carrier_detect: bool, + /// BUSY UART busy. If this bit is set to 1, the UART is busy + /// transmitting data. This bit remains set until the complete + /// byte, including all the stop bits, has been sent from the + /// shift register. This bit is set as soon as the transmit FIFO + /// becomes non-empty, regardless of whether the UART is enabled + /// or not. + pub busy: bool, + /// RXFE Receive FIFO empty. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the receive holding + /// register is empty. If the FIFO is enabled, the RXFE bit is + /// set when the receive FIFO is empty. + pub receive_fifo_empty: bool, + /// TXFF Transmit FIFO full. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the transmit holding + /// register is full. If the FIFO is enabled, the TXFF bit is + /// set when the transmit FIFO is full. + pub transmit_fifo_full: bool, + /// RXFF Receive FIFO full. The meaning of this bit depends on the= state + /// of the FEN bit in the UARTLCR_H register. If the FIFO is + /// disabled, this bit is set when the receive holding register + /// is full. If the FIFO is enabled, the RXFF bit is set when + /// the receive FIFO is full. + pub receive_fifo_full: bool, + /// Transmit FIFO empty. The meaning of this bit depends on the st= ate of + /// the FEN bit in the [Line Control register](LineControl), + /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the + /// transmit holding register is empty. If the FIFO is enabled, + /// the TXFE bit is set when the transmit FIFO is empty. This + /// bit does not indicate if there is data in the transmit shift + /// register. + pub transmit_fifo_empty: bool, + /// `RI`, is `true` when `nUARTRI` is `LOW`. + pub ring_indicator: bool, + _reserved_zero_no_modify: u7, + } + + impl Flags { + pub fn reset(&mut self) { + // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a= re 1 + self.set_receive_fifo_full(false); + self.set_transmit_fifo_full(false); + self.set_busy(false); + self.set_receive_fifo_empty(true); + self.set_transmit_fifo_empty(true); + } + } + + impl Default for Flags { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Line Control Register, `UARTLCR_H` + #[doc(alias =3D "UARTLCR_H")] + pub struct LineControl { + /// 15:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u8, + /// 7 SPS Stick parity select. + /// 0 =3D stick parity is disabled + /// 1 =3D either: + /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked + /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table= 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// b10 =3D 7 bits + /// b01 =3D 6 bits + /// b00 =3D 5 bits. + pub word_length: WordLength, + /// FEN Enable FIFOs: + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// EPS Even parity select. Controls the type of parity the UART u= ses + /// during transmission and reception: + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + /// This bit has no effect when the `PEN` bit disables parity chec= king + /// and generation. See Table 3-11 on page 3-14 for the parity + /// truth table. + pub parity: Parity, + /// 1 PEN Parity enable: + /// + /// - 0 =3D parity is disabled and no parity bit added to the data= frame + /// - 1 =3D parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output o= n the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break comma= nd, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + } + + impl LineControl { + pub fn reset(&mut self) { + // All the bits are cleared to 0 when reset. + *self =3D 0.into(); + } + } + + impl Default for LineControl { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `EPS` "Even parity select", field of [Line Control + /// register](LineControl). + pub enum Parity { + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + Odd =3D 0, + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + Even =3D 1, + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control + /// register](LineControl). + pub enum Mode { + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers + Character =3D 0, + /// 1 =3D transmit and receive FIFO buffers are enabled (FIFO mode= ). + FIFO =3D 1, + } + + impl From for bool { + fn from(val: Mode) -> Self { + matches!(val, Mode::FIFO) + } + } + + #[bitsize(2)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `WLEN` Word length, field of [Line Control register](LineControl). + /// + /// These bits indicate the number of data bits transmitted or receive= d in a + /// frame as follows: + pub enum WordLength { + /// b11 =3D 8 bits + _8Bits =3D 0b11, + /// b10 =3D 7 bits + _7Bits =3D 0b10, + /// b01 =3D 6 bits + _6Bits =3D 0b01, + /// b00 =3D 5 bits. + _5Bits =3D 0b00, + } + + /// Control Register, `UARTCR` + /// + /// The `UARTCR` register is the control register. All the bits are cl= eared + /// to `0` on reset except for bits `9` and `8` that are set to `1`. + /// + /// # Source + /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 + #[bitsize(16)] + #[doc(alias =3D "UARTCR")] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct Control { + /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is d= isabled + /// in the middle of transmission or reception, it completes the c= urrent + /// character before stopping. 1 =3D the UART is enabled. Data + /// transmission and reception occurs for either UART signals or S= IR + /// signals depending on the setting of the SIREN bit. + pub enable_uart: bool, + /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIRO= UT` + /// remains LOW (no light pulse generated), and signal transitions= on + /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is + /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains= HIGH, + /// in the marking state. Signal transitions on UARTRXD or modem s= tatus + /// inputs have no effect. This bit has no effect if the UARTEN bit + /// disables the UART. + pub enable_sir: bool, + /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA enc= oding + /// mode. If this bit is cleared to 0, low-level bits are transmit= ted as + /// an active high pulse with a width of 3/ 16th of the bit period= . If + /// this bit is set to 1, low-level bits are transmitted with a pu= lse + /// width that is 3 times the period of the IrLPBaud16 input signa= l, + /// regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + pub sir_lowpower_irda_mode: u1, + /// Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u4, + /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN b= it is + /// set to 1 and the SIRTEST bit in the Test Control register, UAR= TTCR + /// on page 4-5 is set to 1, then the nSIROUT path is inverted, an= d fed + /// through to the SIRIN path. The SIRTEST bit in the test registe= r must + /// be set to 1 to override the normal half-duplex SIR operation. = This + /// must be the requirement for accessing the test registers during + /// normal operation, and SIRTEST must be cleared to 0 when loopba= ck + /// testing is finished. This feature reduces the amount of extern= al + /// coupling required during system test. If this bit is set to 1,= and + /// the SIRTEST bit is set to 0, the UARTTXD path is fed through t= o the + /// UARTRXD path. In either SIR mode or UART mode, when this bit i= s set, + /// the modem outputs are also fed through to the modem inputs. Th= is bit + /// is cleared to 0 on reset, to disable loopback. + pub enable_loopback: bool, + /// `TXE` Transmit enable. If this bit is set to 1, the transmit s= ection + /// of the UART is enabled. Data transmission occurs for either UA= RT + /// signals, or SIR signals depending on the setting of the SIREN = bit. + /// When the UART is disabled in the middle of transmission, it + /// completes the current character before stopping. + pub enable_transmit: bool, + /// `RXE` Receive enable. If this bit is set to 1, the receive sec= tion + /// of the UART is enabled. Data reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN b= it. + /// When the UART is disabled in the middle of reception, it compl= etes + /// the current character before stopping. + pub enable_receive: bool, + /// `DTR` Data transmit ready. This bit is the complement of the U= ART + /// data transmit ready, `nUARTDTR`, modem status output. That is,= when + /// the bit is programmed to a 1 then `nUARTDTR` is LOW. + pub data_transmit_ready: bool, + /// `RTS` Request to send. This bit is the complement of the UART + /// request to send, `nUARTRTS`, modem status output. That is, whe= n the + /// bit is programmed to a 1 then `nUARTRTS` is LOW. + pub request_to_send: bool, + /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1= `) + /// modem status output. That is, when the bit is programmed to a = 1 the + /// output is 0. For DTE this can be used as Data Carrier Detect (= DCD). + pub out_1: bool, + /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2= `) + /// modem status output. That is, when the bit is programmed to a = 1, the + /// output is 0. For DTE this can be used as Ring Indicator (RI). + pub out_2: bool, + /// `RTSEn` RTS hardware flow control enable. If this bit is set t= o 1, + /// RTS hardware flow control is enabled. Data is only requested w= hen + /// there is space in the receive FIFO for it to be received. + pub rts_hardware_flow_control_enable: bool, + /// `CTSEn` CTS hardware flow control enable. If this bit is set t= o 1, + /// CTS hardware flow control is enabled. Data is only transmitted= when + /// the `nUARTCTS` signal is asserted. + pub cts_hardware_flow_control_enable: bool, + } + + impl Control { + pub fn reset(&mut self) { + *self =3D 0.into(); + self.set_enable_receive(true); + self.set_enable_transmit(true); + } + } + + impl Default for Control { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC + pub const INT_OE: u32 =3D 1 << 10; + pub const INT_BE: u32 =3D 1 << 9; + pub const INT_PE: u32 =3D 1 << 8; + pub const INT_FE: u32 =3D 1 << 7; + pub const INT_RT: u32 =3D 1 << 6; + pub const INT_TX: u32 =3D 1 << 5; + pub const INT_RX: u32 =3D 1 << 4; + pub const INT_DSR: u32 =3D 1 << 3; + pub const INT_DCD: u32 =3D 1 << 2; + pub const INT_CTS: u32 =3D 1 << 1; + pub const INT_RI: u32 =3D 1 << 0; + pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + + #[repr(u32)] + pub enum Interrupt { + OE =3D 1 << 10, + BE =3D 1 << 9, + PE =3D 1 << 8, + FE =3D 1 << 7, + RT =3D 1 << 6, + TX =3D 1 << 5, + RX =3D 1 << 4, + DSR =3D 1 << 3, + DCD =3D 1 << 2, + CTS =3D 1 << 1, + RI =3D 1 << 0, + } + + impl Interrupt { + pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + } +} + +// TODO: You must disable the UART before any of the control registers are +// reprogrammed. When the UART is disabled in the middle of transmission or +// reception, it completes the current character before stopping diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/= memory_ops.rs new file mode 100644 index 0000000000000000000000000000000000000000..8d066ebf6d016fa30db00493375= 1a854d7e59117 --- /dev/null +++ b/rust/hw/char/pl011/src/memory_ops.rs @@ -0,0 +1,59 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::device::PL011State; + +pub static PL011_OPS: MemoryRegionOps =3D MemoryRegionOps { + read: Some(pl011_read), + write: Some(pl011_write), + read_with_attrs: None, + write_with_attrs: None, + endianness: device_endian::DEVICE_NATIVE_ENDIAN, + valid: unsafe { MaybeUninit::::zeroed()= .assume_init() }, + impl_: MemoryRegionOps__bindgen_ty_2 { + min_access_size: 4, + max_access_size: 4, + ..unsafe { MaybeUninit::::zeroed().= assume_init() } + }, +}; + +#[no_mangle] +unsafe extern "C" fn pl011_read( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + size: core::ffi::c_uint, +) -> u64 { + assert!(!opaque.is_null()); + let mut state =3D unsafe { NonNull::new_unchecked(opaque.cast::()) }; + let val =3D unsafe { state.as_mut().read(addr, size) }; + match val { + std::ops::ControlFlow::Break(val) =3D> val, + std::ops::ControlFlow::Continue(val) =3D> { + // SAFETY: self.char_backend is a valid CharBackend instance a= fter it's been + // initialized in realize(). + let cb_ptr =3D unsafe { core::ptr::addr_of_mut!(state.as_mut()= .char_backend) }; + unsafe { qemu_chr_fe_accept_input(cb_ptr) }; + + val + } + } +} + +#[no_mangle] +unsafe extern "C" fn pl011_write( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + data: u64, + _size: core::ffi::c_uint, +) { + unsafe { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); + state.as_mut().write(addr, data) + } +} diff --git a/rust/hw/meson.build b/rust/hw/meson.build new file mode 100644 index 0000000000000000000000000000000000000000..860196645e719624d2e2e6bc301= b62b81ab2e19b --- /dev/null +++ b/rust/hw/meson.build @@ -0,0 +1 @@ +subdir('char') diff --git a/rust/meson.build b/rust/meson.build index 7a32b1b195083571931ad589965c10ddaf6383b1..def77389cddc52f5d4503840e9b= dfb1207586fa2 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -1,2 +1,4 @@ subdir('qemu-api-macros') subdir('qemu-api') + +subdir('hw') diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh index 62a2cf45d28ed5565076443b9f931a647d395542..30677c3ec9032ea01090f74602d= 839d1c571d012 100755 --- a/scripts/archive-source.sh +++ b/scripts/archive-source.sh @@ -27,7 +27,9 @@ sub_file=3D"${sub_tdir}/submodule.tar" # in their checkout, because the build environment is completely # different to the host OS. subprojects=3D"keycodemapdb libvfio-user berkeley-softfloat-3 - berkeley-testfloat-3 proc-macro2-1-rs quote-1-rs + berkeley-testfloat-3 arbitrary-int-1-rs bilge-0.2-rs + bilge-impl-0.2-rs either-1-rs itertools-0.11-rs proc-macro2-1-rs + proc-macro-error-1-rs proc-macro-error-attr-1-rs quote-1-rs syn-2-rs unicode-ident-1-rs" sub_deinit=3D"" =20 diff --git a/scripts/make-release b/scripts/make-release index cf7d694ef73ba1c6c5afad5d211a42f6a6fe1577..8dc939124c4fd4abf3509c3b64c= 0588bc8810962 100755 --- a/scripts/make-release +++ b/scripts/make-release @@ -18,7 +18,9 @@ fi =20 # Only include wraps that are invoked with subproject() SUBPROJECTS=3D"libvfio-user keycodemapdb berkeley-softfloat-3 - berkeley-testfloat-3 proc-macro2-1-rs quote-1-rs + berkeley-testfloat-3 arbitrary-int-1-rs bilge-0.2-rs + bilge-impl-0.2-rs either-1-rs itertools-0.11-rs proc-macro2-1-rs + proc-macro-error-1-rs proc-macro-error-attr-1-rs quote-1-rs syn-2-rs unicode-ident-1-rs" =20 src=3D"$1" diff --git a/scripts/rust/rust_root_crate.sh b/scripts/rust/rust_root_crate= .sh new file mode 100755 index 0000000000000000000000000000000000000000..975bddf7f1a4c6ca7770f800bdc= 894cdff1f3ab1 --- /dev/null +++ b/scripts/rust/rust_root_crate.sh @@ -0,0 +1,13 @@ +#!/bin/sh + +set -eu + +cat < (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778658587628.9139644200035; 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778659832116600 Add a new derive procedural macro to declare device models. Add corresponding DeviceImpl trait after already existing ObjectImpl trait. At the same time, add instance_init, instance_post_init, instance_finalize methods to the ObjectImpl trait and call them from the ObjectImplUnsafe trait, which is generated by the procedural macro. This allows all the boilerplate device model registration to be handled by macros, and all pertinent details to be declared through proc macro attributes or trait associated constants and methods. The device class can now be generated automatically and the name can be optionally overridden: ------------------------ >8 ------------------------ #[repr(C)] #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::Device)] #[device(class_name_override =3D PL011Class)] /// PL011 Device Model in QEMU pub struct PL011State { ------------------------ >8 ------------------------ Properties are now marked as field attributes: ------------------------ >8 ------------------------ #[property(name =3D c"chardev", qdev_prop =3D qdev_prop_chr)] pub char_backend: CharBackend, ------------------------ >8 ------------------------ Object methods (instance_init, etc) methods are now trait methods: ------------------------ >8 ------------------------ /// Trait a type must implement to be registered with QEMU. pub trait ObjectImpl { type Class: ClassImpl; const TYPE_NAME: &'static CStr; const PARENT_TYPE_NAME: Option<&'static CStr>; const ABSTRACT: bool; unsafe fn instance_init(&mut self) {} fn instance_post_init(&mut self) {} fn instance_finalize(&mut self) {} } ------------------------ >8 ------------------------ Device methods (realize/reset etc) are now safe idiomatic trait methods: ------------------------ >8 ------------------------ /// Implementation methods for device types. pub trait DeviceImpl: ObjectImpl { fn realize(&mut self) {} fn reset(&mut self) {} } ------------------------ >8 ------------------------ The derive Device macro is responsible for creating all the extern "C" FFI functions that QEMU needs to call these methods. Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 124 +++----- rust/hw/char/pl011/src/device_class.rs | 70 ----- rust/hw/char/pl011/src/lib.rs | 1 - rust/qemu-api-macros/src/device.rs | 433 ++++++++++++++++++++++= ++++ rust/qemu-api-macros/src/lib.rs | 45 +-- rust/qemu-api-macros/src/object.rs | 107 +++++++ rust/qemu-api-macros/src/symbols.rs | 55 ++++ rust/qemu-api-macros/src/utilities.rs | 152 +++++++++ rust/qemu-api/meson.build | 3 +- rust/qemu-api/src/definitions.rs | 97 ------ rust/qemu-api/src/device_class.rs | 128 -------- rust/qemu-api/src/lib.rs | 6 +- rust/qemu-api/src/objects.rs | 90 ++++++ rust/qemu-api/src/tests.rs | 49 --- subprojects/packagefiles/syn-2-rs/meson.build | 1 + 15 files changed, 902 insertions(+), 459 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index c7193b41beec0b177dbc75ac0e43fcfea4c82bfb..c469877b1ca70dd1a02e3a2449c= 65ad3e57c93ae 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -9,7 +9,7 @@ =20 use qemu_api::{ bindings::{self, *}, - definitions::ObjectImpl, + objects::*, }; =20 use crate::{ @@ -26,7 +26,8 @@ pub const PL011_FIFO_DEPTH: usize =3D 16_usize; =20 #[repr(C)] -#[derive(Debug, qemu_api_macros::Object)] +#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::Device)] +#[device(class_name_override =3D PL011Class)] /// PL011 Device Model in QEMU pub struct PL011State { pub parent_obj: SysBusDevice, @@ -51,6 +52,7 @@ pub struct PL011State { pub read_count: usize, pub read_trigger: usize, #[doc(alias =3D "chr")] + #[property(name =3D c"chardev", qdev_prop =3D qdev_prop_chr)] pub char_backend: CharBackend, /// QEMU interrupts /// @@ -68,38 +70,17 @@ pub struct PL011State { #[doc(alias =3D "clk")] pub clock: NonNull, #[doc(alias =3D "migrate_clk")] + #[property(name =3D c"migrate-clk", qdev_prop =3D qdev_prop_bool)] pub migrate_clock: bool, } =20 impl ObjectImpl for PL011State { type Class =3D PL011Class; - const TYPE_INFO: qemu_api::bindings::TypeInfo =3D qemu_api::type_info!= { Self }; + const TYPE_NAME: &'static CStr =3D crate::TYPE_PL011; const PARENT_TYPE_NAME: Option<&'static CStr> =3D Some(TYPE_SYS_BUS_DE= VICE); const ABSTRACT: bool =3D false; - const INSTANCE_INIT: Option = =3D Some(pl011_init); - const INSTANCE_POST_INIT: Option =3D None; - const INSTANCE_FINALIZE: Option =3D None; -} =20 -#[repr(C)] -pub struct PL011Class { - _inner: [u8; 0], -} - -impl qemu_api::definitions::Class for PL011Class { - const CLASS_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), - > =3D Some(crate::device_class::pl011_class_init); - const CLASS_BASE_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), - > =3D None; -} - -#[used] -pub static CLK_NAME: &CStr =3D c"clk"; - -impl PL011State { /// Initializes a pre-allocated, unitialized instance of `PL011State`. /// /// # Safety @@ -108,7 +89,7 @@ impl PL011State { /// `PL011State` type. It must not be called more than once on the same /// location/instance. All its fields are expected to hold unitialized /// values with the sole exception of `parent_obj`. - pub unsafe fn init(&mut self) { + unsafe fn instance_init(&mut self) { let dev =3D addr_of_mut!(*self).cast::(); // SAFETY: // @@ -120,7 +101,7 @@ pub unsafe fn init(&mut self) { addr_of_mut!(*self).cast::(), &PL011_OPS, addr_of_mut!(*self).cast::(), - Self::TYPE_INFO.name, + Self::TYPE_NAME.as_ptr(), 0x1000, ); let sbd =3D addr_of_mut!(*self).cast::(); @@ -147,7 +128,49 @@ pub unsafe fn init(&mut self) { .unwrap(); } } +} =20 +impl DeviceImpl for PL011State { + fn realize(&mut self) { + // SAFETY: self.char_backend has the correct size and alignment fo= r a + // CharBackend object, and its callbacks are of the correct types. + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + fn reset(&mut self) { + self.line_control.reset(); + self.receive_status_error_clear.reset(); + self.dmacr =3D 0; + self.int_enabled =3D 0; + self.int_level =3D 0; + self.ilpr =3D 0; + self.ibrd =3D 0; + self.fbrd =3D 0; + self.read_trigger =3D 1; + self.ifl =3D 0x12; + self.control.reset(); + self.flags =3D 0.into(); + self.reset_fifo(); + } +} + +impl qemu_api::objects::Migrateable for PL011State {} + +#[used] +pub static CLK_NAME: &CStr =3D c"clk"; + +impl PL011State { pub fn read( &mut self, offset: hwaddr, @@ -394,39 +417,6 @@ fn set_read_trigger(&mut self) { self.read_trigger =3D 1; } =20 - pub fn realize(&mut self) { - // SAFETY: self.char_backend has the correct size and alignment fo= r a - // CharBackend object, and its callbacks are of the correct types. - unsafe { - qemu_chr_fe_set_handlers( - addr_of_mut!(self.char_backend), - Some(pl011_can_receive), - Some(pl011_receive), - Some(pl011_event), - None, - addr_of_mut!(*self).cast::(), - core::ptr::null_mut(), - true, - ); - } - } - - pub fn reset(&mut self) { - self.line_control.reset(); - self.receive_status_error_clear.reset(); - self.dmacr =3D 0; - self.int_enabled =3D 0; - self.int_level =3D 0; - self.ilpr =3D 0; - self.ibrd =3D 0; - self.fbrd =3D 0; - self.read_trigger =3D 1; - self.ifl =3D 0x12; - self.control.reset(); - self.flags =3D 0.into(); - self.reset_fifo(); - } - pub fn reset_fifo(&mut self) { self.read_count =3D 0; self.read_pos =3D 0; @@ -583,17 +573,3 @@ pub fn update(&self) { dev } } - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_init(obj: *mut Object) { - unsafe { - debug_assert!(!obj.is_null()); - let mut state =3D NonNull::new_unchecked(obj.cast::()); - state.as_mut().init(); - } -} diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr= c/device_class.rs deleted file mode 100644 index b7ab31af02d7bb50ae94be0b153baafc7ccfa375..000000000000000000000000000= 0000000000000 --- a/rust/hw/char/pl011/src/device_class.rs +++ /dev/null @@ -1,70 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -use core::ptr::NonNull; - -use qemu_api::{bindings::*, definitions::ObjectImpl}; - -use crate::device::PL011State; - -#[used] -pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { - name: PL011State::TYPE_INFO.name, - unmigratable: true, - ..unsafe { ::core::mem::MaybeUninit::::zeroed().as= sume_init() } -}; - -qemu_api::declare_properties! { - PL011_PROPERTIES, - qemu_api::define_property!( - c"chardev", - PL011State, - char_backend, - unsafe { &qdev_prop_chr }, - CharBackend - ), - qemu_api::define_property!( - c"migrate-clk", - PL011State, - migrate_clock, - unsafe { &qdev_prop_bool }, - bool - ), -} - -qemu_api::device_class_init! { - pl011_class_init, - props =3D> PL011_PROPERTIES, - realize_fn =3D> Some(pl011_realize), - legacy_reset_fn =3D> Some(pl011_reset), - vmsd =3D> VMSTATE_PL011, -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { - unsafe { - assert!(!dev.is_null()); - let mut state =3D NonNull::new_unchecked(dev.cast::()); - state.as_mut().realize(); - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { - unsafe { - assert!(!dev.is_null()); - let mut state =3D NonNull::new_unchecked(dev.cast::()); - state.as_mut().reset(); - } -} diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index 2939ee50c99ceaacf6ec68127272d58814e33679..f4d9cce4b01f605cfcbec7ea87c= 8b2009d77ee52 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -42,7 +42,6 @@ extern crate qemu_api; =20 pub mod device; -pub mod device_class; pub mod memory_ops; =20 pub const TYPE_PL011: &::core::ffi::CStr =3D c"pl011"; diff --git a/rust/qemu-api-macros/src/device.rs b/rust/qemu-api-macros/src/= device.rs new file mode 100644 index 0000000000000000000000000000000000000000..3b965576a065601cd5c97d5ab6a= 2501f96d16a61 --- /dev/null +++ b/rust/qemu-api-macros/src/device.rs @@ -0,0 +1,433 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use proc_macro::TokenStream; +use quote::{format_ident, quote, ToTokens}; +use syn::{ + parse::{Parse, ParseStream}, + Result, +}; +use syn::{parse_macro_input, DeriveInput}; + +use crate::{symbols::*, utilities::*}; + +#[derive(Debug, Default)] +struct DeriveContainer { + category: Option, + class_name: Option, + class_name_override: Option, +} + +impl Parse for DeriveContainer { + fn parse(input: ParseStream) -> Result { + let _: syn::Token![#] =3D input.parse()?; + let bracketed; + _ =3D syn::bracketed!(bracketed in input); + assert_eq!(DEVICE, bracketed.parse::()?); + let mut retval =3D Self { + category: None, + class_name: None, + class_name_override: None, + }; + let content; + _ =3D syn::parenthesized!(content in bracketed); + while !content.is_empty() { + let value: syn::Ident =3D content.parse()?; + if value =3D=3D CLASS_NAME { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.class_name.is_some() { + panic!("{} can only be used at most once", CLASS_NAME); + } + retval.class_name =3D Some(content.parse()?); + } else if value =3D=3D CLASS_NAME_OVERRIDE { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.class_name_override.is_some() { + panic!("{} can only be used at most once", CLASS_NAME_= OVERRIDE); + } + retval.class_name_override =3D Some(content.parse()?); + } else if value =3D=3D CATEGORY { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.category.is_some() { + panic!("{} can only be used at most once", CATEGORY); + } + let lit: syn::LitStr =3D content.parse()?; + let path: syn::Path =3D lit.parse()?; + retval.category =3D Some(path); + } else { + panic!("unrecognized token `{}`", value); + } + + if !content.is_empty() { + let _: syn::Token![,] =3D content.parse()?; + } + } + if retval.class_name.is_some() && retval.class_name_override.is_so= me() { + panic!( + "Cannot define `{}` and `{}` at the same time", + CLASS_NAME, CLASS_NAME_OVERRIDE + ); + } + Ok(retval) + } +} + +#[derive(Debug)] +struct QdevProperty { + name: Option, + qdev_prop: Option, +} + +impl Parse for QdevProperty { + fn parse(input: ParseStream) -> Result { + let _: syn::Token![#] =3D input.parse()?; + let bracketed; + _ =3D syn::bracketed!(bracketed in input); + assert_eq!(PROPERTY, bracketed.parse::()?); + let mut retval =3D Self { + name: None, + qdev_prop: None, + }; + let content; + _ =3D syn::parenthesized!(content in bracketed); + while !content.is_empty() { + let value: syn::Ident =3D content.parse()?; + if value =3D=3D NAME { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.name.is_some() { + panic!("{} can only be used at most once", NAME); + } + retval.name =3D Some(content.parse()?); + } else if value =3D=3D QDEV_PROP { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.qdev_prop.is_some() { + panic!("{} can only be used at most once", QDEV_PROP); + } + retval.qdev_prop =3D Some(content.parse()?); + } else { + panic!("unrecognized token `{}`", value); + } + + if !content.is_empty() { + let _: syn::Token![,] =3D content.parse()?; + } + } + Ok(retval) + } +} + +pub fn derive_device(input: TokenStream) -> TokenStream { + let input =3D parse_macro_input!(input as DeriveInput); + + assert_is_repr_c_struct(&input, "Device"); + + let derive_container: DeriveContainer =3D input + .attrs + .iter() + .find(|a| a.path() =3D=3D DEVICE) + .map(|a| syn::parse(a.to_token_stream().into()).expect("could not = parse device attr")) + .unwrap_or_default(); + let (qdev_properties_static, qdev_properties_expanded) =3D make_qdev_p= roperties(&input); + let class_expanded =3D gen_device_class(derive_container, qdev_propert= ies_static, &input.ident); + let name =3D input.ident; + + let realize_fn =3D format_ident!("__{}_realize_generated", name); + let reset_fn =3D format_ident!("__{}_reset_generated", name); + + let expanded =3D quote! { + unsafe impl ::qemu_api::objects::DeviceImplUnsafe for #name { + const REALIZE: ::core::option::Option< + unsafe extern "C" fn( + dev: *mut ::qemu_api::bindings::DeviceState, + errp: *mut *mut ::qemu_api::bindings::Error, + ), + > =3D Some(#realize_fn); + const RESET: ::core::option::Option< + unsafe extern "C" fn(dev: *mut ::qemu_api::bindings::Devic= eState), + > =3D Some(#reset_fn); + } + + #[no_mangle] + pub unsafe extern "C" fn #realize_fn( + dev: *mut ::qemu_api::bindings::DeviceState, + errp: *mut *mut ::qemu_api::bindings::Error, + ) { + let mut instance =3D NonNull::new(dev.cast::<#name>()).expect(= concat!("Expected dev to be a non-null pointer of type ", stringify!(#name)= )); + unsafe { + ::qemu_api::objects::DeviceImpl::realize(instance.as_mut()= ); + } + } + + #[no_mangle] + pub unsafe extern "C" fn #reset_fn( + dev: *mut ::qemu_api::bindings::DeviceState, + ) { + let mut instance =3D NonNull::new(dev.cast::<#name>()).expect(= concat!("Expected dev to be a non-null pointer of type ", stringify!(#name)= )); + unsafe { + ::qemu_api::objects::DeviceImpl::reset(instance.as_mut()); + } + } + + #qdev_properties_expanded + #class_expanded + }; + + TokenStream::from(expanded) +} + +fn make_qdev_properties(input: &DeriveInput) -> (syn::Ident, proc_macro2::= TokenStream) { + let name =3D &input.ident; + + let qdev_properties: Vec<(syn::Field, QdevProperty)> =3D match &input.= data { + syn::Data::Struct(syn::DataStruct { + fields: syn::Fields::Named(fields), + .. + }) =3D> fields + .named + .iter() + .map(|f| { + f.attrs + .iter() + .filter(|a| a.path() =3D=3D PROPERTY) + .map(|a| (f.clone(), a.clone())) + }) + .flatten() + .map(|(f, a)| { + ( + f.clone(), + syn::parse(a.to_token_stream().into()).expect("could n= ot parse property attr"), + ) + }) + .collect::>(), + _other =3D> unreachable!(), + }; + + let mut properties_expanded =3D quote! { + unsafe { ::core::mem::MaybeUninit::<::qemu_api::bindings::Property= >::zeroed().assume_init() } + }; + let prop_len =3D qdev_properties.len() + 1; + for (field, prop) in qdev_properties { + let prop_name =3D prop.name.as_ref().unwrap(); + let field_name =3D field.ident.as_ref().unwrap(); + let qdev_prop =3D prop.qdev_prop.as_ref().unwrap(); + let prop =3D quote! { + ::qemu_api::bindings::Property { + name: ::core::ffi::CStr::as_ptr(#prop_name), + info: unsafe { &#qdev_prop }, + offset: ::core::mem::offset_of!(#name, #field_name) as _, + bitnr: 0, + bitmask: 0, + set_default: false, + defval: ::qemu_api::bindings::Property__bindgen_ty_1 { i: = 0 }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; + properties_expanded =3D quote! { + #prop, + #properties_expanded + }; + } + let properties_ident =3D format_ident!("__{}_QDEV_PROPERTIES", name); + let expanded =3D quote! { + #[no_mangle] + pub static mut #properties_ident: [::qemu_api::bindings::Property;= #prop_len] =3D [#properties_expanded]; + }; + (properties_ident, expanded) +} + +fn gen_device_class( + derive_container: DeriveContainer, + qdev_properties_static: syn::Ident, + name: &syn::Ident, +) -> proc_macro2::TokenStream { + let (class_name, class_def) =3D match ( + derive_container.class_name_override, + derive_container.class_name, + ) { + (Some(class_name), _) =3D> { + let class_expanded =3D quote! { + #[repr(C)] + pub struct #class_name { + _inner: [u8; 0], + } + }; + (class_name, class_expanded) + } + (None, Some(class_name)) =3D> (class_name, quote! {}), + (None, None) =3D> { + let class_name =3D format_ident!("{}Class", name); + let class_expanded =3D quote! { + #[repr(C)] + pub struct #class_name { + _inner: [u8; 0], + } + }; + (class_name, class_expanded) + } + }; + let class_init_fn =3D format_ident!("__{}_class_init_generated", class= _name); + let class_base_init_fn =3D format_ident!("__{}_class_base_init_generat= ed", class_name); + + let (vmsd, vmsd_impl) =3D { + let (i, vmsd) =3D make_vmstate(name); + (quote! { &#i }, vmsd) + }; + let category =3D if let Some(category) =3D derive_container.category { + quote! { + const BITS_PER_LONG: u32 =3D ::core::ffi::c_ulong::BITS; + let _: ::qemu_api::bindings::DeviceCategory =3D #category; + let nr: ::core::ffi::c_ulong =3D #category as _; + let mask =3D 1 << (nr as u32 % BITS_PER_LONG); + let p =3D ::core::ptr::addr_of_mut!(dc.as_mut().categories).of= fset((nr as u32 / BITS_PER_LONG) as isize); + let p: *mut ::core::ffi::c_ulong =3D p.cast(); + let categories =3D p.read_unaligned(); + p.write_unaligned(categories | mask); + } + } else { + quote! {} + }; + let props =3D quote! { + ::qemu_api::bindings::device_class_set_props(dc.as_mut(), #qdev_pr= operties_static.as_mut_ptr()); + }; + + quote! { + #class_def + + impl ::qemu_api::objects::ClassImpl for #class_name { + type Object =3D #name; + } + + unsafe impl ::qemu_api::objects::ClassImplUnsafe for #class_name { + const CLASS_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c= ore::ffi::c_void), + > =3D Some(#class_init_fn); + const CLASS_BASE_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c= ore::ffi::c_void), + > =3D Some(#class_base_init_fn); + } + + #[no_mangle] + pub unsafe extern "C" fn #class_init_fn(klass: *mut ObjectClass, d= ata: *mut core::ffi::c_void) { + { + { + let mut dc =3D + ::core::ptr::NonNull::new(klass.cast::<::qemu_api:= :bindings::DeviceClass>()).unwrap(); + unsafe { + dc.as_mut().realize =3D + <#name as ::qemu_api::objects::DeviceImplUnsaf= e>::REALIZE; + ::qemu_api::bindings::device_class_set_legacy_rese= t( + dc.as_mut(), + <#name as ::qemu_api::objects::DeviceImplUnsaf= e>::RESET + ); + dc.as_mut().vmsd =3D #vmsd; + #props + #category + } + } + let mut klass =3D NonNull::new(klass.cast::<#class_name>()= ).expect(concat!("Expected klass to be a non-null pointer of type ", string= ify!(#class_name))); + unsafe { + ::qemu_api::objects::ClassImpl::class_init(klass.as_mu= t(), data); + } + } + } + #[no_mangle] + pub unsafe extern "C" fn #class_base_init_fn(klass: *mut ObjectCla= ss, data: *mut core::ffi::c_void) { + { + let mut klass =3D NonNull::new(klass.cast::<#class_name>()= ).expect(concat!("Expected klass to be a non-null pointer of type ", string= ify!(#class_name))); + unsafe { + ::qemu_api::objects::ClassImpl::class_base_init(klass.= as_mut(), data); + } + } + } + + #vmsd_impl + } +} + +fn make_vmstate(name: &syn::Ident) -> (syn::Ident, proc_macro2::TokenStrea= m) { + let vmstate_description_ident =3D format_ident!("__VMSTATE_{}", name); + + let pre_load =3D format_ident!("__{}_pre_load_generated", name); + let post_load =3D format_ident!("__{}_post_load_generated", name); + let pre_save =3D format_ident!("__{}_pre_save_generated", name); + let post_save =3D format_ident!("__{}_post_save_generated", name); + let needed =3D format_ident!("__{}_needed_generated", name); + let dev_unplug_pending =3D format_ident!("__{}_dev_unplug_pending_gene= rated", name); + + let migrateable_fish =3D quote! {<#name as ::qemu_api::objects::Migrat= eable>}; + let vmstate_description =3D quote! { + #[used] + #[allow(non_upper_case_globals)] + pub static #vmstate_description_ident: ::qemu_api::bindings::VMSta= teDescription =3D ::qemu_api::bindings::VMStateDescription { + name: if let Some(name) =3D #migrateable_fish::NAME { + name.as_ptr() + } else { + <#name as ::qemu_api::objects::ObjectImplUnsafe>::TYPE_INF= O.name + }, + unmigratable: #migrateable_fish::UNMIGRATABLE, + early_setup: #migrateable_fish::EARLY_SETUP, + version_id: #migrateable_fish::VERSION_ID, + minimum_version_id: #migrateable_fish::MINIMUM_VERSION_ID, + priority: #migrateable_fish::PRIORITY, + pre_load: Some(#pre_load), + post_load: Some(#post_load), + pre_save: Some(#pre_save), + post_save: Some(#post_save), + needed: Some(#needed), + dev_unplug_pending: Some(#dev_unplug_pending), + fields: ::core::ptr::null(), + subsections: ::core::ptr::null(), + }; + + #[no_mangle] + pub unsafe extern "C" fn #pre_load(opaque: *mut ::core::ffi::c_voi= d) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::pre_load(instance.as_mut= ()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #post_load(opaque: *mut ::core::ffi::c_vo= id, version_id: core::ffi::c_int) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::post_load(instance.as_mu= t(), version_id) + } + } + #[no_mangle] + pub unsafe extern "C" fn #pre_save(opaque: *mut ::core::ffi::c_voi= d) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::pre_save(instance.as_mut= ()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #post_save(opaque: *mut ::core::ffi::c_vo= id) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::post_save(instance.as_mu= t()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #needed(opaque: *mut ::core::ffi::c_void)= -> bool { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::needed(instance.as_mut()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #dev_unplug_pending(opaque: *mut ::core::= ffi::c_void) -> bool { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::dev_unplug_pending(insta= nce.as_mut()) + } + } + }; + + let expanded =3D quote! { + #vmstate_description + }; + (vmstate_description_ident, expanded) +} diff --git a/rust/qemu-api-macros/src/lib.rs b/rust/qemu-api-macros/src/lib= .rs index 59aba592d9ae4c5a4cdfdc6f9b9b08363b8a57e5..7753a853fae72fc87e6dc642cf0= 76c6d0c736345 100644 --- a/rust/qemu-api-macros/src/lib.rs +++ b/rust/qemu-api-macros/src/lib.rs @@ -2,42 +2,21 @@ // Author(s): Manos Pitsidianakis // SPDX-License-Identifier: GPL-2.0-or-later =20 +#![allow(dead_code)] + use proc_macro::TokenStream; -use quote::{format_ident, quote}; -use syn::{parse_macro_input, DeriveInput}; + +mod device; +mod object; +mod symbols; +mod utilities; =20 #[proc_macro_derive(Object)] pub fn derive_object(input: TokenStream) -> TokenStream { - let input =3D parse_macro_input!(input as DeriveInput); - - let name =3D input.ident; - let module_static =3D format_ident!("__{}_LOAD_MODULE", name); - - let expanded =3D quote! { - #[allow(non_upper_case_globals)] - #[used] - #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] - #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] - #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] - pub static #module_static: extern "C" fn() =3D { - extern "C" fn __register() { - unsafe { - ::qemu_api::bindings::type_register_static(&<#name as = ::qemu_api::definitions::ObjectImpl>::TYPE_INFO); - } - } - - extern "C" fn __load() { - unsafe { - ::qemu_api::bindings::register_module_init( - Some(__register), - ::qemu_api::bindings::module_init_type::MODULE_INI= T_QOM - ); - } - } - - __load - }; - }; + object::derive_object(input) +} =20 - TokenStream::from(expanded) +#[proc_macro_derive(Device, attributes(device, property))] +pub fn derive_device(input: TokenStream) -> TokenStream { + device::derive_device(input) } diff --git a/rust/qemu-api-macros/src/object.rs b/rust/qemu-api-macros/src/= object.rs new file mode 100644 index 0000000000000000000000000000000000000000..f808069aea42de752dea7524fef= 64467427f105c --- /dev/null +++ b/rust/qemu-api-macros/src/object.rs @@ -0,0 +1,107 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use proc_macro::TokenStream; +use quote::{format_ident, quote}; +use syn::{parse_macro_input, DeriveInput}; + +use crate::utilities::*; + +pub fn derive_object(input: TokenStream) -> TokenStream { + let input =3D parse_macro_input!(input as DeriveInput); + + assert_is_repr_c_struct(&input, "Object"); + + let name =3D input.ident; + let module_static =3D format_ident!("__{}_LOAD_MODULE", name); + + let ctors =3D quote! { + #[allow(non_upper_case_globals)] + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static #module_static: extern "C" fn() =3D { + extern "C" fn __register() { + unsafe { + ::qemu_api::bindings::type_register_static(&<#name as = ::qemu_api::objects::ObjectImplUnsafe>::TYPE_INFO); + } + } + + extern "C" fn __load() { + unsafe { + ::qemu_api::bindings::register_module_init( + Some(__register), + ::qemu_api::bindings::module_init_type::MODULE_INI= T_QOM + ); + } + } + + __load + }; + }; + + let instance_init =3D format_ident!("__{}_instance_init_generated", na= me); + let instance_post_init =3D format_ident!("__{}_instance_post_init_gene= rated", name); + let instance_finalize =3D format_ident!("__{}_instance_finalize_genera= ted", name); + + let obj_impl_unsafe =3D quote! { + unsafe impl ::qemu_api::objects::ObjectImplUnsafe for #name { + const TYPE_INFO: ::qemu_api::bindings::TypeInfo =3D + ::qemu_api::bindings::TypeInfo { + name: ::TYPE_= NAME.as_ptr(), + parent: if let Some(pname) =3D ::PARENT_TYPE_NAME { + pname.as_ptr() + } else { + ::core::ptr::null() + }, + instance_size: ::core::mem::size_of::() as ::qem= u_api::bindings::size_t, + instance_align: ::core::mem::align_of::() as ::q= emu_api::bindings::size_t, + instance_init: ::INSTANCE_INIT, + instance_post_init: ::INSTANCE_POST_INIT, + instance_finalize: ::INSTANCE_FINALIZE, + abstract_: ::= ABSTRACT, + class_size: ::core::mem::size_of::<::Class>() as ::qemu_api::bindings::size_t, + class_init: <= ::Class as ::qemu_api::objects::ClassImplUnsafe>::CLASS_INIT, + class_base_init: <::Class as ::qemu_api::objects::ClassImplUnsafe>::CLASS_BASE_INIT, + class_data: ::core::ptr::null_mut(), + interfaces: ::core::ptr::null_mut(), + }; + const INSTANCE_INIT: Option =3D Some(#instance_init); + const INSTANCE_POST_INIT: Option =3D Some(#instance_post_init); + const INSTANCE_FINALIZE: Option =3D Some(#instance_finalize); + } + + #[no_mangle] + pub unsafe extern "C" fn #instance_init(obj: *mut ::qemu_api::bind= ings::Object) { + let mut instance =3D NonNull::new(obj.cast::<#name>()).expect(= concat!("Expected obj to be a non-null pointer of type ", stringify!(#name)= )); + unsafe { + ::qemu_api::objects::ObjectImpl::instance_init(instance.as= _mut()); + } + } + + #[no_mangle] + pub unsafe extern "C" fn #instance_post_init(obj: *mut ::qemu_api:= :bindings::Object) { + let mut instance =3D NonNull::new(obj.cast::<#name>()).exp= ect(concat!("Expected obj to be a non-null pointer of type ", stringify!(#n= ame))); + unsafe { + ::qemu_api::objects::ObjectImpl::instance_post_init(instan= ce.as_mut()); + } + } + + #[no_mangle] + pub unsafe extern "C" fn #instance_finalize(obj: *mut ::qemu_api::= bindings::Object) { + let mut instance =3D NonNull::new(obj.cast::<#name>()).exp= ect(concat!("Expected obj to be a non-null pointer of type ", stringify!(#n= ame))); + unsafe { + ::qemu_api::objects::ObjectImpl::instance_finalize(instanc= e.as_mut()); + } + } + }; + + let expanded =3D quote! { + #obj_impl_unsafe + + #ctors + }; + TokenStream::from(expanded) +} diff --git a/rust/qemu-api-macros/src/symbols.rs b/rust/qemu-api-macros/src= /symbols.rs new file mode 100644 index 0000000000000000000000000000000000000000..f73768d228ed2b4d478c18336db= 56cb11e70f012 --- /dev/null +++ b/rust/qemu-api-macros/src/symbols.rs @@ -0,0 +1,55 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::fmt; +use syn::{Ident, Path}; + +#[derive(Copy, Clone, Debug)] +pub struct Symbol(&'static str); + +pub const DEVICE: Symbol =3D Symbol("device"); +pub const NAME: Symbol =3D Symbol("name"); +pub const CATEGORY: Symbol =3D Symbol("category"); +pub const CLASS_NAME: Symbol =3D Symbol("class_name"); +pub const CLASS_NAME_OVERRIDE: Symbol =3D Symbol("class_name_override"); +pub const QDEV_PROP: Symbol =3D Symbol("qdev_prop"); +pub const MIGRATEABLE: Symbol =3D Symbol("migrateable"); +pub const PROPERTIES: Symbol =3D Symbol("properties"); +pub const PROPERTY: Symbol =3D Symbol("property"); + +impl PartialEq for Ident { + fn eq(&self, word: &Symbol) -> bool { + self =3D=3D word.0 + } +} + +impl<'a> PartialEq for &'a Ident { + fn eq(&self, word: &Symbol) -> bool { + *self =3D=3D word.0 + } +} + +impl PartialEq for Path { + fn eq(&self, word: &Symbol) -> bool { + self.is_ident(word.0) + } +} + +impl<'a> PartialEq for &'a Path { + fn eq(&self, word: &Symbol) -> bool { + self.is_ident(word.0) + } +} + +impl PartialEq for Symbol { + fn eq(&self, ident: &Ident) -> bool { + ident =3D=3D self.0 + } +} + +impl fmt::Display for Symbol { + fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { + self.0.fmt(fmt) + } +} diff --git a/rust/qemu-api-macros/src/utilities.rs b/rust/qemu-api-macros/s= rc/utilities.rs new file mode 100644 index 0000000000000000000000000000000000000000..bd8776539aa0bb3bcaa023bd88d= 962efe1431746 --- /dev/null +++ b/rust/qemu-api-macros/src/utilities.rs @@ -0,0 +1,152 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use syn::{parenthesized, token, Data, DeriveInput, LitInt}; + +#[derive(Default)] +pub enum Abi { + #[default] + Rust, + C, + Transparent, + Other(String), +} + +#[derive(Default)] +pub struct Repr { + pub abi: Abi, + /// whether the attribute was declared in the definition. + pub present: bool, + pub align: Option, + pub packed: Option, +} + +impl core::fmt::Display for Repr { + fn fmt(&self, fmt: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(fmt, "repr(")?; + match &self.abi { + Abi::C =3D> write!(fmt, "C")?, + Abi::Rust =3D> write!(fmt, "Rust")?, + Abi::Transparent =3D> write!(fmt, "transparent")?, + Abi::Other(s) =3D> write!(fmt, "{}", s)?, + } + if self.align.is_some() || self.packed.is_some() { + write!(fmt, ", ")?; + if let Some(v) =3D self.align { + write!(fmt, "align({})", v)?; + if self.packed.is_some() { + write!(fmt, ", ")?; + } + } + match self.packed { + Some(1) =3D> write!(fmt, "packed")?, + Some(n) =3D> write!(fmt, "packed({})", n)?, + None =3D> {} + } + } + write!(fmt, ")") + } +} + +impl Repr { + pub fn detect_repr(attrs: &[syn::Attribute]) -> Self { + let mut repr =3D Self::default(); + + // We don't validate the repr attribute; if it's invalid rustc wil= l complain + // anyway. + for attr in attrs { + if attr.path().is_ident("repr") { + repr.present =3D true; + if let Err(err) =3D attr.parse_nested_meta(|meta| { + // #[repr(C)] + if meta.path.is_ident("C") { + repr.abi =3D Abi::C; + return Ok(()); + } + + // #[repr(Rust)] + if meta.path.is_ident("Rust") { + repr.abi =3D Abi::Rust; + return Ok(()); + } + + // #[repr(transparent)] + if meta.path.is_ident("transparent") { + repr.abi =3D Abi::Transparent; + return Ok(()); + } + + // #[repr(align(N))] + if meta.path.is_ident("align") { + let content; + parenthesized!(content in meta.input); + let lit: LitInt =3D content.parse()?; + let n: usize =3D lit.base10_parse()?; + repr.align =3D Some(n); + return Ok(()); + } + + // #[repr(packed)] or #[repr(packed(N))], omitted N me= ans 1 + if meta.path.is_ident("packed") { + repr.packed =3D if meta.input.peek(token::Paren) { + let content; + parenthesized!(content in meta.input); + let lit: LitInt =3D content.parse()?; + let n: usize =3D lit.base10_parse()?; + Some(n) + } else { + Some(1) + }; + return Ok(()); + } + + if let Some(i) =3D meta.path.get_ident() { + repr.abi =3D Abi::Other(i.to_string()); + } + + Err(meta.error("unrecognized repr")) + }) { + println!("Error while processing Object Derive macro: = {}", err); + } + } + } + repr + } +} + +pub fn assert_is_repr_c_struct(input: &DeriveInput, derive_macro: &'static= str) { + if !matches!(input.data, Data::Struct(_)) { + panic!( + "`{}` derive macro can only be used with structs, and `{}` is = {}", + derive_macro, + input.ident, + match input.data { + Data::Struct(_) =3D> unreachable!(), + Data::Enum(_) =3D> "enum", + Data::Union(_) =3D> "union", + } + ); + } + match Repr::detect_repr(&input.attrs) { + Repr { abi: Abi::C, .. } =3D> { /* all good */ } + Repr { + abi: Abi::Transparent, + .. + } =3D> { + // If the data layout is `transparent`, then its representation + // depends on the ABI of the wrapped type. We cannot + // detect it here. + } + other =3D> { + panic!( + "`{}` derive macro can only be used with repr(C) structs, = and `{}` {} \ + {}\nHint: Annotate the struct with `#[repr(C)]`.", + derive_macro, + input.ident, + if other.present { "is" } else { "defaults to" }, + other, + ); + } + } +} diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build index c72d34b607df1da90185046f4d9c26b3cb6c6523..0bd70b59afcc005251135802897= 954789b068e6e 100644 --- a/rust/qemu-api/meson.build +++ b/rust/qemu-api/meson.build @@ -3,8 +3,7 @@ _qemu_api_rs =3D static_library( structured_sources( [ 'src/lib.rs', - 'src/definitions.rs', - 'src/device_class.rs', + 'src/objects.rs', ], {'.' : bindings_rs}, ), diff --git a/rust/qemu-api/src/definitions.rs b/rust/qemu-api/src/definitio= ns.rs deleted file mode 100644 index 60bd3f8aaa65ae131a9c4628a96ac52f590d7324..000000000000000000000000000= 0000000000000 --- a/rust/qemu-api/src/definitions.rs +++ /dev/null @@ -1,97 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -//! Definitions required by QEMU when registering a device. - -use ::core::ffi::{c_void, CStr}; - -use crate::bindings::{Object, ObjectClass, TypeInfo}; - -/// Trait a type must implement to be registered with QEMU. -pub trait ObjectImpl { - type Class; - const TYPE_INFO: TypeInfo; - const TYPE_NAME: &'static CStr; - const PARENT_TYPE_NAME: Option<&'static CStr>; - const ABSTRACT: bool; - const INSTANCE_INIT: Option; - const INSTANCE_POST_INIT: Option; - const INSTANCE_FINALIZE: Option; -} - -pub trait Class { - const CLASS_INIT: Option; - const CLASS_BASE_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c_void), - >; -} - -#[macro_export] -macro_rules! module_init { - ($func:expr, $type:expr) =3D> { - #[used] - #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] - #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] - #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] - pub static LOAD_MODULE: extern "C" fn() =3D { - extern "C" fn __load() { - unsafe { - $crate::bindings::register_module_init(Some($func), $t= ype); - } - } - - __load - }; - }; - (qom: $func:ident =3D> $body:block) =3D> { - // NOTE: To have custom identifiers for the ctor func we need to e= ither supply - // them directly as a macro argument or create them with a proc ma= cro. - #[used] - #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] - #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] - #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] - pub static LOAD_MODULE: extern "C" fn() =3D { - extern "C" fn __load() { - #[no_mangle] - unsafe extern "C" fn $func() { - $body - } - - unsafe { - $crate::bindings::register_module_init( - Some($func), - $crate::bindings::module_init_type::MODULE_INIT_QO= M, - ); - } - } - - __load - }; - }; -} - -#[macro_export] -macro_rules! type_info { - ($t:ty) =3D> { - $crate::bindings::TypeInfo { - name: <$t as $crate::definitions::ObjectImpl>::TYPE_NAME.as_pt= r(), - parent: if let Some(pname) =3D <$t as $crate::definitions::Obj= ectImpl>::PARENT_TYPE_NAME { - pname.as_ptr() - } else { - ::core::ptr::null_mut() - }, - instance_size: ::core::mem::size_of::<$t>() as $crate::binding= s::size_t, - instance_align: ::core::mem::align_of::<$t>() as $crate::bindi= ngs::size_t, - instance_init: <$t as $crate::definitions::ObjectImpl>::INSTAN= CE_INIT, - instance_post_init: <$t as $crate::definitions::ObjectImpl>::I= NSTANCE_POST_INIT, - instance_finalize: <$t as $crate::definitions::ObjectImpl>::IN= STANCE_FINALIZE, - abstract_: <$t as $crate::definitions::ObjectImpl>::ABSTRACT, - class_size: ::core::mem::size_of::<<$t as $crate::definitions= ::ObjectImpl>::Class>() as $crate::bindings::size_t, - class_init: <<$t as $crate::definitions::ObjectImpl>::Class as= $crate::definitions::Class>::CLASS_INIT, - class_base_init: <<$t as $crate::definitions::ObjectImpl>::Cla= ss as $crate::definitions::Class>::CLASS_BASE_INIT, - class_data: ::core::ptr::null_mut(), - interfaces: ::core::ptr::null_mut(), - }; - } -} diff --git a/rust/qemu-api/src/device_class.rs b/rust/qemu-api/src/device_c= lass.rs deleted file mode 100644 index 1ea95beb78dbf8637d9af1edb668d51411a9ac33..000000000000000000000000000= 0000000000000 --- a/rust/qemu-api/src/device_class.rs +++ /dev/null @@ -1,128 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -use std::sync::OnceLock; - -use crate::bindings::Property; - -#[macro_export] -macro_rules! device_class_init { - ($func:ident, props =3D> $props:ident, realize_fn =3D> $realize_fn:exp= r, legacy_reset_fn =3D> $legacy_reset_fn:expr, vmsd =3D> $vmsd:ident$(,)*) = =3D> { - #[no_mangle] - pub unsafe extern "C" fn $func( - klass: *mut $crate::bindings::ObjectClass, - _: *mut ::core::ffi::c_void, - ) { - let mut dc =3D - ::core::ptr::NonNull::new(klass.cast::<$crate::bindings::D= eviceClass>()).unwrap(); - dc.as_mut().realize =3D $realize_fn; - dc.as_mut().vmsd =3D &$vmsd; - $crate::bindings::device_class_set_legacy_reset(dc.as_mut(), $= legacy_reset_fn); - $crate::bindings::device_class_set_props(dc.as_mut(), $props.a= s_mut_ptr()); - } - }; -} - -#[macro_export] -macro_rules! define_property { - ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr, default = =3D $defval:expr$(,)*) =3D> { - $crate::bindings::Property { - name: { - #[used] - static _TEMP: &::core::ffi::CStr =3D $name; - _TEMP.as_ptr() - }, - info: $prop, - offset: ::core::mem::offset_of!($state, $field) - .try_into() - .expect("Could not fit offset value to type"), - bitnr: 0, - bitmask: 0, - set_default: true, - defval: $crate::bindings::Property__bindgen_ty_1 { u: $defval.= into() }, - arrayoffset: 0, - arrayinfo: ::core::ptr::null(), - arrayfieldsize: 0, - link_type: ::core::ptr::null(), - } - }; - ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr$(,)*) =3D>= { - $crate::bindings::Property { - name: { - #[used] - static _TEMP: &::core::ffi::CStr =3D $name; - _TEMP.as_ptr() - }, - info: $prop, - offset: ::core::mem::offset_of!($state, $field) - .try_into() - .expect("Could not fit offset value to type"), - bitnr: 0, - bitmask: 0, - set_default: false, - defval: $crate::bindings::Property__bindgen_ty_1 { i: 0 }, - arrayoffset: 0, - arrayinfo: ::core::ptr::null(), - arrayfieldsize: 0, - link_type: ::core::ptr::null(), - } - }; -} - -#[repr(C)] -pub struct Properties(pub OnceLock<[Property; N]>, pub fn(= ) -> [Property; N]); - -impl Properties { - pub fn as_mut_ptr(&mut self) -> *mut Property { - _ =3D self.0.get_or_init(self.1); - self.0.get_mut().unwrap().as_mut_ptr() - } -} - -#[macro_export] -macro_rules! declare_properties { - ($ident:ident, $($prop:expr),*$(,)*) =3D> { - - const fn _calc_prop_len() -> usize { - let mut len =3D 1; - $({ - _ =3D stringify!($prop); - len +=3D 1; - })* - len - } - const PROP_LEN: usize =3D _calc_prop_len(); - - fn _make_properties() -> [$crate::bindings::Property; PROP_LEN] { - [ - $($prop),*, - unsafe { ::core::mem::MaybeUninit::<$crate::bindings::= Property>::zeroed().assume_init() }, - ] - } - - #[no_mangle] - pub static mut $ident: $crate::device_class::Properties = =3D $crate::device_class::Properties(::std::sync::OnceLock::new(), _make_pr= operties); - }; -} - -#[macro_export] -macro_rules! vm_state_description { - ($(#[$outer:meta])* - $name:ident, - $(name: $vname:expr,)* - $(unmigratable: $um_val:expr,)* - ) =3D> { - #[used] - $(#[$outer])* - pub static $name: $crate::bindings::VMStateDescription =3D $crate:= :bindings::VMStateDescription { - $(name: { - #[used] - static VMSTATE_NAME: &::core::ffi::CStr =3D $vname; - $vname.as_ptr() - },)* - unmigratable: true, - ..unsafe { ::core::mem::MaybeUninit::<$crate::bindings::VMStat= eDescription>::zeroed().assume_init() } - }; - } -} diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs index e72fb4b4bb13b0982f828b6ec1cfe848c3e6bdf0..b94adc15288cdc62de7679988f5= 49ebd80f895d7 100644 --- a/rust/qemu-api/src/lib.rs +++ b/rust/qemu-api/src/lib.rs @@ -27,11 +27,7 @@ unsafe impl Sync for bindings::Property {} unsafe impl Sync for bindings::TypeInfo {} unsafe impl Sync for bindings::VMStateDescription {} =20 -pub mod definitions; -pub mod device_class; - -#[cfg(test)] -mod tests; +pub mod objects; =20 use std::alloc::{GlobalAlloc, Layout}; =20 diff --git a/rust/qemu-api/src/objects.rs b/rust/qemu-api/src/objects.rs new file mode 100644 index 0000000000000000000000000000000000000000..5c6762023ed6914f9c6b7dd16a5= e07f778c2d4fa --- /dev/null +++ b/rust/qemu-api/src/objects.rs @@ -0,0 +1,90 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Implementation traits for QEMU objects, devices. + +use ::core::ffi::{c_int, c_void, CStr}; + +use crate::bindings::{DeviceState, Error, MigrationPriority, Object, Objec= tClass, TypeInfo}; + +/// Trait a type must implement to be registered with QEMU. +pub trait ObjectImpl { + type Class: ClassImpl; + const TYPE_NAME: &'static CStr; + const PARENT_TYPE_NAME: Option<&'static CStr>; + const ABSTRACT: bool; + + unsafe fn instance_init(&mut self) {} + fn instance_post_init(&mut self) {} + fn instance_finalize(&mut self) {} +} + +/// The `extern`/`unsafe` analogue of [`ObjectImpl`]; it is used internall= y by `#[derive(Object)]` +/// and should not be implemented manually. +pub unsafe trait ObjectImplUnsafe { + const TYPE_INFO: TypeInfo; + + const INSTANCE_INIT: Option; + const INSTANCE_POST_INIT: Option; + const INSTANCE_FINALIZE: Option; +} + +/// Methods for QOM class types. +pub trait ClassImpl { + type Object: ObjectImpl; + + unsafe fn class_init(&mut self, _data: *mut core::ffi::c_void) {} + unsafe fn class_base_init(&mut self, _data: *mut core::ffi::c_void) {} +} + +/// The `extern`/`unsafe` analogue of [`ClassImpl`]; it is used internally= by `#[derive(Object)]` +/// and should not be implemented manually. +pub unsafe trait ClassImplUnsafe { + const CLASS_INIT: Option; + const CLASS_BASE_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c_void), + >; +} + +/// Implementation methods for device types. +pub trait DeviceImpl: ObjectImpl { + fn realize(&mut self) {} + fn reset(&mut self) {} +} + +/// The `extern`/`unsafe` analogue of [`DeviceImpl`]; it is used internall= y by `#[derive(Device)]` +/// and should not be implemented manually. +pub unsafe trait DeviceImplUnsafe { + const REALIZE: Option; + const RESET: Option; +} + +/// Constant metadata and implementation methods for types with device mig= ration state. +pub trait Migrateable: DeviceImplUnsafe { + const NAME: Option<&'static CStr> =3D None; + const UNMIGRATABLE: bool =3D true; + const EARLY_SETUP: bool =3D false; + const VERSION_ID: c_int =3D 1; + const MINIMUM_VERSION_ID: c_int =3D 1; + const PRIORITY: MigrationPriority =3D MigrationPriority::MIG_PRI_DEFAU= LT; + + unsafe fn pre_load(&mut self) -> c_int { + 0 + } + unsafe fn post_load(&mut self, _version_id: c_int) -> c_int { + 0 + } + unsafe fn pre_save(&mut self) -> c_int { + 0 + } + unsafe fn post_save(&mut self) -> c_int { + 0 + } + unsafe fn needed(&mut self) -> bool { + false + } + unsafe fn dev_unplug_pending(&mut self) -> bool { + false + } +} diff --git a/rust/qemu-api/src/tests.rs b/rust/qemu-api/src/tests.rs deleted file mode 100644 index df54edbd4e27e7d2aafc243355d1826d52497c21..000000000000000000000000000= 0000000000000 --- a/rust/qemu-api/src/tests.rs +++ /dev/null @@ -1,49 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis -// SPDX-License-Identifier: GPL-2.0-or-later - -use crate::{ - bindings::*, declare_properties, define_property, device_class_init, v= m_state_description, -}; - -#[test] -fn test_device_decl_macros() { - // Test that macros can compile. - vm_state_description! { - VMSTATE, - name: c"name", - unmigratable: true, - } - - #[repr(C)] - pub struct DummyState { - pub char_backend: CharBackend, - pub migrate_clock: bool, - } - - declare_properties! { - DUMMY_PROPERTIES, - define_property!( - c"chardev", - DummyState, - char_backend, - unsafe { &qdev_prop_chr }, - CharBackend - ), - define_property!( - c"migrate-clk", - DummyState, - migrate_clock, - unsafe { &qdev_prop_bool }, - bool - ), - } - - device_class_init! { - dummy_class_init, - props =3D> DUMMY_PROPERTIES, - realize_fn =3D> None, - reset_fn =3D> None, - vmsd =3D> VMSTATE, - } -} diff --git a/subprojects/packagefiles/syn-2-rs/meson.build b/subprojects/pa= ckagefiles/syn-2-rs/meson.build index a53335f3092e06723039513a1bf5a0d35b4afcd7..9f56ce1c24d0ff86e9b0146b0f8= 2c37ac868fab7 100644 --- a/subprojects/packagefiles/syn-2-rs/meson.build +++ b/subprojects/packagefiles/syn-2-rs/meson.build @@ -24,6 +24,7 @@ _syn_rs =3D static_library( '--cfg', 'feature=3D"printing"', '--cfg', 'feature=3D"clone-impls"', '--cfg', 'feature=3D"proc-macro"', + '--cfg', 'feature=3D"extra-traits"', ], dependencies: [ quote_dep, --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778717; cv=none; d=zohomail.com; s=zohoarc; b=i5spGlYFUYHQ1UjnKay6vJigpH0kfw5pxeIvIu6hgXvOkWGJMaK9TmCbkNCL6RtBr5JUazKeDRXeIfN7jMD4SjTJnB40ltYXFSQBQ5M5AVtVdE2ILcdp+MtnyjbF7cQ1DiT1ahyVNwype+lrowemTREzWiD3SthE1cHib8FPnHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778717; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2iGhVX3FthgCu9tCSB5ib+BmYJD5e1RgHUcKSHCgOOI=; b=bOPEE42Yo9an6soTMyXqs+IpVGpx7ScWpT4UeFkF4VkginJk67O9u3czO7mx/TexW7cygXq1ZauyJMnrSQ63qKZcfzpIx05/s4z1rPe+liu5G0QzOeYohsvX3zOQvo97US9ZRMVXeahzxbLXNTNusabAfkq0TLEWxDdJt4J6ftw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778717262335.9086770749336; Thu, 24 Oct 2024 07:05:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRW-0007Bf-RB; Thu, 24 Oct 2024 10:04:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRC-00078q-EU for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:50 -0400 Received: from mail-lj1-x235.google.com ([2a00:1450:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yR8-0003wK-OK for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:42 -0400 Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2fb51e00c05so14154581fa.0 for ; Thu, 24 Oct 2024 07:03:37 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778718289116600 This commit adds support for declaring migration state to device models in Rust. This is done through different but related parts: - The Device derive macro gains new attributes `vmstate_fields` and `vmstate_subsections`. This allows the device declaration to include the vmstate fields directly at the struct definition. - a new qemu_api module, `vmstate` was added. There a bunch of Rust macros declared there that are equivalent in spirit to the C macros declared in include/migration/vmstate.h. For example the Rust of equivalent of the C macro: VMSTATE_UINT32(field_name, struct_name) is: vmstate_uint32!(field_name, StructName) This breathtaking development now allows us to not have to define VMStateDescription ourselves but split the notion of migration to two parts: - A Migrateable trait that allows a type to define version_ids, name, priority, override methods like pre_load, post_load, pre_save etc. - Define the actual vmstate fields and subsections through the Device derive macro right there with the struct definition: ------------------------ >8 ------------------------ #[repr(C)] #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::Device)] +#[device( + class_name_override =3D PL011Class, + vmstate_fields =3D vmstate_fields!{ + vmstate_unused!(u32::BITS as u64), + vmstate_uint32!(flags, PL011State), + vmstate_uint32!(line_control, PL011State), + vmstate_uint32!(receive_status_error_clear, PL011State), + vmstate_uint32!(control, PL011State), + vmstate_uint32!(dmacr, PL011State), + vmstate_uint32!(int_enabled, PL011State), + vmstate_uint32!(int_level, PL011State), + vmstate_uint32_array!(read_fifo, PL011State, PL011_FIFO_DEPTH), + vmstate_uint32!(ilpr, PL011State), + vmstate_uint32!(ibrd, PL011State), + vmstate_uint32!(fbrd, PL011State), + vmstate_uint32!(ifl, PL011State), + vmstate_int32!(read_pos, PL011State), + vmstate_int32!(read_count, PL011State), + vmstate_int32!(read_trigger, PL011State), + }, + vmstate_subsections =3D vmstate_subsections!{ + VMSTATE_PL011_CLOCK + } +)] /// PL011 Device Model in QEMU pub struct PL011State { pub parent_obj: SysBusDevice, ------------------------ >8 ------------------------ Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 92 +++++++- rust/qemu-api-macros/src/device.rs | 111 +++------- rust/qemu-api-macros/src/lib.rs | 1 + rust/qemu-api-macros/src/symbols.rs | 2 + rust/qemu-api-macros/src/vmstate.rs | 113 ++++++++++ rust/qemu-api/meson.build | 1 + rust/qemu-api/src/lib.rs | 3 + rust/qemu-api/src/vmstate.rs | 403 ++++++++++++++++++++++++++++++++= ++++ 8 files changed, 637 insertions(+), 89 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index c469877b1ca70dd1a02e3a2449c65ad3e57c93ae..57dc37dadef631fbccfa3049a3d= 8701b4e62b5b3 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -10,6 +10,8 @@ use qemu_api::{ bindings::{self, *}, objects::*, + vmstate_clock, vmstate_fields, vmstate_int32, vmstate_subsections, vms= tate_uint32, + vmstate_uint32_array, vmstate_unused, }; =20 use crate::{ @@ -20,14 +22,74 @@ =20 static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; =20 +/// Integer Baud Rate Divider, `UARTIBRD` +const IBRD_MASK: u32 =3D 0x3f; + +/// Fractional Baud Rate Divider, `UARTFBRD` +const FBRD_MASK: u32 =3D 0xffff; + const DATA_BREAK: u32 =3D 1 << 10; =20 /// QEMU sourced constant. pub const PL011_FIFO_DEPTH: usize =3D 16_usize; =20 +#[no_mangle] +extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool { + unsafe { + debug_assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().migrate_clock + } +} + +qemu_api::vmstate_description! { + /// Migration subsection for [`PL011State`] clock. + pub static VMSTATE_PL011_CLOCK: VMStateDescription =3D VMStateDescript= ion { + name: c"pl011/clock", + unmigratable: false, + early_setup: false, + version_id: 1, + minimum_version_id: 1, + priority: MigrationPriority::MIG_PRI_DEFAULT, + pre_load: None, + post_load: None, + pre_save: None, + post_save: None, + needed: Some(pl011_clock_needed), + dev_unplug_pending: None, + fields: vmstate_fields!{ + vmstate_clock!(clock, PL011State), + }, + subsections: ::core::ptr::null(), + }; +} + #[repr(C)] #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::Device)] -#[device(class_name_override =3D PL011Class)] +#[device( + class_name_override =3D PL011Class, + vmstate_fields =3D vmstate_fields!{ + vmstate_unused!(u32::BITS as u64), + vmstate_uint32!(flags, PL011State), + vmstate_uint32!(line_control, PL011State), + vmstate_uint32!(receive_status_error_clear, PL011State), + vmstate_uint32!(control, PL011State), + vmstate_uint32!(dmacr, PL011State), + vmstate_uint32!(int_enabled, PL011State), + vmstate_uint32!(int_level, PL011State), + vmstate_uint32_array!(read_fifo, PL011State, PL011_FIFO_DEPTH), + vmstate_uint32!(ilpr, PL011State), + vmstate_uint32!(ibrd, PL011State), + vmstate_uint32!(fbrd, PL011State), + vmstate_uint32!(ifl, PL011State), + vmstate_int32!(read_pos, PL011State), + vmstate_int32!(read_count, PL011State), + vmstate_int32!(read_trigger, PL011State), + }, + vmstate_subsections =3D vmstate_subsections!{ + VMSTATE_PL011_CLOCK + } +)] /// PL011 Device Model in QEMU pub struct PL011State { pub parent_obj: SysBusDevice, @@ -165,7 +227,33 @@ fn reset(&mut self) { } } =20 -impl qemu_api::objects::Migrateable for PL011State {} +impl qemu_api::objects::Migrateable for PL011State { + const NAME: Option<&'static CStr> =3D Some(c"pl011"); + const UNMIGRATABLE: bool =3D false; + const VERSION_ID: c_int =3D 2; + const MINIMUM_VERSION_ID: c_int =3D 2; + + unsafe fn post_load(&mut self, _version_id: c_int) -> c_int { + /* Sanity-check input state */ + if self.read_pos >=3D self.read_fifo.len() || self.read_count > se= lf.read_fifo.len() { + return -1; + } + + if !self.fifo_enabled() && self.read_count > 0 && self.read_pos > = 0 { + // Older versions of PL011 didn't ensure that the single + // character in the FIFO in FIFO-disabled mode is in + // element 0 of the array; convert to follow the current + // code's assumptions. + self.read_fifo[0] =3D self.read_fifo[self.read_pos]; + self.read_pos =3D 0; + } + + self.ibrd &=3D IBRD_MASK; + self.fbrd &=3D FBRD_MASK; + + 0 + } +} =20 #[used] pub static CLK_NAME: &CStr =3D c"clk"; diff --git a/rust/qemu-api-macros/src/device.rs b/rust/qemu-api-macros/src/= device.rs index 3b965576a065601cd5c97d5ab6a2501f96d16a61..a666c64087715b9dc0d9ebe33f2= b22d965381c64 100644 --- a/rust/qemu-api-macros/src/device.rs +++ b/rust/qemu-api-macros/src/device.rs @@ -10,11 +10,13 @@ }; use syn::{parse_macro_input, DeriveInput}; =20 -use crate::{symbols::*, utilities::*}; +use crate::{symbols::*, utilities::*, vmstate}; =20 #[derive(Debug, Default)] struct DeriveContainer { category: Option, + vmstate_fields: Option, + vmstate_subsections: Option, class_name: Option, class_name_override: Option, } @@ -27,6 +29,8 @@ fn parse(input: ParseStream) -> Result { assert_eq!(DEVICE, bracketed.parse::()?); let mut retval =3D Self { category: None, + vmstate_fields: None, + vmstate_subsections: None, class_name: None, class_name_override: None, }; @@ -54,6 +58,20 @@ fn parse(input: ParseStream) -> Result { let lit: syn::LitStr =3D content.parse()?; let path: syn::Path =3D lit.parse()?; retval.category =3D Some(path); + } else if value =3D=3D VMSTATE_FIELDS { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.vmstate_fields.is_some() { + panic!("{} can only be used at most once", VMSTATE_FIE= LDS); + } + let expr: syn::Expr =3D content.parse()?; + retval.vmstate_fields =3D Some(expr); + } else if value =3D=3D VMSTATE_SUBSECTIONS { + let _: syn::Token![=3D] =3D content.parse()?; + if retval.vmstate_subsections.is_some() { + panic!("{} can only be used at most once", VMSTATE_SUB= SECTIONS); + } + let expr: syn::Expr =3D content.parse()?; + retval.vmstate_subsections =3D Some(expr); } else { panic!("unrecognized token `{}`", value); } @@ -272,7 +290,11 @@ pub struct #class_name { let class_base_init_fn =3D format_ident!("__{}_class_base_init_generat= ed", class_name); =20 let (vmsd, vmsd_impl) =3D { - let (i, vmsd) =3D make_vmstate(name); + let (i, vmsd) =3D vmstate::make_vmstate( + name, + derive_container.vmstate_fields, + derive_container.vmstate_subsections, + ); (quote! { &#i }, vmsd) }; let category =3D if let Some(category) =3D derive_container.category { @@ -346,88 +368,3 @@ unsafe impl ::qemu_api::objects::ClassImplUnsafe for #= class_name { #vmsd_impl } } - -fn make_vmstate(name: &syn::Ident) -> (syn::Ident, proc_macro2::TokenStrea= m) { - let vmstate_description_ident =3D format_ident!("__VMSTATE_{}", name); - - let pre_load =3D format_ident!("__{}_pre_load_generated", name); - let post_load =3D format_ident!("__{}_post_load_generated", name); - let pre_save =3D format_ident!("__{}_pre_save_generated", name); - let post_save =3D format_ident!("__{}_post_save_generated", name); - let needed =3D format_ident!("__{}_needed_generated", name); - let dev_unplug_pending =3D format_ident!("__{}_dev_unplug_pending_gene= rated", name); - - let migrateable_fish =3D quote! {<#name as ::qemu_api::objects::Migrat= eable>}; - let vmstate_description =3D quote! { - #[used] - #[allow(non_upper_case_globals)] - pub static #vmstate_description_ident: ::qemu_api::bindings::VMSta= teDescription =3D ::qemu_api::bindings::VMStateDescription { - name: if let Some(name) =3D #migrateable_fish::NAME { - name.as_ptr() - } else { - <#name as ::qemu_api::objects::ObjectImplUnsafe>::TYPE_INF= O.name - }, - unmigratable: #migrateable_fish::UNMIGRATABLE, - early_setup: #migrateable_fish::EARLY_SETUP, - version_id: #migrateable_fish::VERSION_ID, - minimum_version_id: #migrateable_fish::MINIMUM_VERSION_ID, - priority: #migrateable_fish::PRIORITY, - pre_load: Some(#pre_load), - post_load: Some(#post_load), - pre_save: Some(#pre_save), - post_save: Some(#post_save), - needed: Some(#needed), - dev_unplug_pending: Some(#dev_unplug_pending), - fields: ::core::ptr::null(), - subsections: ::core::ptr::null(), - }; - - #[no_mangle] - pub unsafe extern "C" fn #pre_load(opaque: *mut ::core::ffi::c_voi= d) -> ::core::ffi::c_int { - let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); - unsafe { - ::qemu_api::objects::Migrateable::pre_load(instance.as_mut= ()) - } - } - #[no_mangle] - pub unsafe extern "C" fn #post_load(opaque: *mut ::core::ffi::c_vo= id, version_id: core::ffi::c_int) -> ::core::ffi::c_int { - let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); - unsafe { - ::qemu_api::objects::Migrateable::post_load(instance.as_mu= t(), version_id) - } - } - #[no_mangle] - pub unsafe extern "C" fn #pre_save(opaque: *mut ::core::ffi::c_voi= d) -> ::core::ffi::c_int { - let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); - unsafe { - ::qemu_api::objects::Migrateable::pre_save(instance.as_mut= ()) - } - } - #[no_mangle] - pub unsafe extern "C" fn #post_save(opaque: *mut ::core::ffi::c_vo= id) -> ::core::ffi::c_int { - let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); - unsafe { - ::qemu_api::objects::Migrateable::post_save(instance.as_mu= t()) - } - } - #[no_mangle] - pub unsafe extern "C" fn #needed(opaque: *mut ::core::ffi::c_void)= -> bool { - let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); - unsafe { - ::qemu_api::objects::Migrateable::needed(instance.as_mut()) - } - } - #[no_mangle] - pub unsafe extern "C" fn #dev_unplug_pending(opaque: *mut ::core::= ffi::c_void) -> bool { - let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); - unsafe { - ::qemu_api::objects::Migrateable::dev_unplug_pending(insta= nce.as_mut()) - } - } - }; - - let expanded =3D quote! { - #vmstate_description - }; - (vmstate_description_ident, expanded) -} diff --git a/rust/qemu-api-macros/src/lib.rs b/rust/qemu-api-macros/src/lib= .rs index 7753a853fae72fc87e6dc642cf076c6d0c736345..7b5c0c044da879241b05bba75ed= cb17b498e5d5a 100644 --- a/rust/qemu-api-macros/src/lib.rs +++ b/rust/qemu-api-macros/src/lib.rs @@ -10,6 +10,7 @@ mod object; mod symbols; mod utilities; +mod vmstate; =20 #[proc_macro_derive(Object)] pub fn derive_object(input: TokenStream) -> TokenStream { diff --git a/rust/qemu-api-macros/src/symbols.rs b/rust/qemu-api-macros/src= /symbols.rs index f73768d228ed2b4d478c18336db56cb11e70f012..79c242cf069d5de1dd0cd61b2a5= c7814564af47e 100644 --- a/rust/qemu-api-macros/src/symbols.rs +++ b/rust/qemu-api-macros/src/symbols.rs @@ -15,6 +15,8 @@ pub const CLASS_NAME_OVERRIDE: Symbol =3D Symbol("class_name_override"); pub const QDEV_PROP: Symbol =3D Symbol("qdev_prop"); pub const MIGRATEABLE: Symbol =3D Symbol("migrateable"); +pub const VMSTATE_FIELDS: Symbol =3D Symbol("vmstate_fields"); +pub const VMSTATE_SUBSECTIONS: Symbol =3D Symbol("vmstate_subsections"); pub const PROPERTIES: Symbol =3D Symbol("properties"); pub const PROPERTY: Symbol =3D Symbol("property"); =20 diff --git a/rust/qemu-api-macros/src/vmstate.rs b/rust/qemu-api-macros/src= /vmstate.rs new file mode 100644 index 0000000000000000000000000000000000000000..2d72bf13b5acc861fac0814d749= 762ddb76824d5 --- /dev/null +++ b/rust/qemu-api-macros/src/vmstate.rs @@ -0,0 +1,113 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use quote::{format_ident, quote}; + +pub fn make_vmstate( + name: &syn::Ident, + vmstate_fields: Option, + vmstate_subsections: Option, +) -> (syn::Ident, proc_macro2::TokenStream) { + let vmstate_description_ident =3D format_ident!("__VMSTATE_{}", name); + + let pre_load =3D format_ident!("__{}_pre_load_generated", name); + let post_load =3D format_ident!("__{}_post_load_generated", name); + let pre_save =3D format_ident!("__{}_pre_save_generated", name); + let post_save =3D format_ident!("__{}_post_save_generated", name); + let needed =3D format_ident!("__{}_needed_generated", name); + let dev_unplug_pending =3D format_ident!("__{}_dev_unplug_pending_gene= rated", name); + + let migrateable_fish =3D quote! {<#name as ::qemu_api::objects::Migrat= eable>}; + let vmstate_fields =3D if let Some(fields) =3D vmstate_fields { + quote! { + #fields + } + } else { + quote! { + ::core::ptr::null() + } + }; + let vmstate_subsections =3D if let Some(subsections) =3D vmstate_subse= ctions { + quote! { + #subsections + } + } else { + quote! { + ::core::ptr::null() + } + }; + + let vmstate_description =3D quote! { + #[used] + #[allow(non_upper_case_globals)] + pub static #vmstate_description_ident: ::qemu_api::bindings::VMSta= teDescription =3D ::qemu_api::bindings::VMStateDescription { + name: if let Some(name) =3D #migrateable_fish::NAME { + name.as_ptr() + } else { + <#name as ::qemu_api::objects::ObjectImplUnsafe>::TYPE_INF= O.name + }, + unmigratable: #migrateable_fish::UNMIGRATABLE, + early_setup: #migrateable_fish::EARLY_SETUP, + version_id: #migrateable_fish::VERSION_ID, + minimum_version_id: #migrateable_fish::MINIMUM_VERSION_ID, + priority: #migrateable_fish::PRIORITY, + pre_load: Some(#pre_load), + post_load: Some(#post_load), + pre_save: Some(#pre_save), + post_save: Some(#post_save), + needed: Some(#needed), + dev_unplug_pending: Some(#dev_unplug_pending), + fields: #vmstate_fields, + subsections: #vmstate_subsections, + }; + + #[no_mangle] + pub unsafe extern "C" fn #pre_load(opaque: *mut ::core::ffi::c_voi= d) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::pre_load(instance.as_mut= ()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #post_load(opaque: *mut ::core::ffi::c_vo= id, version_id: core::ffi::c_int) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::post_load(instance.as_mu= t(), version_id) + } + } + #[no_mangle] + pub unsafe extern "C" fn #pre_save(opaque: *mut ::core::ffi::c_voi= d) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::pre_save(instance.as_mut= ()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #post_save(opaque: *mut ::core::ffi::c_vo= id) -> ::core::ffi::c_int { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::post_save(instance.as_mu= t()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #needed(opaque: *mut ::core::ffi::c_void)= -> bool { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::needed(instance.as_mut()) + } + } + #[no_mangle] + pub unsafe extern "C" fn #dev_unplug_pending(opaque: *mut ::core::= ffi::c_void) -> bool { + let mut instance =3D NonNull::new(opaque.cast::<#name>()).expe= ct(concat!("Expected opaque to be a non-null pointer of type ", stringify!(= #name), "::Object")); + unsafe { + ::qemu_api::objects::Migrateable::dev_unplug_pending(insta= nce.as_mut()) + } + } + }; + + let expanded =3D quote! { + #vmstate_description + }; + (vmstate_description_ident, expanded) +} diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build index 0bd70b59afcc005251135802897954789b068e6e..11984abb878bef18be3c819f61d= a24ce1405ea59 100644 --- a/rust/qemu-api/meson.build +++ b/rust/qemu-api/meson.build @@ -4,6 +4,7 @@ _qemu_api_rs =3D static_library( [ 'src/lib.rs', 'src/objects.rs', + 'src/vmstate.rs', ], {'.' : bindings_rs}, ), diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs index b94adc15288cdc62de7679988f549ebd80f895d7..d276adfb6622eee6e42494e089e= 1f20b0b5cdf08 100644 --- a/rust/qemu-api/src/lib.rs +++ b/rust/qemu-api/src/lib.rs @@ -26,8 +26,11 @@ unsafe impl Send for bindings::Property {} unsafe impl Sync for bindings::Property {} unsafe impl Sync for bindings::TypeInfo {} unsafe impl Sync for bindings::VMStateDescription {} +unsafe impl Sync for bindings::VMStateField {} +unsafe impl Sync for bindings::VMStateInfo {} =20 pub mod objects; +pub mod vmstate; =20 use std::alloc::{GlobalAlloc, Layout}; =20 diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs new file mode 100644 index 0000000000000000000000000000000000000000..4478febc9ac2768cca3e638ebae= 27b042edb1bf2 --- /dev/null +++ b/rust/qemu-api/src/vmstate.rs @@ -0,0 +1,403 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Helper macros to declare migration state for device models. +//! +//! Some macros are direct equivalents to the C macros declared in `includ= e/migration/vmstate.h` +//! while [`vmstate_description`], [`vmstate_subsections`] and [`vmstate_f= ields`] are meant to be +//! used when declaring a device model state struct with the [`Device`](qe= mu_api_macros::Device) +//! `Derive` macro. + +#[doc(alias =3D "VMSTATE_UNUSED_BUFFER")] +#[macro_export] +macro_rules! vmstate_unused_buffer { + ($field_exists_fn:expr, $version_id:expr, $size:expr) =3D> {{ + $crate::bindings::VMStateField { + name: c"unused".as_ptr(), + err_hint: ::core::ptr::null(), + offset: 0, + size: $size, + start: 0, + num: 0, + num_offset: 0, + size_offset: 0, + info: unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate= _info_unused_buffer) }, + flags: VMStateFlags::VMS_BUFFER, + vmsd: ::core::ptr::null(), + version_id: $version_id, + struct_version_id: 0, + field_exists: $field_exists_fn, + } + }}; +} + +#[doc(alias =3D "VMSTATE_UNUSED_V")] +#[macro_export] +macro_rules! vmstate_unused_v { + ($version_id:expr, $size:expr) =3D> {{ + $crate::vmstate_unused_buffer!(None, $version_id, $size) + }}; +} + +#[doc(alias =3D "VMSTATE_UNUSED")] +#[macro_export] +macro_rules! vmstate_unused { + ($size:expr) =3D> {{ + $crate::vmstate_unused_v!(0, $size) + }}; +} + +#[doc(alias =3D "VMSTATE_SINGLE_TEST")] +#[macro_export] +macro_rules! vmstate_single_test { + ($field_name:ident, $struct_name:ty, $field_exists_fn:expr, $version_i= d:expr, $info:block, $size:expr) =3D> {{ + $crate::bindings::VMStateField { + name: ::core::concat!(::core::stringify!($field_name), 0) + .as_bytes() + .as_ptr() as *const ::core::ffi::c_char, + err_hint: ::core::ptr::null(), + offset: ::core::mem::offset_of!($struct_name, $field_name) as = _, + size: $size, + start: 0, + num: 0, + num_offset: 0, + size_offset: 0, + info: $info, + flags: VMStateFlags::VMS_SINGLE, + vmsd: ::core::ptr::null(), + version_id: $version_id, + struct_version_id: 0, + field_exists: $field_exists_fn, + } + }}; +} + +#[doc(alias =3D "VMSTATE_SINGLE")] +#[macro_export] +macro_rules! vmstate_single { + ($field_name:ident, $struct_name:ty, $version_id:expr, $info:block, $s= ize:expr) =3D> {{ + $crate::vmstate_single_test!($field_name, $struct_name, None, $ver= sion_id, $info, $size) + }}; +} + +#[doc(alias =3D "VMSTATE_UINT32_V")] +#[macro_export] +macro_rules! vmstate_uint32_v { + ($field_name:ident, $struct_name:ty, $version_id:expr) =3D> {{ + $crate::vmstate_single!( + $field_name, + $struct_name, + $version_id, + { unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate_inf= o_uint32) } }, + u32::BITS as u64 + ) + }}; +} + +#[doc(alias =3D "VMSTATE_UINT32")] +#[macro_export] +macro_rules! vmstate_uint32 { + ($field_name:ident, $struct_name:ty) =3D> {{ + $crate::vmstate_uint32_v!($field_name, $struct_name, 0) + }}; +} + +#[doc(alias =3D "VMSTATE_INT32_V")] +#[macro_export] +macro_rules! vmstate_int32_v { + ($field_name:ident, $struct_name:ty, $version_id:expr) =3D> {{ + $crate::vmstate_single!( + $field_name, + $struct_name, + $version_id, + { unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate_inf= o_int32) } }, + i32::BITS as u64 + ) + }}; +} + +#[doc(alias =3D "VMSTATE_INT32")] +#[macro_export] +macro_rules! vmstate_int32 { + ($field_name:ident, $struct_name:ty) =3D> {{ + $crate::vmstate_int32_v!($field_name, $struct_name, 0) + }}; +} + +#[doc(alias =3D "VMSTATE_ARRAY")] +#[macro_export] +macro_rules! vmstate_array { + ($field_name:ident, $struct_name:ty, $length:expr, $version_id:expr, $= info:block, $size:expr) =3D> {{ + $crate::bindings::VMStateField { + name: ::core::concat!(::core::stringify!($field_name), 0) + .as_bytes() + .as_ptr() as *const ::core::ffi::c_char, + err_hint: ::core::ptr::null(), + offset: ::core::mem::offset_of!($struct_name, $field_name) as = _, + size: $size, + start: 0, + num: $length as _, + num_offset: 0, + size_offset: 0, + info: $info, + flags: VMStateFlags::VMS_ARRAY, + vmsd: ::core::ptr::null(), + version_id: $version_id, + struct_version_id: 0, + field_exists: None, + } + }}; +} + +#[doc(alias =3D "VMSTATE_UINT32_ARRAY_V")] +#[macro_export] +macro_rules! vmstate_uint32_array_v { + ($field_name:ident, $struct_name:ty, $length:expr, $version_id:expr) = =3D> {{ + $crate::vmstate_array!( + $field_name, + $struct_name, + $length, + $version_id, + { unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate_inf= o_uint32) } }, + u32::BITS as u64 + ) + }}; +} + +#[doc(alias =3D "VMSTATE_UINT32_ARRAY")] +#[macro_export] +macro_rules! vmstate_uint32_array { + ($field_name:ident, $struct_name:ty, $length:expr) =3D> {{ + $crate::vmstate_uint32_array_v!($field_name, $struct_name, $length= , 0) + }}; +} + +#[doc(alias =3D "VMSTATE_STRUCT_POINTER_V")] +#[macro_export] +macro_rules! vmstate_struct_pointer_v { + ($field_name:ident, $struct_name:ty, $version_id:expr, $vmsd:expr, $ty= pe:ty) =3D> {{ + $crate::bindings::VMStateField { + name: ::core::concat!(::core::stringify!($field_name), 0) + .as_bytes() + .as_ptr() as *const ::core::ffi::c_char, + err_hint: ::core::ptr::null(), + offset: ::core::mem::offset_of!($struct_name, $field_name) as = _, + size: ::core::mem::size_of::<*const $type>() as _, + start: 0, + num: 0, + num_offset: 0, + size_offset: 0, + info: ::core::ptr::null(), + flags: VMStateFlags(VMStateFlags::VMS_STRUCT.0 | VMStateFlags:= :VMS_POINTER.0), + vmsd: $vmsd, + version_id: $version_id, + struct_version_id: 0, + field_exists: None, + } + }}; +} + +#[doc(alias =3D "VMSTATE_ARRAY_OF_POINTER")] +#[macro_export] +macro_rules! vmstate_array_of_pointer { + ($field_name:ident, $struct_name:ty, $num:expr, $version_id:expr, $inf= o:expr, $type:ty) =3D> {{ + $crate::bindings::VMStateField { + name: ::core::concat!(::core::stringify!($field_name), 0) + .as_bytes() + .as_ptr() as *const ::core::ffi::c_char, + version_id: $version_id, + num: $num, + info: $info, + size: ::core::mem::size_of::<*const $type>() as _, + flags: VMStateFlags(VMStateFlags::VMS_ARRAY.0 | VMStateFlags::= VMS_ARRAY_OF_POINTER.0), + offset: ::core::mem::offset_of!($struct_name, $field_name) as = _, + err_hint: ::core::ptr::null(), + start: 0, + num_offset: 0, + size_offset: 0, + vmsd: ::core::ptr::null(), + struct_version_id: 0, + field_exists: None, + } + }}; +} + +#[doc(alias =3D "VMSTATE_ARRAY_OF_POINTER_TO_STRUCT")] +#[macro_export] +macro_rules! vmstate_array_of_pointer_to_struct { + ($field_name:ident, $struct_name:ty, $num:expr, $version_id:expr, $vms= d:expr, $type:ty) =3D> {{ + $crate::bindings::VMStateField { + name: ::core::concat!(::core::stringify!($field_name), 0) + .as_bytes() + .as_ptr() as *const ::core::ffi::c_char, + version_id: $version_id, + num: $num, + vmsd: $vmsd, + size: ::core::mem::size_of::<*const $type>() as _, + flags: VMStateFlags( + VMStateFlags::VMS_ARRAY.0 + | VMStateFlags::VMS_STRUCT.0 + | VMStateFlags::VMS_ARRAY_OF_POINTER.0, + ), + offset: ::core::mem::offset_of!($struct_name, $field_name) as = _, + err_hint: ::core::ptr::null(), + start: 0, + num_offset: 0, + size_offset: 0, + vmsd: ::core::ptr::null(), + struct_version_id: 0, + field_exists: None, + } + }}; +} + +#[doc(alias =3D "VMSTATE_CLOCK_V")] +#[macro_export] +macro_rules! vmstate_clock_v { + ($field_name:ident, $struct_name:ty, $version_id:expr) =3D> {{ + $crate::vmstate_struct_pointer_v!( + $field_name, + $struct_name, + $version_id, + { unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate_clo= ck) } }, + $crate::bindings::Clock + ) + }}; +} + +#[doc(alias =3D "VMSTATE_CLOCK")] +#[macro_export] +macro_rules! vmstate_clock { + ($field_name:ident, $struct_name:ty) =3D> {{ + $crate::vmstate_clock_v!($field_name, $struct_name, 0) + }}; +} + +#[doc(alias =3D "VMSTATE_ARRAY_CLOCK_V")] +#[macro_export] +macro_rules! vmstate_array_clock_v { + ($field_name:ident, $struct_name:ty, $num:expr, $version_id:expr) =3D>= {{ + $crate::vmstate_array_of_pointer_to_struct!( + $field_name, + $struct_name, + $num, + $version_id, + { unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate_clo= ck) } }, + $crate::bindings::Clock + ) + }}; +} + +#[doc(alias =3D "VMSTATE_ARRAY_CLOCK")] +#[macro_export] +macro_rules! vmstate_array_clock { + ($field_name:ident, $struct_name:ty, $num:expr) =3D> {{ + $crate::vmstate_array_clock_v!($field_name, $struct_name, $name, 0) + }}; +} + +/// Helper macro to declare a list of +/// ([`VMStateField`](`crate::bindings::VMStateField`)) into a static and = return a +/// pointer to the array of values it created. +#[macro_export] +macro_rules! vmstate_fields { + ($($field:expr),*$(,)*) =3D> {{ + #[used] + static _FIELDS: &[$crate::bindings::VMStateField] =3D &[ + $($field),*, + $crate::bindings::VMStateField { + name: ::core::ptr::null(), + err_hint: ::core::ptr::null(), + offset: 0, + size: 0, + start: 0, + num: 0, + num_offset: 0, + size_offset: 0, + info: ::core::ptr::null(), + flags: VMStateFlags::VMS_END, + vmsd: ::core::ptr::null(), + version_id: 0, + struct_version_id: 0, + field_exists: None, + } + ]; + _FIELDS.as_ptr() + }} +} + +/// A transparent wrapper type for the `subsections` field of +/// [`VMStateDescription`](crate::bindings::VMStateDescription). +/// +/// This is necessary to be able to declare subsection descriptions as sta= tics, because the only +/// way to implement `Sync` for a foreign type (and `*const` pointers are = foreign types in Rust) is +/// to create a wrapper struct and `unsafe impl Sync` for it. +/// +/// This struct is used in the [`vmstate_subsections`] macro implementatio= n. +#[repr(transparent)] +pub struct VMStateSubsectionsWrapper(pub &'static [*const crate::bindings:= :VMStateDescription]); + +unsafe impl Sync for VMStateSubsectionsWrapper {} + +/// Helper macro to declare a list of subsections +/// ([`VMStateDescription`](`crate::bindings::VMStateDescription`)) into a= static and return a +/// pointer to the array of pointers it created. +#[macro_export] +macro_rules! vmstate_subsections { + ($($subsection:expr),*$(,)*) =3D> {{ + #[used] + static _SUBSECTIONS: $crate::vmstate::VMStateSubsectionsWrapper = =3D $crate::vmstate::VMStateSubsectionsWrapper(&[ + $({ + #[used] + static _SUBSECTION: $crate::bindings::VMStateDescription = =3D $subsection; + ::core::ptr::addr_of!(_SUBSECTION) + }),*, + ::core::ptr::null() + ]); + _SUBSECTIONS.0.as_ptr() + }} +} + +/// Thin macro to declare a valid [`VMStateDescription`](`crate::bindings:= :VMStateDescription`) +/// static. +#[macro_export] +macro_rules! vmstate_description { + ($(#[$outer:meta])* + pub static $name:ident: VMStateDescription =3D VMStateDescription { + name: $vname:expr, + unmigratable: $um_val:expr, + early_setup: $early_setup:expr, + version_id: $version_id:expr, + minimum_version_id: $minimum_version_id:expr, + priority: $priority:expr, + pre_load: $pre_load_fn:expr, + post_load: $post_load_fn:expr, + pre_save: $pre_save_fn:expr, + post_save: $post_save_fn:expr, + needed: $needed_fn:expr, + dev_unplug_pending: $dev_unplug_pending_fn:expr, + fields: $fields:expr, + subsections: $subsections:expr$(,)* + }; + ) =3D> { + #[used] + $(#[$outer])* + pub static $name: $crate::bindings::VMStateDescription =3D $cr= ate::bindings::VMStateDescription { + name: ::core::ffi::CStr::as_ptr($vname), + unmigratable: $um_val, + early_setup: $early_setup, + version_id: $version_id, + minimum_version_id: $minimum_version_id, + priority: $priority, + pre_load: None, + post_load: None, + pre_save: None, + post_save: None, + needed: None, + dev_unplug_pending: None, + fields: $fields, + subsections: $subsections, + }; + } +} --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778734; cv=none; d=zohomail.com; s=zohoarc; b=eyxQfKlTeiAarC2vTw0PPy+dhNu+CP05p1p4vVlZDavn5WUSWe65RDhbhSNL5mx8NDtxBruAELu/QlW85KwssUi6XbROjZW0jGImFwYDnizbLJBMbnf2KpP8yaBK+Msx/VxSZ+oPe8KqyIllURA1C+zubtECC1aiVUTuJ7SRsjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778734; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hbU95iGb43ykjR6uVl1fMgZcXOfT8jfUmlrwgLmbMOQ=; b=Enb1wanTRCjcX9ySoyDHiQkSO4it93YCtVQyJYlgxzsLtt23YmQaXe6HMVF2AOkCQzDdmomeO4E1mAOEZmY/K5HqZDzziM3KLYgsCMooC3Hqe8g/fqM+XylnJZWTlImrlgZlKOLutkj70/RDEUO8I8whysZ966NObPrCHyd1RFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778734666350.98072046130017; Thu, 24 Oct 2024 07:05:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRY-0007CZ-56; Thu, 24 Oct 2024 10:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRD-00078r-JN for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:53 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yRC-0003ww-55 for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:43 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a9a0ef5179dso120046166b.1 for ; Thu, 24 Oct 2024 07:03:41 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778736113116600 We do not need to have CLK_NAME public nor a static. No functional change. Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 57dc37dadef631fbccfa3049a3d8701b4e62b5b3..115786f9fa7f03c16cd44462cb7= df5623ba3a6d7 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -152,6 +152,8 @@ impl ObjectImpl for PL011State { /// location/instance. All its fields are expected to hold unitialized /// values with the sole exception of `parent_obj`. unsafe fn instance_init(&mut self) { + const CLK_NAME: &CStr =3D c"clk"; + let dev =3D addr_of_mut!(*self).cast::(); // SAFETY: // @@ -255,9 +257,6 @@ unsafe fn post_load(&mut self, _version_id: c_int) -> c= _int { } } =20 -#[used] -pub static CLK_NAME: &CStr =3D c"clk"; - impl PL011State { pub fn read( &mut self, --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778768; cv=none; d=zohomail.com; s=zohoarc; b=eAQZ3BC23uRjeei2bBikM3Vtf9R+zNqGTr6ujdg0/5iEO+7R5sCPwpu52kjynSxXlV0zrlmDUehBPDzjxPKFKEF8IyG0vVNmiAf0eifr8UX8v8o4GcQfVFx+R9NBSWVWRCJDwEp+KHUphHuV7NtrU8oDltfEcNzwz2hAi6gt9pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778768; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WITWBs3eKYPfFgEanUhD+BoP6AjEmCFyXtxJHZOASQo=; b=RDk0VZVAWGJb5rkndFN47QUCJVGtBmlMmbhpfA+14hF4bTKfgzLKhonndIYBAMHPSVPoK7ng4djIKLTtbfSUtzDvxjw/X5A2hcvUgsLauT6Pz9ReegVGNCtlnruHmK/Jwow/QbzDYAqI9opiSresZQ8KRbS1EKB4oRRlJARQU0k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778768887379.8323501074889; Thu, 24 Oct 2024 07:06:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRX-0007CO-E7; Thu, 24 Oct 2024 10:04:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRH-000792-6V for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:53 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yRF-0003xB-Hs for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:46 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-a99ebb390a5so383654866b.1 for ; Thu, 24 Oct 2024 07:03:45 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778770390116600 Add a device specialization for the Luminary UART device. This commit adds a DeviceId enum that utilizes the Index trait to return different bytes depending on what device id the UART has (Arm -default- or Luminary) Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 59 ++++++++++++++++++++++++++++++++++++= ++-- rust/hw/char/pl011/src/lib.rs | 1 + 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 115786f9fa7f03c16cd44462cb7df5623ba3a6d7..3aa055dee4b10866a624505a9d0= 5ef1ab8182dce 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -20,8 +20,6 @@ RegisterOffset, }; =20 -static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; - /// Integer Baud Rate Divider, `UARTIBRD` const IBRD_MASK: u32 =3D 0x3f; =20 @@ -64,6 +62,29 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) ->= bool { }; } =20 +#[derive(Clone, Copy, Debug)] +enum DeviceId { + #[allow(dead_code)] + Arm =3D 0, + Luminary, +} + +impl std::ops::Index for DeviceId { + type Output =3D c_uchar; + + fn index(&self, idx: hwaddr) -> &Self::Output { + match self { + Self::Arm =3D> &Self::PL011_ID_ARM[idx as usize], + Self::Luminary =3D> &Self::PL011_ID_LUMINARY[idx as usize], + } + } +} + +impl DeviceId { + const PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0x= f0, 0x05, 0xb1]; + const PL011_ID_LUMINARY: [c_uchar; 8] =3D [0x11, 0x00, 0x18, 0x01, 0x0= d, 0xf0, 0x05, 0xb1]; +} + #[repr(C)] #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::Device)] #[device( @@ -134,6 +155,8 @@ pub struct PL011State { #[doc(alias =3D "migrate_clk")] #[property(name =3D c"migrate-clk", qdev_prop =3D qdev_prop_bool)] pub migrate_clock: bool, + /// The byte string that identifies the device. + device_id: DeviceId, } =20 impl ObjectImpl for PL011State { @@ -267,7 +290,7 @@ pub fn read( =20 std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset= ) { Err(v) if (0x3f8..0x400).contains(&v) =3D> { - u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) + u64::from(self.device_id[(offset - 0xfe0) >> 2]) } Err(_) =3D> { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); @@ -660,3 +683,33 @@ pub fn update(&self) { dev } } + +#[repr(C)] +#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::Device)] +/// PL011 Luminary device model. +pub struct PL011Luminary { + parent_obj: PL011State, +} + +impl ObjectImpl for PL011Luminary { + type Class =3D PL011LuminaryClass; + + const TYPE_NAME: &'static CStr =3D crate::TYPE_PL011_LUMINARY; + const PARENT_TYPE_NAME: Option<&'static CStr> =3D Some(crate::TYPE_PL0= 11); + const ABSTRACT: bool =3D false; + + /// Initializes a pre-allocated, unitialized instance of `PL011Luminar= y`. + /// + /// # Safety + /// + /// `self` must point to a correctly sized and aligned location for the + /// `PL011Luminary` type. It must not be called more than once on the = same + /// location/instance. All its fields are expected to hold unitialized + /// values with the sole exception of `parent_obj`. + unsafe fn instance_init(&mut self) { + self.parent_obj.device_id =3D DeviceId::Luminary; + } +} + +impl DeviceImpl for PL011Luminary {} +impl qemu_api::objects::Migrateable for PL011Luminary {} diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index f4d9cce4b01f605cfcbec7ea87c8b2009d77ee52..5516e018b4bfebe5175c515e5aa= 4598f54b39dfc 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -45,6 +45,7 @@ pub mod memory_ops; =20 pub const TYPE_PL011: &::core::ffi::CStr =3D c"pl011"; +pub const TYPE_PL011_LUMINARY: &::core::ffi::CStr =3D c"pl011_luminary"; =20 /// Offset of each register from the base memory address of the device. /// --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778766; cv=none; d=zohomail.com; s=zohoarc; b=Q84bLVF9+FHyeQ82c5UdUSBhAMc8S4bj8+glfMIMNiXPobKJO49uF4d5Sb6cQppkz1H8T6gdwSIeGYRmQJaVN3kT34BUN6XA1tZHvpX2egtkCJuf9kqLvHqHKNH9WGknM6wj5Xhogkr54e1KrUXNXGnBQNhjnPwal2rigx7ao3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778766; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KCn73+YkWwVjQeZCOwMpqD8LHrnSQOeaidvNNKE/Tbg=; b=hc8Eu+nCLwA/Jh+SMV4I20btV1ZjrjPAxw18oIuvK4dn7HvT6uYbiJftMY5pETMS2v7JfKOIbNm9kzg6c32gOh0XiMqJVeeWAFna/xY9wo057hnFN8Q6KUpkFub3NQHYwwS19dUIyT4X0tWpj7E9ADkWrtHA6JOk2mL1TkvV3JI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778766404732.8487505797077; Thu, 24 Oct 2024 07:06:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRW-0007Bb-Au; Thu, 24 Oct 2024 10:04:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRJ-00079A-G9 for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:53 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yRH-0003xI-PG for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:49 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-a9a0ec0a94fso122898066b.1 for ; Thu, 24 Oct 2024 07:03:47 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778768423116600 extern "C" callbacks in instance_init() do not need to be public. Move them to local function scope instead. No functional change. Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 104 +++++++++++++++++++----------------= ---- 1 file changed, 50 insertions(+), 54 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 3aa055dee4b10866a624505a9d05ef1ab8182dce..75399fa6352916fa9cc24164af0= ea2e20fe29399 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -219,6 +219,56 @@ unsafe fn instance_init(&mut self) { =20 impl DeviceImpl for PL011State { fn realize(&mut self) { + /// # Safety + /// + /// We expect the FFI user of this function to pass a valid pointe= r, that has + /// the same size as [`PL011State`]. We also expect the device is + /// readable/writeable from one thread at any time. + unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_i= nt { + unsafe { + debug_assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().can_receive().into() + } + } + /// # Safety + /// + /// We expect the FFI user of this function to pass a valid pointe= r, that has + /// the same size as [`PL011State`]. We also expect the device is + /// readable/writeable from one thread at any time. + /// + /// The buffer and size arguments must also be valid. + unsafe extern "C" fn pl011_receive( + opaque: *mut core::ffi::c_void, + buf: *const u8, + size: core::ffi::c_int, + ) { + unsafe { + debug_assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + if state.as_ref().loopback_enabled() { + return; + } + if size > 0 { + debug_assert!(!buf.is_null()); + state.as_mut().put_fifo(c_uint::from(buf.read_volatile= ())) + } + } + } + + /// # Safety + /// + /// We expect the FFI user of this function to pass a valid pointe= r, that has + /// the same size as [`PL011State`]. We also expect the device is + /// readable/writeable from one thread at any time. + unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, e= vent: QEMUChrEvent) { + unsafe { + debug_assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().event(event) + } + } + // SAFETY: self.char_backend has the correct size and alignment fo= r a // CharBackend object, and its callbacks are of the correct types. unsafe { @@ -611,60 +661,6 @@ pub fn update(&self) { =20 /// # Safety /// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { - unsafe { - debug_assert!(!opaque.is_null()); - let state =3D NonNull::new_unchecked(opaque.cast::()); - state.as_ref().can_receive().into() - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -/// -/// The buffer and size arguments must also be valid. -#[no_mangle] -pub unsafe extern "C" fn pl011_receive( - opaque: *mut core::ffi::c_void, - buf: *const u8, - size: core::ffi::c_int, -) { - unsafe { - debug_assert!(!opaque.is_null()); - let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); - if state.as_ref().loopback_enabled() { - return; - } - if size > 0 { - debug_assert!(!buf.is_null()); - state.as_mut().put_fifo(c_uint::from(buf.read_volatile())) - } - } -} - -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer, that = has -/// the same size as [`PL011State`]. We also expect the device is -/// readable/writeable from one thread at any time. -#[no_mangle] -pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { - unsafe { - debug_assert!(!opaque.is_null()); - let mut state =3D NonNull::new_unchecked(opaque.cast::= ()); - state.as_mut().event(event) - } -} - -/// # Safety -/// /// We expect the FFI user of this function to pass a valid pointer for `c= hr`. #[no_mangle] pub unsafe extern "C" fn pl011_create( --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778741; cv=none; d=zohomail.com; s=zohoarc; b=IjHv1eV7ZXL/zs+oc9SEoPc3TdsUGO5s16bVrJxy/jdNmXzqf/nUoeJD72b8oTk+cMQi3PzAPFaXhZHT88xcEZvNRycFPCm2djjNKXYKb/DOv7r3jbb0Rbc522FdSqvysILZSJsWd5GD+2T7INYoCzoz4auQEr0IM6QkG9x8p28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778741; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+f2xVZQLPWqFbFB+BWu+Obk2BX5gjbKzI8BtdihEOhw=; b=ILLyio81itNevVSai2HBXhdVlutPn1gK8Dw2bSTlfn2LskaM3E+Xd6j8m3ZuRsPBFpDBaBldQ2TZCp2+VAFKzrdWipzsuyIUbVE7osY+JLFHq+Jz1pN5/FQhrpZE6W5/vySRm3XalDr9eEkfMW0VCzZbvRRyUCPi4UxPjOgdayA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778741425321.47510917992804; Thu, 24 Oct 2024 07:05:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRY-0007CS-2H; Thu, 24 Oct 2024 10:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRK-00079O-4O for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:53 -0400 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yRI-0003xP-JE for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:49 -0400 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-539f58c68c5so1719229e87.3 for ; Thu, 24 Oct 2024 07:03:48 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778744141116600 This code juxtaposed what should be happening according to the C device model but is not needed now that this has been reviewed (I hope) and its validity checked against what the C device does (I hope, again). No functional change. Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 75399fa6352916fa9cc24164af0ea2e20fe29399..cf1964fecdfd6d9dae3378890aa= 8b515a1ddc036 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -347,7 +347,6 @@ pub fn read( 0 } Ok(DR) =3D> { - // s->flags &=3D ~PL011_FLAG_RXFF; self.flags.set_receive_fifo_full(false); let c =3D self.read_fifo[self.read_pos]; if self.read_count > 0 { @@ -355,11 +354,9 @@ pub fn read( self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); } if self.read_count =3D=3D 0 { - // self.flags |=3D PL011_FLAG_RXFE; self.flags.set_receive_fifo_empty(true); } if self.read_count + 1 =3D=3D self.read_trigger { - //self.int_level &=3D ~ INT_RX; self.int_level &=3D !registers::INT_RX; } // Update error bits. @@ -529,13 +526,6 @@ fn loopback_mdmctrl(&mut self) { * dealt with here. */ =20 - //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | - // PL011_FLAG_DSR | PL011_FLAG_CTS); - //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; - //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; - //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; - //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; - // self.flags.set_ring_indicator(self.control.out_2()); self.flags.set_data_carrier_detect(self.control.out_1()); self.flags.set_clear_to_send(self.control.request_to_send()); @@ -546,10 +536,6 @@ fn loopback_mdmctrl(&mut self) { let mut il =3D self.int_level; =20 il &=3D !Interrupt::MS; - //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; - //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; - //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; - //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; =20 if self.flags.data_set_ready() { il |=3D Interrupt::DSR as u32; @@ -622,10 +608,8 @@ pub fn put_fifo(&mut self, value: c_uint) { let slot =3D (self.read_pos + self.read_count) & (depth - 1); self.read_fifo[slot] =3D value; self.read_count +=3D 1; - // s->flags &=3D ~PL011_FLAG_RXFE; self.flags.set_receive_fifo_empty(false); if self.read_count =3D=3D depth { - //s->flags |=3D PL011_FLAG_RXFF; self.flags.set_receive_fifo_full(true); } =20 --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778739; cv=none; d=zohomail.com; s=zohoarc; b=VW76VJhGcIzAgGsY9H637CPMAkkcm7QBa6Xv2ubt8HIMrJ10yeia+LDLKviK6/Qe87Ewb8DTHMwdCTYegwZEQQCboJZld1cY6YF2keyuUTVYnGr6EtPxIW2FMGLuo/naDoe7eh/0eNh6Eid8+74CgI37abFC3CU+xZzwghK8+yk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778739; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8Qgg42N8SuToqImklsCIv0xNcAbCllJIjfd+s7ENKDE=; b=feq9tVI6yTW92wdu8Iam6uT/I86V2mL2fpYNv5mHJ3eFll8KZ5q+FLLYyFB9ByHOM7oTMCPAccG8esT8ANbbr+EmuaFf81gRpFB4mV41s7+vwBrURW9Gl7nz7lqcCVcUO7DmqBDq4tEtQSZ8zGSSOZ6ciLAq6xaN3Kj9MoG5k1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778739305741.8420076552999; Thu, 24 Oct 2024 07:05:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRZ-0007Cu-Ep; Thu, 24 Oct 2024 10:04:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRO-00079u-Ca for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:04:00 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yRL-0003xf-TO for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:03:53 -0400 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a9acafdb745so196016766b.0 for ; Thu, 24 Oct 2024 07:03:51 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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=20 /// Integer Baud Rate Divider, `UARTIBRD` -const IBRD_MASK: u32 =3D 0x3f; +const IBRD_MASK: u32 =3D 0xffff; =20 /// Fractional Baud Rate Divider, `UARTFBRD` -const FBRD_MASK: u32 =3D 0xffff; +const FBRD_MASK: u32 =3D 0x3f; =20 const DATA_BREAK: u32 =3D 1 << 10; =20 --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778750; cv=none; d=zohomail.com; s=zohoarc; b=j6RDHrWpZI0R2UyFz5JasY7fxwacTEyRmV1SzpKcvgyqRs7nJIpiB/BPkOEbY/zmFVow1pYFoanFXNcYlLNBumv/q1QhvU06WV8NUp07qRIWJgrFvnJ+04vp6cBzFD2+7kFlwu6MvLQ1Okbxn+2jVj6okveHwxWBfxO6gOq3XXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778750; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778752286116600 Logging in QEMU is done by function-like C macros, which we cannot use directly from Rust with bindgen. This commit adds a new qemu_api module, `log`, that provides the following interfaces: - a `LogMask` enum type that uses the mask values from the generated bindings, and makes sure the rust enum variant names and values will match. - `LogMask` aliases `LogMask::GUEST_ERROR` and `LogMask::UNIMPLEMENTED` for convenience. - a private qemu_loglevel_mask() function, counterpart of `qemu_loglevel_mask` in `include/qemu/log-for-trace.h`, which we cannot use from bindgen since it's a static inline item. - public qemu_log(), qemu_log_mask() and qemu_log_mask_and_addr() functions that should act like the C equivalent: pub fn qemu_log_mask_and_addr(log_mask: LogMask, address: u64, str: &str); pub fn qemu_log_mask(log_mask: LogMask, str: &str); pub fn qemu_log(str: &str); It takes a 'static or allocated string slice as argument, but in the feature we will introduce better log macros in Rust that make use of Rust's format arguments. This is not really a bad compromise since generating a log item is not a hot path so allocating here is fine. Example usage will be: ```rust qemu_log_mask(LogMask::GUEST_ERROR, "device XYZ failed spectacularly"); qemu_log_mask( LogMask::UNIMPLEMENTED, &format!( "We haven't implemented this feature in {file}:{line} out of pure lazine= ss.", file =3D file!(), line =3D line!() ) ); ``` Signed-off-by: Manos Pitsidianakis --- rust/wrapper.h | 1 + rust/qemu-api/meson.build | 1 + rust/qemu-api/src/lib.rs | 1 + rust/qemu-api/src/log.rs | 140 ++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 143 insertions(+) diff --git a/rust/wrapper.h b/rust/wrapper.h index 77e40213efb686d23f6b768b78602e4337623280..8f76ef26f111d5e1f308268f445= 696acc7ddbfef 100644 --- a/rust/wrapper.h +++ b/rust/wrapper.h @@ -32,6 +32,7 @@ =20 #include "qemu/osdep.h" #include "qemu/module.h" +#include "qemu/log.h" #include "qemu-io.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build index 11984abb878bef18be3c819f61da24ce1405ea59..a82ff0d39a2263d15bda312aa0a= 2d46c77b2501f 100644 --- a/rust/qemu-api/meson.build +++ b/rust/qemu-api/meson.build @@ -3,6 +3,7 @@ _qemu_api_rs =3D static_library( structured_sources( [ 'src/lib.rs', + 'src/log.rs', 'src/objects.rs', 'src/vmstate.rs', ], diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs index d276adfb6622eee6e42494e089e1f20b0b5cdf08..c3eb464f66361ee2349e636c49e= 38d3a6b57ad97 100644 --- a/rust/qemu-api/src/lib.rs +++ b/rust/qemu-api/src/lib.rs @@ -29,6 +29,7 @@ unsafe impl Sync for bindings::VMStateDescription {} unsafe impl Sync for bindings::VMStateField {} unsafe impl Sync for bindings::VMStateInfo {} =20 +pub mod log; pub mod objects; pub mod vmstate; =20 diff --git a/rust/qemu-api/src/log.rs b/rust/qemu-api/src/log.rs new file mode 100644 index 0000000000000000000000000000000000000000..50525ac6b7f49786c2975843b7d= c70b91c18d5a0 --- /dev/null +++ b/rust/qemu-api/src/log.rs @@ -0,0 +1,140 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Logging functionality. +//! +//! This module provides: +//! +//! - a [`LogMask`] enum type that uses the mask values from the generated +//! bindings, and makes sures the rust enum variant names and values will +//! match. +//! - [`LogMask`] aliases [`LogMask::GUEST_ERROR`] and [`LogMask::UNIMPLEM= ENTED`] +//! for convenience. +//! - a private `qemu_loglevel_mask()` function, counterpart of +//! `qemu_loglevel_mask` in `include/qemu/log-for-trace.h`, which we +//! cannot use from bindgen since it's a `static inline` item. +//! - public [`qemu_log`], [`qemu_log_mask`] and [`qemu_log_mask_and_addr`= ] functions that act like +//! the C equivalents. +//! +//! # Examples +//! +//! ```rust +//! # use qemu_api::log::*; +//! # fn main() { +//! qemu_log_mask(LogMask::GUEST_ERROR, "device XYZ failed spectacularly"); +//! +//! qemu_log_mask( +//! LogMask::UNIMPLEMENTED, +//! &format!( +//! "We haven't implemented this feature in {file}:{line} out of pure l= aziness.", +//! file =3D file!(), +//! line =3D line!() +//! ) +//! ); +//! # } +//! ``` + +use crate::bindings; + +macro_rules! mask_variants { + ($(#[$outer:meta])* + pub enum $name:ident { + $( + $(#[$attrs:meta])* + $symbol:ident + ),*$(,)* + }) =3D> { + $(#[$outer])* + pub enum $name { + $( + $(#[$attrs])* + $symbol =3D bindings::$symbol + ),* + } + }; +} + +mask_variants! { + /// A wrapper type for the various log mask `#defines` in the C code b= ase. + #[allow(non_camel_case_types)] + #[derive(Copy, Clone, Eq, PartialEq, Debug)] + #[repr(u32)] + pub enum LogMask { + CPU_LOG_TB_OUT_ASM, + CPU_LOG_TB_IN_ASM, + CPU_LOG_TB_OP, + CPU_LOG_TB_OP_OPT, + CPU_LOG_INT, + CPU_LOG_EXEC, + CPU_LOG_PCALL, + CPU_LOG_TB_CPU, + CPU_LOG_RESET, + LOG_UNIMP, + LOG_GUEST_ERROR, + CPU_LOG_MMU, + CPU_LOG_TB_NOCHAIN, + CPU_LOG_PAGE, + LOG_TRACE, + CPU_LOG_TB_OP_IND, + CPU_LOG_TB_FPU, + CPU_LOG_PLUGIN, + /// For user-mode strace logging. + LOG_STRACE, + LOG_PER_THREAD, + CPU_LOG_TB_VPU, + LOG_TB_OP_PLUGIN, + } +} + +impl LogMask { + /// Alias. + pub const GUEST_ERROR: Self =3D LogMask::LOG_GUEST_ERROR; + /// Alias. + pub const UNIMPLEMENTED: Self =3D LogMask::LOG_UNIMP; +} + +/// Returns `true` if a bit is set in the current loglevel mask. +/// +/// Counterpart of `qemu_loglevel_mask` in `include/qemu/log-for-trace.h`. +fn qemu_loglevel_mask(mask: LogMask) -> bool { + // SAFETY: This is an internal global variable. We only read from it a= nd reading invalid values + // is not a concern here. + let current_level =3D unsafe { bindings::qemu_loglevel }; + let mask =3D mask as ::core::ffi::c_int; + + (current_level & mask) !=3D 0 +} + +/// Log a message in QEMU's log, given a specific log mask. +pub fn qemu_log_mask(log_mask: LogMask, str: &str) { + if qemu_loglevel_mask(log_mask) { + qemu_log(str); + } +} + +/// Log a message in QEMU's log only if a bit is set on the current loglev= el mask and we are in the +/// address range we care about. +pub fn qemu_log_mask_and_addr(log_mask: LogMask, address: u64, str: &str) { + if qemu_loglevel_mask(log_mask) && { + // SAFETY: This function reads global variables/system state but a= n error here is not a + // concern. + unsafe { bindings::qemu_log_in_addr_range(address) } + } { + qemu_log(str); + } +} + +/// Log a message in QEMU's log, without a log mask. +pub fn qemu_log(str: &str) { + let Ok(cstr) =3D ::std::ffi::CString::new(str) else { + panic!( + "qemu_log_mask: Converting passed string {:?} to CString faile= d.", + str + ); + }; + // SAFETY: We're passing two valid CStr pointers. The second argument = for the variadic + // `qemu_log` function must be a `*const c_char` since the format spec= ifier is `%s`. + // Therefore this is a safe call. + unsafe { bindings::qemu_log(c"%s\n".as_ptr(), cstr.as_ptr()) }; +} --=20 2.45.2 From nobody Sat Nov 23 18:10:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1729778765; cv=none; d=zohomail.com; s=zohoarc; b=EfPsRhL/yqoRbY3XfZVnhE5tD4IKhyhHq/+CbSP4bQrZfWSzyvkAjnILikVu1SfpWEtqkAFvJ8ogZktAsAcstlGqgnRua7bJgV8ZUkQAEIGLleBbLGVlxOylqlyo7mgXrXCCZoV+3a9xcbqbjpLHEvFaA0MUzBwg51sni0oaLJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729778765; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=10FS6ba90SAfmfgqA/GoqytJLsUTvwlTO03Bcs2OdSo=; b=avkRMhqtj9inkP0hXFWLdBs6mVlk0xavz7h5ZntZ3YKbsIleuNO2uJypiTvlWDpCJ2D73lZ8rEStDotd8MgIOil0mIsyu61wgNTCuVxzQYwZmamEO2Eol0m7a/nuVL9akDFncNd3Bxq9U+V6wc+oru9vmdRvdOLUMBlRQ5y8Mp0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729778765418691.9575443660757; Thu, 24 Oct 2024 07:06:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3yRX-0007CN-DO; Thu, 24 Oct 2024 10:04:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3yRU-0007AI-EJ for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:04:01 -0400 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t3yRS-0003y1-Q1 for qemu-devel@nongnu.org; Thu, 24 Oct 2024 10:04:00 -0400 Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-539f58c68c5so1719687e87.3 for ; Thu, 24 Oct 2024 07:03:58 -0700 (PDT) Received: from [127.0.1.1] (adsl-113.37.6.2.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729778766316116600 Use the qemu_log_mask() functions introduced in previous commit to log errors like the C pl011 device does. Signed-off-by: Manos Pitsidianakis --- rust/hw/char/pl011/src/device.rs | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 6d1353dafc14bfe73703b5cff7e1ff7659de220e..57b38f44f90d74d0c1a94bb9144= eff08db94fadf 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -9,6 +9,7 @@ =20 use qemu_api::{ bindings::{self, *}, + log::*, objects::*, vmstate_clock, vmstate_fields, vmstate_int32, vmstate_subsections, vms= tate_uint32, vmstate_uint32_array, vmstate_unused, @@ -343,7 +344,14 @@ pub fn read( u64::from(self.device_id[(offset - 0xfe0) >> 2]) } Err(_) =3D> { - // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + qemu_log_mask( + LogMask::GUEST_ERROR, + &format!( + "pl011:{file}:{line}: Bad offset 0x{offset:x}", + file =3D file!(), + line =3D line!(), + ), + ); 0 } Ok(DR) =3D> { @@ -389,15 +397,30 @@ pub fn read( } =20 pub fn write(&mut self, offset: hwaddr, value: u64) { - // eprintln!("write offset {offset} value {value}"); use RegisterOffset::*; let value: u32 =3D value as u32; match RegisterOffset::try_from(offset) { Err(_bad_offset) =3D> { - eprintln!("write bad offset {offset} value {value}"); + qemu_log_mask( + LogMask::GUEST_ERROR, + &format!( + "pl011:{file}:{line}: Bad write offset 0x{offset:x= } of value 0x:{value:x}", + file =3D file!(), + line =3D line!(), + ), + ); } Ok(DR) =3D> { - // ??? Check if transmitter is enabled. + // Check if transmitter is enabled. + if !self.control.enable_uart() { + qemu_log_mask(LogMask::GUEST_ERROR, "PL011 data writte= n to disabled UART"); + } + if !self.control.enable_transmit() { + qemu_log_mask( + LogMask::GUEST_ERROR, + "PL011 data written to disabled TX UART", + ); + } let ch: u8 =3D value as u8; // XXX this blocks entire thread. Rewrite to use // qemu_chr_fe_write and background I/O callbacks @@ -474,8 +497,10 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { Ok(DMACR) =3D> { self.dmacr =3D value; if value & 3 > 0 { - // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); - eprintln!("pl011: DMA not implemented"); + qemu_log_mask( + LogMask::UNIMPLEMENTED, + "pl011: DMA functionality is not implemented", + ); } } } --=20 2.45.2