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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71ec13d73b1sm5438338b3a.105.2024.10.22.20.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 20:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729654476; x=1730259276; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n7/ieuf1Sfgsx1D01jF/RZfRXby31shptLEkFmD0Tv8=; b=Jceim6yXSyhrul6JHdyVSfBang0kEbuGU8RtWEqusM2PhQCv1/xbPxEQW0NQmpZS/V SIzHaC3yZgDV4940FJHhnSl9aF3ZLmx0MiPiKqHx692IL5YGhjAEqQQglnr6VpVhEKV0 mkoXEyK6RNRdw0t3IfFtsIIRdpDLFFOu8HPGXryx2ppDefKr8kjMTYrOT+xzn7bj/meu mBmcpj+lCAWeCWOuiwACdUCYLbvm3SNk6UAM+srXhCvohq0JhsE63KBrSnoaiWPVjP5z cy0T7JNj9mo41gb67mAu6B/82FM+G9bw1veglOz7jeLQqPtTxP1cJuBkc+WI60wkH5vZ h9sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729654476; x=1730259276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n7/ieuf1Sfgsx1D01jF/RZfRXby31shptLEkFmD0Tv8=; b=Y8MPZP9T9dugGLOAdLHCXLr+nFpq5b3KQsfLy1tkOeUHJ2Z3gDHsrPqgQTIimeAZNh AWhwX2qx1kcEmid++Nrr73KgBc4l0MrbC8bvjoUBhTXh5oKe9/YvRBpBa3AS3qyjF622 DKmvwtTAIGuPj8C2Nd717ssEC8Xk1Lb101o0mKsHWTMEnTtV7mIo9l9OqG31GeLpLmLs pALZ/YgVBoka5yR2vHbLo7SI5xH4jlPM1voH4ss9/4t9WeSw+c3MCaK7ji27wmWJDDVQ JTrJqxMdygAOmbaNd+l7FkqRseQYAAPEo9lhE8N/FCmwuYYnki5hT3ryh+itJ8ZRMof3 3InA== X-Gm-Message-State: AOJu0Yx+mKbKvYMO4McP+LeJwld3MlnC3ANRMNWYU5CNEQx0AOnYoUkn UYe5fwX6su/DSXHpGI++XMECKvY+erVTVnvj456duChCTEM700xrStV9By5vUE7pq1xU2oORM8m s X-Google-Smtp-Source: AGHT+IGrfgnNLWn1TmIN1hovvN3cZY/aHuE58iAK+ZQ/UDdLnN5FPuJOoyB07QKjgtH/8bAX+q05dg== X-Received: by 2002:a05:6a00:4f90:b0:71e:68ae:aae1 with SMTP id d2e1a72fcca58-72030b936f1mr2008282b3a.19.1729654476205; Tue, 22 Oct 2024 20:34:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, TANG Tiancheng , Liu Zhiwei , Daniel Henrique Barboza Subject: [PULL 03/24] util: Add RISC-V vector extension probe in cpuinfo Date: Tue, 22 Oct 2024 20:34:11 -0700 Message-ID: <20241023033432.1353830-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023033432.1353830-1-richard.henderson@linaro.org> References: <20241023033432.1353830-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729654729065116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means we can convert all of the division into subtraction. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is more strictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least in current QEMU implemenation, the V vector extension depends on the zve64d extension. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Tested-by: Daniel Henrique Barboza Message-ID: <20241007025700.47259-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- host/include/riscv/host/cpuinfo.h | 2 ++ util/cpuinfo-riscv.c | 34 ++++++++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cp= uinfo.h index 2b00660e36..cdc784e7b6 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,9 +10,11 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; +extern unsigned riscv_lg2_vlenb; =20 /* * We cannot rely on constructor ordering, so other constructors must diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 8cacc67645..971c924012 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -4,6 +4,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/host-utils.h" #include "host/cpuinfo.h" =20 #ifdef CONFIG_ASM_HWPROBE_H @@ -13,6 +14,7 @@ #endif =20 unsigned cpuinfo; +unsigned riscv_lg2_vlenb; static volatile sig_atomic_t got_sigill; =20 static void sigill_handler(int signo, siginfo_t *si, void *data) @@ -34,7 +36,7 @@ static void sigill_handler(int signo, siginfo_t *si, void= *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO= _ZVE64X; unsigned info =3D cpuinfo; =20 if (info) { @@ -50,6 +52,10 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |=3D CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && \ + (defined(__riscv_vector) || defined(__riscv_zve64x)) + info |=3D CPUINFO_ZVE64X; #endif left &=3D ~info; =20 @@ -69,11 +75,22 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #ifdef RISCV_HWPROBE_EXT_ZICOND info |=3D pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICO= ND : 0; left &=3D ~CPUINFO_ZICOND; +#endif + /* For rv64, V is Zve64d, a superset of Zve64x. */ + info |=3D pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : = 0; +#ifdef RISCV_HWPROBE_EXT_ZVE64X + info |=3D pair.value & RISCV_HWPROBE_EXT_ZVE64X ? CPUINFO_ZVE6= 4X : 0; #endif } } #endif /* CONFIG_ASM_HWPROBE_H */ =20 + /* + * We only detect support for vectors with hwprobe. All kernels with + * support for vectors in userspace also support the hwprobe syscall. + */ + left &=3D ~CPUINFO_ZVE64X; + if (left) { struct sigaction sa_old, sa_new; =20 @@ -113,6 +130,21 @@ unsigned __attribute__((constructor)) cpuinfo_init(voi= d) assert(left =3D=3D 0); } =20 + if (info & CPUINFO_ZVE64X) { + /* + * We are guaranteed by RVV-1.0 that VLEN is a power of 2. + * We are guaranteed by Zve64x that VLEN >=3D 64, and that + * EEW of {8,16,32,64} are supported. + */ + unsigned long vlenb; + /* csrr %0, vlenb */ + asm volatile(".insn i 0x73, 0x2, %0, zero, -990" : "=3Dr"(vlenb)); + assert(vlenb >=3D 8); + assert(is_power_of_2(vlenb)); + /* Cache VLEN in a convenient form. */ + riscv_lg2_vlenb =3D ctz32(vlenb); + } + info |=3D CPUINFO_ALWAYS; cpuinfo =3D info; return info; --=20 2.43.0