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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:e0c:1:1599::14; envelope-from=castet.matthieu@free.fr; helo=smtp5-g21.free.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @free.fr) X-ZM-MESSAGEID: 1729629319970116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Matthieu Castet --- hw/intc/armv7m_nvic.c | 38 +++++++++++++++++++++++++++++++++----- target/arm/cpu.c | 4 ++-- target/arm/ptw.c | 23 +++++++++++++++++++---- target/arm/tcg/cpu-v7m.c | 21 ++++++++++++++++++++- 4 files changed, 74 insertions(+), 12 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 98f3cf59bc..ed084e9db3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1386,7 +1386,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf); } - case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda0: /* MPU_RASR (v6M/v7M), MPU_RLAR (v8M) */ case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ @@ -1876,6 +1876,14 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, return; } =20 + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { + if (offset !=3D 0xd9c) + goto bad_offset; + + /* do not support size less than 256 */ + value &=3D ~0xe0; + } + if (value & (1 << 4)) { /* VALID bit means use the region number specified in this * value and also update MPU_RNR.REGION with that value. @@ -1900,12 +1908,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, tlb_flush(CPU(cpu)); break; } - case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ - case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ - case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ - case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ + case 0xda0: /* MPU_RASR (v6M/v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v6M/v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v6M/v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v6M/v7M), MPU_RLAR_A3 (v8M) */ { int region =3D cpu->env.pmsav7.rnr[attrs.secure]; + int rsize; =20 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -1926,6 +1935,25 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, return; } =20 + rsize =3D extract32(value, 1, 5); + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { + if (offset !=3D 0xda0) + goto bad_offset; + /* for armv6-m rsize >=3D 7 (min 256) */ + if (rsize < 7) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPU region size too small %d\n", rsize); + return; + } + } + + /* for armv7-m rsize >=3D 4 (min 32) */ + if (rsize < 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPU region size too small %d\n", rsize); + return; + } + if (region >=3D cpu->pmsav7_dregion) { return; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1320fd8c8f..875e3aab69 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -508,7 +508,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) sizeof(*env->pmsav8.rlar[M_REG_S]) * cpu->pmsav7_dregion); } - } else if (arm_feature(env, ARM_FEATURE_V7)) { + } else if (arm_feature(env, ARM_FEATURE_M)) { memset(env->pmsav7.drbar, 0, sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); memset(env->pmsav7.drsr, 0, @@ -2454,7 +2454,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } =20 if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + arm_feature(env, ARM_FEATURE_M)) { uint32_t nr =3D cpu->pmsav7_dregion; =20 if (nr > 0xff) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index dd40268397..fa771907e3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2383,6 +2383,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu= , ARMMMUIdx mmu_idx, return regime_sctlr(env, mmu_idx) & SCTLR_BR; } =20 +/* armv6m PMSAv6 is mostly compatible with PMSAv7, + * main difference : + * - min region size is 256 instead of 32 + * - TEX can be only 0 (Tex not used by qemu) + * - no alias register + * - HardFault instead of MemManage + */ static bool get_phys_addr_pmsav7(CPUARMState *env, S1Translate *ptw, uint32_t address, @@ -2423,11 +2430,19 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, continue; } =20 - if (!rsize) { + /* Issue warning for invalid values + * for armv7-m rsize >=3D 4 (min 32) + * for armv6-m rsize >=3D 7 (min 256) + */ + if (!rsize || + (arm_feature(env, ARM_FEATURE_M) && ( + rsize < 7 || + (rsize < 4 && !arm_feature(env, ARM_FEATURE_V7)))))= { qemu_log_mask(LOG_GUEST_ERROR, - "DRSR[%d]: Rsize field cannot be 0\n", n); + "DRSR[%d]: Rsize field cannot be %d\n", n, r= size); continue; } + rsize++; rmask =3D (1ull << rsize) - 1; =20 @@ -3515,8 +3530,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, ptw, address, access_type, result, fi); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - /* PMSAv7 */ + } else if (arm_feature(env, ARM_FEATURE_V7) || arm_feature(env, AR= M_FEATURE_M)) { + /* PMSAv7 or PMSAv6 */ ret =3D get_phys_addr_pmsav7(env, ptw, address, access_type, result, fi); } else { diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 58e54578d6..01bc5d4375 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -76,6 +76,20 @@ static void cortex_m0_initfn(Object *obj) cpu->isar.id_isar6 =3D 0x00000000; } =20 +static void cortex_m0p_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + /* cortex-m0p is a cortex-m0 with + * vtor and mpu extension + */ + cortex_m0_initfn(obj); + + cpu->midr =3D 0x410cc601; + cpu->pmsav7_dregion =3D 8; +} + + static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -111,6 +125,7 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion =3D 8; + /* VFPv4-SP */ cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000000; @@ -141,6 +156,7 @@ static void cortex_m7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x411fc272; /* r1p2 */ cpu->pmsav7_dregion =3D 8; + /* VFPv5 DP */ cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; cpu->isar.mvfr2 =3D 0x00000040; @@ -173,6 +189,7 @@ static void cortex_m33_initfn(Object *obj) cpu->midr =3D 0x410fd213; /* r0p3 */ cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; + /* VFPv5 DP */ cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000040; @@ -209,7 +226,7 @@ static void cortex_m55_initfn(Object *obj) cpu->revidr =3D 0; cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; - /* These are the MVFR* values for the FPU + full MVE configuration */ + /* These are the MVFR* values for the FPv5-D16-M + full MVE configurat= ion */ cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; @@ -267,6 +284,8 @@ static void arm_v7m_class_init(ObjectClass *oc, void *d= ata) static const ARMCPUInfo arm_v7m_cpus[] =3D { { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m0p", .initfn =3D cortex_m0p_initfn, + .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, --=20 2.39.5