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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu , Yongwei Ma Subject: [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Date: Tue, 22 Oct 2024 21:51:50 +0800 Message-Id: <20241022135151.2052198-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022135151.2052198-1-zhao1.liu@intel.com> References: <20241022135151.2052198-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.519, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1729604420634116600 Content-Type: text/plain; charset="utf-8" Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 31 ++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2047633e4cf7..8aea2308dcb9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1791,6 +1791,10 @@ static void pc_machine_class_init(ObjectClass *oc, v= oid *data) mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; mc->smp_props.modules_supported =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_AUTO; =20 diff --git a/qemu-options.hx b/qemu-options.hx index daae49414740..fe39973d97a5 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=3D@var{} memory encryption object t= o use (default=3Dnone)\n" " hmat=3Don|off controls ACPI HMAT support (default=3Do= ff)\n" " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n" - " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n", + " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n" + " smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3D= topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=3D]name[,prop=3Dvalue[,...]]`` @@ -159,6 +160,34 @@ SRST :: =20 -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512 + + ``smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3Dtopologylevel`` + Define cache properties for SMP system. + + ``cache=3Dcachename`` specifies the cache that the properties will= be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=3Dtopologylevel`` sets the cache topology level. It acc= epts + CPU topology levels including ``thread``, ``core``, ``module``, + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a speci= al + value ``default``. If ``default`` is set, then the cache topology = will + follow the architecture's default cache topology model. If another + topology level is set, the cache will be shared at corresponding C= PU + topology level. For example, ``topology=3Dcore`` makes the cache s= hared + by all threads within a core. The omitting cache will default to u= sing + the ``default`` level. + + The default cache topology model for an i386 PC machine is as foll= ows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``= l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dcore,s= mp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dcore ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, --=20 2.34.1