From nobody Wed Oct 23 00:25:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1729604284; cv=none; d=zohomail.com; s=zohoarc; b=OGmZG7EuPbpimafrkCcwdZcwtxFBKIQ9Xuno5TBtnNNPt13m+d6x0YoXwFcslw+75faeAIkOTU7xga7nMjo3vpNRc3oz0jUYDtwYi2g7qDaIjYiwuDxd0B1E/kDQcd7IVAb+A52gIrhiDsWNZmQXs8bxq8E46kVXqOcyEsBXnLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729604284; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r24SK2dtWO/SgKKW6czEwW+P5IRNwWdkeYXMLKioACc=; b=dT2MlJ67dyFIxKDHOtIyIMs2Ybd5Dztflk2Dm2Jz8Bv71g/8FgSSq0J8PtkjjGHAJUPhRjLsgdQzlvEPBeUc6t4zo2KDn/IeUuh0hbAr2Z2cbAVQIG7/6XTMmC8vhQvZYIJSzr8HbU8ZsIkXw1+w5s3XAuMfZ9dnguvlx9BLTWM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729604284343598.4119376915958; Tue, 22 Oct 2024 06:38:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3F3w-0005yj-07; Tue, 22 Oct 2024 09:36:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3F3t-0005xb-RG; Tue, 22 Oct 2024 09:36:37 -0400 Received: from mgamail.intel.com ([198.175.65.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3F3s-0000DU-41; Tue, 22 Oct 2024 09:36:37 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 06:36:34 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa009.jf.intel.com with ESMTP; 22 Oct 2024 06:36:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729604196; x=1761140196; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Git+7j02oNMDGgTgXnT+j1SOHf1VUhf6k7CHTi5Pq3w=; b=V6WLrK2XKIAVA0s04/0e0WRSIiNTwIIaKA0iw6jWEbEbtZ6prbtxUpE1 CosUCWNB61KcGy+Yu3QjRHsREisn2S296wLqw9YFdwdcyK8WAJjMhjWYG a6A7qQ7e2My3/o43ecka76mg08NIyHZ4iDt7mwWkxYD1IgZ7N0W109w/v G7b8pLtkaK/E0TqtoVjI9djTkPsPuzAW/pTTM668owdNCDPPtCLMidPib 2ZUMjCzf9mrDLGwLMzPqwfUBLIAutz7LGUg8Sd6aeUmMneWQXSmN0GKA2 ZCBYCA4i/utOT8k5MrwL302dBGBmjXTDM6t42hJZA4nZJMF84041cOoQC w==; X-CSE-ConnectionGUID: YLEM/NDIRuuiEIz524sObA== X-CSE-MsgGUID: Hf839jFKTKORqHLg0e5n3A== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46603704" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46603704" X-CSE-ConnectionGUID: Zu/J4WhNRKCC4Y6LAfIRJg== X-CSE-MsgGUID: Ih/MATrcSBepcRjmz4lYDg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,223,1725346800"; d="scan'208";a="79782388" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Date: Tue, 22 Oct 2024 21:51:47 +0800 Message-Id: <20241022135151.2052198-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022135151.2052198-1-zhao1.liu@intel.com> References: <20241022135151.2052198-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.519, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1729604285630116600 Content-Type: text/plain; charset="utf-8" Currently, we have no way to expose the arch-specific default cache model because the cache model is sometimes related to the CPU model (e.g., i386). Since the user might configure "default" level, any comparison with "default" is meaningless before the machine knows the specific level that "default" refers to. We can only check the correctness of the cache topology after the arch loads the user-configured cache model from MachineState.smp_cache and consumes the special "default" level by replacing it with the specific level. Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * New commit to make cache topology check as a separate helper, so that arch-specific code could use this helper to check cache topology. --- hw/core/machine-smp.c | 48 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 1 + 2 files changed, 49 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index ebb7a134a7be..640b2114b429 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -348,3 +348,51 @@ void machine_set_cache_topo_level(MachineState *ms, Ca= cheLevelAndType cache, { ms->smp_cache.props[cache].topology =3D level; } + +/* + * When both cache1 and cache2 are configured with specific topology levels + * (not default level), is cache1's topology level higher than cache2? + */ +static bool smp_cache_topo_cmp(const SmpCache *smp_cache, + CacheLevelAndType cache1, + CacheLevelAndType cache2) +{ + /* + * Before comparing, the "default" topology level should be replaced + * with the specific level. + */ + assert(smp_cache->props[cache1].topology !=3D CPU_TOPOLOGY_LEVEL_DEFAU= LT); + + return smp_cache->props[cache1].topology > smp_cache->props[cache2].to= pology; +} + +/* + * Currently, we have no way to expose the arch-specific default cache mod= el + * because the cache model is sometimes related to the CPU model (e.g., i3= 86). + * + * We can only check the correctness of the cache topology after the arch = loads + * the user-configured cache model from MachineState and consumes the spec= ial + * "default" level by replacing it with the specific level. + */ +bool machine_check_smp_cache(const MachineState *ms, Error **errp) +{ + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D, + CACHE_LEVEL_AND_TYPE_L2) || + smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I, + CACHE_LEVEL_AND_TYPE_L2)) { + error_setg(errp, + "Invalid smp cache topology. " + "L2 cache topology level shouldn't be lower than L1 cac= he"); + return false; + } + + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2, + CACHE_LEVEL_AND_TYPE_L3)) { + error_setg(errp, + "Invalid smp cache topology. " + "L3 cache topology level shouldn't be lower than L2 cac= he"); + return false; + } + + return true; +} diff --git a/include/hw/boards.h b/include/hw/boards.h index 3d6cb5acd6c7..192f78539a6e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -53,6 +53,7 @@ CpuTopologyLevel machine_get_cache_topo_level(const Machi= neState *ms, CacheLevelAndType cache); void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cach= e, CpuTopologyLevel level); +bool machine_check_smp_cache(const MachineState *ms, Error **errp); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t s= ize); =20 /** --=20 2.34.1