From nobody Wed Oct 23 00:24:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1729604315; cv=none; d=zohomail.com; s=zohoarc; b=md9B1R/6RpKOo845vi3YLdvZLBkJJbipe7u5DDPzmlhjEN/RtkZ/1uJYHlLGhgYFv9v52LbZwUn8YoPTYSvkRtiYhzkFcugQzkY62+wPACBPFOMqUtsXVhOMqBEDB4Zmq9uV9dflaOKSdmbNNRt5+6H8aD0c6vroBSs0y6AqVD8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729604315; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s/7/7uYJ7AQ2n8eEAJtMlb601ryTuWCQLZWpaTh39LU=; b=QK28SUzXZqP8HVozkT/OE3b4Tx3NqeS7wn91x8DxK5T63cy4BJQx3OJogXysTbNf78wB9ytCI5Puj9wasdgalo/hJseNAFHV4/BqkCU5y7bUtPy2tAwk6Qs65eN/SLerBU9KkbihfORYL2DM1hltGFX4jObRs/Tt1SWbw+H+xX8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729604315428712.5254034531497; Tue, 22 Oct 2024 06:38:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3F3f-0005iT-I7; Tue, 22 Oct 2024 09:36:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3F3b-0005bm-7Y; Tue, 22 Oct 2024 09:36:19 -0400 Received: from mgamail.intel.com ([198.175.65.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3F3Y-0000Bw-Tr; Tue, 22 Oct 2024 09:36:18 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 06:36:10 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa009.jf.intel.com with ESMTP; 22 Oct 2024 06:36:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729604177; x=1761140177; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rfk8ITGJI1L5Cei1tN2GoDq9qTCt0wMD3MSKGrYw9Os=; b=iYhI7JW+CV5d0t6fGSTSjdC4tZqaH/LFrVkGDqjLBdC94GWatFnn19z8 vvq3SYoW9XdMnCLHNdq7t6FiJcDLY1apYoPUAc622+ycRQOzlq2bydqCK SgufDlgjipgClzHzuOq0ldUmMSFPnHSm2fKktqNSmNJG44t8UKbtgdOku q5XnQCBXqEmuim8ElrbdVnbi4DOlkuPnJD6+ItKG8LRnlgyXTCcswVr1D qbawPqPjvkOR7VPIxtNOM3VN3XzTWmrSe3UdGURtBlZn8DmISg8utRUaR 7O2+r8qFS4/nwboovm3W6czlskvOlQdc1z4ieEUcTQnFIb+4pObKpT3iy A==; X-CSE-ConnectionGUID: MsvkN1lbTEWRyhPTn6lv3Q== X-CSE-MsgGUID: 9DszuNZsRsqM5fRxpgS1gQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46603605" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46603605" X-CSE-ConnectionGUID: pTHKGFXAR5+ONseAbwlpxA== X-CSE-MsgGUID: 3qo7ZV6NTTmPwm6Pv4ReyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,223,1725346800"; d="scan'208";a="79782232" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu Subject: [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Date: Tue, 22 Oct 2024 21:51:43 +0800 Message-Id: <20241022135151.2052198-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022135151.2052198-1-zhao1.liu@intel.com> References: <20241022135151.2052198-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.519, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1729604315859116600 Content-Type: text/plain; charset="utf-8" In the follow-up change, the CPU topology enumeration will be moved to QAPI. And considerring "invalid" should not be exposed to QAPI as an unsettable item, so, as a preparation for future changes, remove "invalid" level from the current CPU topology enumeration structure and define it by a macro instead. Due to the removal of the enumeration of "invalid", bit 0 of CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid" level, but will start at the SMT level. Therefore, to honor this change, update the encoding rule for CPUID[0x1F]. Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Tested by the following cases to ensure 0x1f's behavior hasn't changed: -smp cpus=3D24,sockets=3D2,dies=3D3,modules=3D2,cores=3D2,threads=3D1 -smp cpus=3D24,sockets=3D2,dies=3D1,modules=3D3,cores=3D2,threads=3D2 -smp cpus=3D24,sockets=3D2,modules=3D3,cores=3D2,threads=3D2 -smp cpus=3D24,sockets=3D2,dies=3D3,modules=3D1,cores=3D2,threads=3D2 -smp cpus=3D24,sockets=3D2,dies=3D3,cores=3D2,threads=3D2 --- Changes since Patch v3: * Now commit to stop exposing "invalid" enumeration in QAPI. (Daniel) --- include/hw/i386/topology.h | 3 ++- target/i386/cpu.c | 13 ++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index dff49fce1154..48b43edc5a90 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -62,6 +62,8 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 +#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX + /* * CPUTopoLevel is the general i386 topology hierarchical representation, * ordered by increasing hierarchical relationship. @@ -69,7 +71,6 @@ typedef struct X86CPUTopoInfo { * or AMD (CPUID[0x80000026]). */ enum CPUTopoLevel { - CPU_TOPO_LEVEL_INVALID, CPU_TOPO_LEVEL_SMT, CPU_TOPO_LEVEL_CORE, CPU_TOPO_LEVEL_MODULE, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ff1af032eaa..638de9c29c4c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -367,20 +367,21 @@ static void encode_topo_cpuid1f(CPUX86State *env, uin= t32_t count, uint32_t *ecx, uint32_t *edx) { X86CPU *cpu =3D env_archcpu(env); - unsigned long level, next_level; + unsigned long level, base_level, next_level; uint32_t num_threads_next_level, offset_next_level; =20 - assert(count + 1 < CPU_TOPO_LEVEL_MAX); + assert(count <=3D CPU_TOPO_LEVEL_PACKAGE); =20 /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. - * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). + * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT). */ - level =3D CPU_TOPO_LEVEL_INVALID; + level =3D CPU_TOPO_LEVEL_SMT; + base_level =3D level; for (int i =3D 0; i <=3D count; i++) { level =3D find_next_bit(env->avail_cpu_topo, CPU_TOPO_LEVEL_PACKAGE, - level + 1); + base_level); =20 /* * CPUID[0x1f] doesn't explicitly encode the package level, @@ -391,6 +392,8 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint3= 2_t count, level =3D CPU_TOPO_LEVEL_INVALID; break; } + /* Search the next level. */ + base_level =3D level + 1; } =20 if (level =3D=3D CPU_TOPO_LEVEL_INVALID) { --=20 2.34.1