From nobody Wed Oct 23 01:27:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1729590182; cv=none; d=zohomail.com; s=zohoarc; b=Knd/P1xxxMgsgosouh18bKLzUEjC9OIv5i89w+6kwTvu4mCf/i7aqvtE9qzHWLGgVKQINDHB8Cqgh2s2sl2csfsWqWrWL/s78n+a039cJT8i9PxuNBJ8X64eLYFeS7OXNhjRzXDFLuSgoWyd6CEHjZ5IJN/JshGR4fzbJk0qK1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729590182; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=sPNhzm8/J8EjJ/L8kCWrUBMV+U4KeZTcU9Vbxs3YM80=; b=gQzR0sq46uMSVm8de3Vb3xa097/yap9Leh5afHRejkpBMF6b7kPTgexmXV1IDNN9/vYd5fFMHlzrbNYCxyKGyUGOdpkdNDHYhoTwnCfAhp1+91W1toSwij96BzCWhH/oC3c1TJqy/FqhfXd7dq5Yfdjb8V49B5+XU1BUiMl7s+0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729590182289347.40066595951373; Tue, 22 Oct 2024 02:43:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3BOh-0002s4-Rd; Tue, 22 Oct 2024 05:41:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3BOT-0002ok-Ue; Tue, 22 Oct 2024 05:41:38 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3BOR-00015E-RL; Tue, 22 Oct 2024 05:41:36 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 22 Oct 2024 17:41:12 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 22 Oct 2024 17:41:12 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , Thomas Huth , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 03/18] hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq Date: Tue, 22 Oct 2024 17:40:55 +0800 Message-ID: <20241022094110.1574011-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241022094110.1574011-1-jamin_lin@aspeedtech.com> References: <20241022094110.1574011-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1729590184208116600 According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2" to enable quad mode. Currently, m25p80 support users utilize "Write Status Register 1(0x01)" com= mand to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x= 35)" command to get the QE bit status. However, some firmware directly utilize "Status Register 2(0x31)" command to set QE bit. To fully support quad mode for w25q01jvq, adds WRSR2 command. Update collecting data needed 1 byte for WRSR2 command in decode_new_cmd function and verify QE bit at the first byte of collecting data bit 2 in complete_collecting_data. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/block/m25p80.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 3f55b8f385..411d810d3b 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -430,6 +430,11 @@ typedef enum { RDCR_EQIO =3D 0x35, RSTQIO =3D 0xf5, =20 + /* + * Winbond: 0x31 - write status register 2 + */ + WRSR2 =3D 0x31, + RNVCR =3D 0xB5, WNVCR =3D 0xB1, =20 @@ -821,6 +826,15 @@ static void complete_collecting_data(Flash *s) s->write_enable =3D false; } break; + case WRSR2: + switch (get_man(s)) { + case MAN_WINBOND: + s->quad_enable =3D !!(s->data[0] & 0x02); + break; + default: + break; + } + break; case BRWR: case EXTEND_ADDR_WRITE: s->ear =3D s->data[0]; @@ -1280,7 +1294,31 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; break; + case WRSR2: + /* + * If WP# is low and status_register_write_disabled is high, + * status register writes are disabled. + * This is also called "hardware protected mode" (HPM). All other + * combinations of the two states are called "software protected m= ode" + * (SPM), and status register writes are permitted. + */ + if ((s->wp_level =3D=3D 0 && s->status_register_write_disabled) + || !s->write_enable) { + qemu_log_mask(LOG_GUEST_ERROR, + "M25P80: Status register 2 write is disabled!\n"= ); + break; + } =20 + switch (get_man(s)) { + case MAN_WINBOND: + s->needed_bytes =3D 1; + s->state =3D STATE_COLLECTING_DATA; + s->pos =3D 0; + break; + default: + break; + } + break; case WRDI: s->write_enable =3D false; if (get_man(s) =3D=3D MAN_SST) { --=20 2.34.1