From nobody Wed Oct 23 01:30:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1729590228; cv=none; d=zohomail.com; s=zohoarc; b=oFboHIRTpEWx1OZB+bD9R5mtKOMhvQsLwUmtuN4Iap6Ij5M0taZMH3qo1LNIgwgVeLSOy5FEIhDjMBfCtnOwK0T+nwTilq4/lY9W+CN6gL4O+P0vG46QY5ueN4ttQAbecKTbpc4V6LxwDfJUro4jiy8axvy+I0QBbEOmvjx1+kc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729590228; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=dmG8xmmABw+4IvLX7DtIERjyyKrXlhA9GmCyZKauRbc=; b=OF2y2VFBQwqtB46BUm2TOEmwWW32ziZhnTdien3lNsKFaQ1RbtGLl1IVNpijYV2zBnNX0ISyIeqOnsTdlvq+JInfPmU4L6AbvvJEQuIIVKxRx8c6/Rq0NxBUfpaViZ2iIm/pA4A4+Awyn1qbuErizsnQDNc/Uwq4OaEQPevAOCk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729590228261165.53304457527918; Tue, 22 Oct 2024 02:43:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3BOj-0002tS-5E; Tue, 22 Oct 2024 05:41:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3BOO-0002o4-M1; Tue, 22 Oct 2024 05:41:33 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3BON-00015E-3J; Tue, 22 Oct 2024 05:41:32 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 22 Oct 2024 17:41:11 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 22 Oct 2024 17:41:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , Thomas Huth , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 02/18] hw/block:m25p80: Fix coding style Date: Tue, 22 Oct 2024 17:40:54 +0800 Message-ID: <20241022094110.1574011-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241022094110.1574011-1-jamin_lin@aspeedtech.com> References: <20241022094110.1574011-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1729590230681116600 Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/block/m25p80.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index f7123f9e68..3f55b8f385 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -61,7 +61,8 @@ typedef struct FlashPartInfo { */ uint8_t id[SPI_NOR_MAX_ID_LEN]; uint8_t id_len; - /* there is confusion between manufacturers as to what a sector is. In= this + /* + * there is confusion between manufacturers as to what a sector is. In= this * device model, a "sector" is the size that is erased by the ERASE_SE= CTOR * command (opcode 0xd8). */ @@ -168,7 +169,7 @@ typedef struct FlashPartInfo { /* * Spansion read mode command length in bytes, * the mode is currently not supported. -*/ + */ =20 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 @@ -189,7 +190,8 @@ static const FlashPartInfo known_devices[] =3D { =20 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, =20 - /* Atmel EEPROMS - it is assumed, that don't care bit in command + /* + * Atmel EEPROMS - it is assumed, that don't care bit in command * is set to 0. Block protection is not supported. */ { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, @@ -275,10 +277,13 @@ static const FlashPartInfo known_devices[] =3D { { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4= ) }, { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2= ) }, { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2= ) }, - { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | = ER_32K, 2) }, - { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | = ER_32K, 2) }, + { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, + ER_4K | ER_32K, 2) }, + { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, + ER_4K | ER_32K, 2) }, =20 - /* Spansion -- single (large) sector size only, at least + /* + * Spansion -- single (large) sector size only, at least * for the chips listed here (without boot sectors). */ { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, @@ -549,7 +554,8 @@ static void blk_sync_complete(void *opaque, int ret) qemu_iovec_destroy(iov); g_free(iov); =20 - /* do nothing. Masters do not directly interact with the backing store, + /* + * do nothing. Masters do not directly interact with the backing store, * only the working copy so no mutexing required. */ } @@ -1843,7 +1849,7 @@ static void m25p80_register_types(void) =20 type_register_static(&m25p80_info); for (i =3D 0; i < ARRAY_SIZE(known_devices); ++i) { - TypeInfo ti =3D { + const TypeInfo ti =3D { .name =3D known_devices[i].part_name, .parent =3D TYPE_M25P80, .class_init =3D m25p80_class_init, --=20 2.34.1