From nobody Wed Oct 23 01:41:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1729590341; cv=none; d=zohomail.com; s=zohoarc; b=JWkWsiqNDHgTdi6+9p99+Z14NSu64/xQSk5K4XGihHXZlwsjsu11v+RzCKhVqGe4N+c1wJeSYXqgqAwOnA2iIHnTamooMD7j0i4FVyZq71uvjJg+F78BMACgCytyMrO8i9wYCxbE0295k207/auc4zSabjmIYpA/nztlhyWnH7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729590341; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=IFr5MtbdaFnHfvkeJ3nGQxLqSa87T2EJpufJG7j+dvI=; b=CfgfluTCXlaqiczEvx3wW9jVXMhCzYgGlSAIdf1SApsPb5QshC9V0zKF6iuK76NzSHuBuBqkLVKyb5YX6o+0Uzj1weBYIhgrTjSHDmWhqp0r40uVA7Ny64gVbOg3euQdcnkL+IGAOuDMvvgfIc9RUWPdCA5abnFe4BRuGIW2vME= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729590341610337.7009365293861; Tue, 22 Oct 2024 02:45:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t3BQ6-0006Dy-Lg; Tue, 22 Oct 2024 05:43:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3BPq-0004i2-N6; Tue, 22 Oct 2024 05:43:03 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t3BPl-0001CU-Mj; Tue, 22 Oct 2024 05:43:02 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 22 Oct 2024 17:41:17 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 22 Oct 2024 17:41:17 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , Thomas Huth , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v2 17/18] test/qtest: Introduce a new aspeed-smc-utils.c to place common testcases Date: Tue, 22 Oct 2024 17:41:09 +0800 Message-ID: <20241022094110.1574011-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241022094110.1574011-1-jamin_lin@aspeedtech.com> References: <20241022094110.1574011-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1729590343093116600 Content-Type: text/plain; charset="utf-8" The testcases for ASPEED SMC model were placed in aspeed_smc-test.c. However, this test file only supports for ARM32. To support all ASPEED SOCs such as AST2700 whose CPU architecture is aarch64, introduces a new aspeed-smc-utils source file and move all common APIs and testcases from aspeed_smc-test.c to aspeed-smc-utils.c. Finally, users are able to re-used these testcase for AST2700 and future ASPEED SOCs testing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-smc-utils.c | 681 ++++++++++++++++++++++++++++++++ tests/qtest/aspeed-smc-utils.h | 95 +++++ tests/qtest/aspeed_smc-test.c | 700 +-------------------------------- tests/qtest/meson.build | 1 + 4 files changed, 778 insertions(+), 699 deletions(-) create mode 100644 tests/qtest/aspeed-smc-utils.c create mode 100644 tests/qtest/aspeed-smc-utils.h diff --git a/tests/qtest/aspeed-smc-utils.c b/tests/qtest/aspeed-smc-utils.c new file mode 100644 index 0000000000..37da5d1f3b --- /dev/null +++ b/tests/qtest/aspeed-smc-utils.c @@ -0,0 +1,681 @@ +/* + * QTest testcase for the M25P80 Flash (Using the Aspeed SPI + * Controller) + * + * Copyright (C) 2016 IBM Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "libqtest-single.h" +#include "qemu/bitops.h" +#include "aspeed-smc-utils.h" + +/* + * Use an explicit bswap for the values read/wrote to the flash region + * as they are BE and the Aspeed CPU is LE. + */ +static inline uint32_t make_be32(uint32_t data) +{ + return bswap32(data); +} + +static inline void spi_writel(const TestData *data, uint64_t offset, + uint32_t value) +{ + qtest_writel(data->s, data->spi_base + offset, value); +} + +static inline uint32_t spi_readl(const TestData *data, uint64_t offset) +{ + return qtest_readl(data->s, data->spi_base + offset); +} + +static inline void flash_writeb(const TestData *data, uint64_t offset, + uint8_t value) +{ + qtest_writeb(data->s, data->flash_base + offset, value); +} + +static inline void flash_writel(const TestData *data, uint64_t offset, + uint32_t value) +{ + qtest_writel(data->s, data->flash_base + offset, value); +} + +static inline uint8_t flash_readb(const TestData *data, uint64_t offset) +{ + return qtest_readb(data->s, data->flash_base + offset); +} + +static inline uint32_t flash_readl(const TestData *data, uint64_t offset) +{ + return qtest_readl(data->s, data->flash_base + offset); +} + +static void spi_conf(const TestData *data, uint32_t value) +{ + uint32_t conf =3D spi_readl(data, R_CONF); + + conf |=3D value; + spi_writel(data, R_CONF, conf); +} + +static void spi_conf_remove(const TestData *data, uint32_t value) +{ + uint32_t conf =3D spi_readl(data, R_CONF); + + conf &=3D ~value; + spi_writel(data, R_CONF, conf); +} + +static void spi_ce_ctrl(const TestData *data, uint32_t value) +{ + uint32_t conf =3D spi_readl(data, R_CE_CTRL); + + conf |=3D value; + spi_writel(data, R_CE_CTRL, conf); +} + +static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t c= md) +{ + uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; + uint32_t ctrl =3D spi_readl(data, ctrl_reg); + ctrl &=3D ~(CTRL_USERMODE | 0xff << 16); + ctrl |=3D mode | (cmd << 16); + spi_writel(data, ctrl_reg, ctrl); +} + +static void spi_ctrl_start_user(const TestData *data) +{ + uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; + uint32_t ctrl =3D spi_readl(data, ctrl_reg); + + ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; + spi_writel(data, ctrl_reg, ctrl); + + ctrl &=3D ~CTRL_CE_STOP_ACTIVE; + spi_writel(data, ctrl_reg, ctrl); +} + +static void spi_ctrl_stop_user(const TestData *data) +{ + uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; + uint32_t ctrl =3D spi_readl(data, ctrl_reg); + + ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; + spi_writel(data, ctrl_reg, ctrl); +} + +static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value) +{ + uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; + uint32_t ctrl =3D spi_readl(data, ctrl_reg); + uint32_t mode; + + mode =3D value & CTRL_IO_MODE_MASK; + ctrl &=3D ~CTRL_IO_MODE_MASK; + ctrl |=3D mode; + spi_writel(data, ctrl_reg, ctrl); +} + +static void flash_reset(const TestData *data) +{ + spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs)); + + spi_ctrl_start_user(data); + flash_writeb(data, 0, RESET_ENABLE); + flash_writeb(data, 0, RESET_MEMORY); + flash_writeb(data, 0, WREN); + flash_writeb(data, 0, BULK_ERASE); + flash_writeb(data, 0, WRDI); + spi_ctrl_stop_user(data); + + spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs)); +} + +static void read_page(const TestData *data, uint32_t addr, uint32_t *page) +{ + int i; + + spi_ctrl_start_user(data); + + flash_writeb(data, 0, EN_4BYTE_ADDR); + flash_writeb(data, 0, READ); + flash_writel(data, 0, make_be32(addr)); + + /* Continuous read are supported */ + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + page[i] =3D make_be32(flash_readl(data, 0)); + } + spi_ctrl_stop_user(data); +} + +static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *p= age) +{ + int i; + + /* move out USER mode to use direct reads from the AHB bus */ + spi_ctrl_setmode(data, CTRL_READMODE, READ); + + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + page[i] =3D make_be32(flash_readl(data, addr + i * 4)); + } +} + +static void write_page_mem(const TestData *data, uint32_t addr, + uint32_t write_value) +{ + spi_ctrl_setmode(data, CTRL_WRITEMODE, PP); + + for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(data, addr + i * 4, write_value); + } +} + +static void assert_page_mem(const TestData *data, uint32_t addr, + uint32_t expected_value) +{ + uint32_t page[FLASH_PAGE_SIZE / 4]; + read_page_mem(data, addr, page); + for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, expected_value); + } +} + +void test_read_jedec(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t jedec =3D 0x0; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, JEDEC_READ); + jedec |=3D flash_readb(test_data, 0) << 16; + jedec |=3D flash_readb(test_data, 0) << 8; + jedec |=3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + + flash_reset(test_data); + + g_assert_cmphex(jedec, =3D=3D, test_data->jedec_id); +} + +void test_erase_sector(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t some_page_addr =3D test_data->page_addr; + uint32_t page[FLASH_PAGE_SIZE / 4]; + int i; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + /* + * Previous page should be full of 0xffs after backend is + * initialized + */ + read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, PP); + flash_writel(test_data, 0, make_be32(some_page_addr)); + + /* Fill the page with its own addresses */ + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); + } + spi_ctrl_stop_user(test_data); + + /* Check the page is correctly written */ + read_page(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4); + } + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, ERASE_SECTOR); + flash_writel(test_data, 0, make_be32(some_page_addr)); + spi_ctrl_stop_user(test_data); + + /* Check the page is erased */ + read_page(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + flash_reset(test_data); +} + +void test_erase_all(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t some_page_addr =3D test_data->page_addr; + uint32_t page[FLASH_PAGE_SIZE / 4]; + int i; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + /* + * Previous page should be full of 0xffs after backend is + * initialized + */ + read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, PP); + flash_writel(test_data, 0, make_be32(some_page_addr)); + + /* Fill the page with its own addresses */ + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); + } + spi_ctrl_stop_user(test_data); + + /* Check the page is correctly written */ + read_page(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4); + } + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, BULK_ERASE); + spi_ctrl_stop_user(test_data); + + /* Check the page is erased */ + read_page(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + flash_reset(test_data); +} + +void test_write_page(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t my_page_addr =3D test_data->page_addr; + uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE; + uint32_t page[FLASH_PAGE_SIZE / 4]; + int i; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, PP); + flash_writel(test_data, 0, make_be32(my_page_addr)); + + /* Fill the page with its own addresses */ + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); + } + spi_ctrl_stop_user(test_data); + + /* Check what was written */ + read_page(test_data, my_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); + } + + /* Check some other page. It should be full of 0xff */ + read_page(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + flash_reset(test_data); +} + +void test_read_page_mem(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t my_page_addr =3D test_data->page_addr; + uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE; + uint32_t page[FLASH_PAGE_SIZE / 4]; + int i; + + /* + * Enable 4BYTE mode for controller. + */ + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); + + /* Enable 4BYTE mode for flash. */ + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, PP); + flash_writel(test_data, 0, make_be32(my_page_addr)); + + /* Fill the page with its own addresses */ + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); + } + spi_ctrl_stop_user(test_data); + spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + /* Check what was written */ + read_page_mem(test_data, my_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); + } + + /* Check some other page. It should be full of 0xff */ + read_page_mem(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + flash_reset(test_data); +} + +void test_write_page_mem(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t my_page_addr =3D test_data->page_addr; + uint32_t page[FLASH_PAGE_SIZE / 4]; + int i; + + /* + * Enable 4BYTE mode for controller. + */ + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); + + /* Enable 4BYTE mode for flash. */ + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + spi_ctrl_stop_user(test_data); + + /* move out USER mode to use direct writes to the AHB bus */ + spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP); + + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(test_data, my_page_addr + i * 4, + make_be32(my_page_addr + i * 4)); + } + + /* Check what was written */ + read_page_mem(test_data, my_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); + } + + flash_reset(test_data); +} + +void test_read_status_reg(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint8_t r; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + + g_assert_cmphex(r & SR_WEL, =3D=3D, 0); + g_assert(!qtest_qom_get_bool + (test_data->s, test_data->node, "write-enable")); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + + g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL); + g_assert(qtest_qom_get_bool + (test_data->s, test_data->node, "write-enable")); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WRDI); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + + g_assert_cmphex(r & SR_WEL, =3D=3D, 0); + g_assert(!qtest_qom_get_bool + (test_data->s, test_data->node, "write-enable")); + + flash_reset(test_data); +} + +void test_status_reg_write_protection(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint8_t r; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + /* default case: WP# is high and SRWD is low -> status register writab= le */ + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + /* test ability to write SRWD */ + flash_writeb(test_data, 0, WRSR); + flash_writeb(test_data, 0, SRWD); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + g_assert_cmphex(r & SRWD, =3D=3D, SRWD); + + /* WP# high and SRWD high -> status register writable */ + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + /* test ability to write SRWD */ + flash_writeb(test_data, 0, WRSR); + flash_writeb(test_data, 0, 0); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + g_assert_cmphex(r & SRWD, =3D=3D, 0); + + /* WP# low and SRWD low -> status register writable */ + qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0); + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + /* test ability to write SRWD */ + flash_writeb(test_data, 0, WRSR); + flash_writeb(test_data, 0, SRWD); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + g_assert_cmphex(r & SRWD, =3D=3D, SRWD); + + /* WP# low and SRWD high -> status register NOT writable */ + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0 , WREN); + /* test ability to write SRWD */ + flash_writeb(test_data, 0, WRSR); + flash_writeb(test_data, 0, 0); + flash_writeb(test_data, 0, RDSR); + r =3D flash_readb(test_data, 0); + spi_ctrl_stop_user(test_data); + /* write is not successful */ + g_assert_cmphex(r & SRWD, =3D=3D, SRWD); + + qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1); + flash_reset(test_data); +} + +void test_write_block_protect(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t sector_size =3D 65536; + uint32_t n_sectors =3D 512; + + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + uint32_t bp_bits =3D 0b0; + + for (int i =3D 0; i < 16; i++) { + bp_bits =3D ((i & 0b1000) << 3) | ((i & 0b0111) << 2); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, BULK_ERASE); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, WRSR); + flash_writeb(test_data, 0, bp_bits); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + spi_ctrl_stop_user(test_data); + + uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors= ) : 0; + uint32_t protection_start =3D n_sectors - num_protected_sectors; + uint32_t protection_end =3D n_sectors; + + for (int sector =3D 0; sector < n_sectors; sector++) { + uint32_t addr =3D sector * sector_size; + + assert_page_mem(test_data, addr, 0xffffffff); + write_page_mem(test_data, addr, make_be32(0xabcdef12)); + + uint32_t expected_value =3D protection_start <=3D sector + && sector < protection_end + ? 0xffffffff : 0xabcdef12; + + assert_page_mem(test_data, addr, expected_value); + } + } + + flash_reset(test_data); +} + +void test_write_block_protect_bottom_bit(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t sector_size =3D 65536; + uint32_t n_sectors =3D 512; + + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + /* top bottom bit is enabled */ + uint32_t bp_bits =3D 0b00100 << 3; + + for (int i =3D 0; i < 16; i++) { + bp_bits =3D (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, BULK_ERASE); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, WRSR); + flash_writeb(test_data, 0, bp_bits); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + spi_ctrl_stop_user(test_data); + + uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors= ) : 0; + uint32_t protection_start =3D 0; + uint32_t protection_end =3D num_protected_sectors; + + for (int sector =3D 0; sector < n_sectors; sector++) { + uint32_t addr =3D sector * sector_size; + + assert_page_mem(test_data, addr, 0xffffffff); + write_page_mem(test_data, addr, make_be32(0xabcdef12)); + + uint32_t expected_value =3D protection_start <=3D sector + && sector < protection_end + ? 0xffffffff : 0xabcdef12; + + assert_page_mem(test_data, addr, expected_value); + } + } + + flash_reset(test_data); +} + +void test_write_page_qpi(const void *data) +{ + const TestData *test_data =3D (const TestData *)data; + uint32_t my_page_addr =3D test_data->page_addr; + uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE; + uint32_t page[FLASH_PAGE_SIZE / 4]; + uint32_t page_pattern[] =3D { + 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf + }; + int i; + + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); + + spi_ctrl_start_user(test_data); + flash_writeb(test_data, 0, EN_4BYTE_ADDR); + flash_writeb(test_data, 0, WREN); + flash_writeb(test_data, 0, PP); + flash_writel(test_data, 0, make_be32(my_page_addr)); + + /* Set QPI mode */ + spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO); + + /* Fill the page pattern */ + for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) { + flash_writel(test_data, 0, make_be32(page_pattern[i])); + } + + /* Fill the page with its own addresses */ + for (; i < FLASH_PAGE_SIZE / 4; i++) { + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); + } + + /* Restore io mode */ + spi_ctrl_set_io_mode(test_data, 0); + spi_ctrl_stop_user(test_data); + + /* Check what was written */ + read_page(test_data, my_page_addr, page); + for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) { + g_assert_cmphex(page[i], =3D=3D, page_pattern[i]); + } + for (; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); + } + + /* Check some other page. It should be full of 0xff */ + read_page(test_data, some_page_addr, page); + for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, 0xffffffff); + } + + flash_reset(test_data); +} + diff --git a/tests/qtest/aspeed-smc-utils.h b/tests/qtest/aspeed-smc-utils.h new file mode 100644 index 0000000000..0f298085c2 --- /dev/null +++ b/tests/qtest/aspeed-smc-utils.h @@ -0,0 +1,95 @@ +/* + * QTest testcase for the M25P80 Flash (Using the Aspeed SPI + * Controller) + * + * Copyright (C) 2016 IBM Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef TESTS_ASPEED_SMC_UTILS_H +#define TESTS_ASPEED_SMC_UTILS_H + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "libqtest-single.h" +#include "qemu/bitops.h" + +/* + * ASPEED SPI Controller registers + */ +#define R_CONF 0x00 +#define CONF_ENABLE_W0 16 +#define R_CE_CTRL 0x04 +#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ +#define R_CTRL0 0x10 +#define CTRL_IO_QUAD_IO BIT(31) +#define CTRL_CE_STOP_ACTIVE BIT(2) +#define CTRL_READMODE 0x0 +#define CTRL_FREADMODE 0x1 +#define CTRL_WRITEMODE 0x2 +#define CTRL_USERMODE 0x3 +#define SR_WEL BIT(1) + +/* + * Flash commands + */ +enum { + JEDEC_READ =3D 0x9f, + RDSR =3D 0x5, + WRDI =3D 0x4, + BULK_ERASE =3D 0xc7, + READ =3D 0x03, + PP =3D 0x02, + WRSR =3D 0x1, + WREN =3D 0x6, + SRWD =3D 0x80, + RESET_ENABLE =3D 0x66, + RESET_MEMORY =3D 0x99, + EN_4BYTE_ADDR =3D 0xB7, + ERASE_SECTOR =3D 0xd8, +}; + +#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) +#define FLASH_PAGE_SIZE 256 + +typedef struct TestData { + QTestState *s; + uint64_t spi_base; + uint64_t flash_base; + uint32_t jedec_id; + char *tmp_path; + uint8_t cs; + const char *node; + uint32_t page_addr; +} TestData; + +void test_read_jedec(const void *data); +void test_erase_sector(const void *data); +void test_erase_all(const void *data); +void test_write_page(const void *data); +void test_read_page_mem(const void *data); +void test_write_page_mem(const void *data); +void test_read_status_reg(const void *data); +void test_status_reg_write_protection(const void *data); +void test_write_block_protect(const void *data); +void test_write_block_protect_bottom_bit(const void *data); +void test_write_page_qpi(const void *data); + +#endif /* TESTS_ASPEED_SMC_UTILS_H */ diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index 59f3876cdc..ef3fdc516e 100644 --- a/tests/qtest/aspeed_smc-test.c +++ b/tests/qtest/aspeed_smc-test.c @@ -27,705 +27,7 @@ #include "qemu/bswap.h" #include "libqtest-single.h" #include "qemu/bitops.h" - -/* - * ASPEED SPI Controller registers - */ -#define R_CONF 0x00 -#define CONF_ENABLE_W0 16 -#define R_CE_CTRL 0x04 -#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ -#define R_CTRL0 0x10 -#define CTRL_IO_QUAD_IO BIT(31) -#define CTRL_CE_STOP_ACTIVE BIT(2) -#define CTRL_READMODE 0x0 -#define CTRL_FREADMODE 0x1 -#define CTRL_WRITEMODE 0x2 -#define CTRL_USERMODE 0x3 -#define SR_WEL BIT(1) - -/* - * Flash commands - */ -enum { - JEDEC_READ =3D 0x9f, - RDSR =3D 0x5, - WRDI =3D 0x4, - BULK_ERASE =3D 0xc7, - READ =3D 0x03, - PP =3D 0x02, - WRSR =3D 0x1, - WREN =3D 0x6, - SRWD =3D 0x80, - RESET_ENABLE =3D 0x66, - RESET_MEMORY =3D 0x99, - EN_4BYTE_ADDR =3D 0xB7, - ERASE_SECTOR =3D 0xd8, -}; - -#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) -#define FLASH_PAGE_SIZE 256 - -typedef struct TestData { - QTestState *s; - uint64_t spi_base; - uint64_t flash_base; - uint32_t jedec_id; - char *tmp_path; - uint8_t cs; - const char *node; - uint32_t page_addr; -} TestData; - -/* - * Use an explicit bswap for the values read/wrote to the flash region - * as they are BE and the Aspeed CPU is LE. - */ -static inline uint32_t make_be32(uint32_t data) -{ - return bswap32(data); -} - -static inline void spi_writel(const TestData *data, uint64_t offset, - uint32_t value) -{ - qtest_writel(data->s, data->spi_base + offset, value); -} - -static inline uint32_t spi_readl(const TestData *data, uint64_t offset) -{ - return qtest_readl(data->s, data->spi_base + offset); -} - -static inline void flash_writeb(const TestData *data, uint64_t offset, - uint8_t value) -{ - qtest_writeb(data->s, data->flash_base + offset, value); -} - -static inline void flash_writel(const TestData *data, uint64_t offset, - uint32_t value) -{ - qtest_writel(data->s, data->flash_base + offset, value); -} - -static inline uint8_t flash_readb(const TestData *data, uint64_t offset) -{ - return qtest_readb(data->s, data->flash_base + offset); -} - -static inline uint32_t flash_readl(const TestData *data, uint64_t offset) -{ - return qtest_readl(data->s, data->flash_base + offset); -} - -static void spi_conf(const TestData *data, uint32_t value) -{ - uint32_t conf =3D spi_readl(data, R_CONF); - - conf |=3D value; - spi_writel(data, R_CONF, conf); -} - -static void spi_conf_remove(const TestData *data, uint32_t value) -{ - uint32_t conf =3D spi_readl(data, R_CONF); - - conf &=3D ~value; - spi_writel(data, R_CONF, conf); -} - -static void spi_ce_ctrl(const TestData *data, uint32_t value) -{ - uint32_t conf =3D spi_readl(data, R_CE_CTRL); - - conf |=3D value; - spi_writel(data, R_CE_CTRL, conf); -} - -static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t c= md) -{ - uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; - uint32_t ctrl =3D spi_readl(data, ctrl_reg); - ctrl &=3D ~(CTRL_USERMODE | 0xff << 16); - ctrl |=3D mode | (cmd << 16); - spi_writel(data, ctrl_reg, ctrl); -} - -static void spi_ctrl_start_user(const TestData *data) -{ - uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; - uint32_t ctrl =3D spi_readl(data, ctrl_reg); - - ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; - spi_writel(data, ctrl_reg, ctrl); - - ctrl &=3D ~CTRL_CE_STOP_ACTIVE; - spi_writel(data, ctrl_reg, ctrl); -} - -static void spi_ctrl_stop_user(const TestData *data) -{ - uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; - uint32_t ctrl =3D spi_readl(data, ctrl_reg); - - ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; - spi_writel(data, ctrl_reg, ctrl); -} - -static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value) -{ - uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4; - uint32_t ctrl =3D spi_readl(data, ctrl_reg); - uint32_t mode; - - mode =3D value & CTRL_IO_MODE_MASK; - ctrl &=3D ~CTRL_IO_MODE_MASK; - ctrl |=3D mode; - spi_writel(data, ctrl_reg, ctrl); -} - -static void flash_reset(const TestData *data) -{ - spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs)); - - spi_ctrl_start_user(data); - flash_writeb(data, 0, RESET_ENABLE); - flash_writeb(data, 0, RESET_MEMORY); - flash_writeb(data, 0, WREN); - flash_writeb(data, 0, BULK_ERASE); - flash_writeb(data, 0, WRDI); - spi_ctrl_stop_user(data); - - spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs)); -} - -static void test_read_jedec(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t jedec =3D 0x0; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, JEDEC_READ); - jedec |=3D flash_readb(test_data, 0) << 16; - jedec |=3D flash_readb(test_data, 0) << 8; - jedec |=3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - - flash_reset(test_data); - - g_assert_cmphex(jedec, =3D=3D, test_data->jedec_id); -} - -static void read_page(const TestData *data, uint32_t addr, uint32_t *page) -{ - int i; - - spi_ctrl_start_user(data); - - flash_writeb(data, 0, EN_4BYTE_ADDR); - flash_writeb(data, 0, READ); - flash_writel(data, 0, make_be32(addr)); - - /* Continuous read are supported */ - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - page[i] =3D make_be32(flash_readl(data, 0)); - } - spi_ctrl_stop_user(data); -} - -static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *p= age) -{ - int i; - - /* move out USER mode to use direct reads from the AHB bus */ - spi_ctrl_setmode(data, CTRL_READMODE, READ); - - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - page[i] =3D make_be32(flash_readl(data, addr + i * 4)); - } -} - -static void write_page_mem(const TestData *data, uint32_t addr, - uint32_t write_value) -{ - spi_ctrl_setmode(data, CTRL_WRITEMODE, PP); - - for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(data, addr + i * 4, write_value); - } -} - -static void assert_page_mem(const TestData *data, uint32_t addr, - uint32_t expected_value) -{ - uint32_t page[FLASH_PAGE_SIZE / 4]; - read_page_mem(data, addr, page); - for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, expected_value); - } -} - -static void test_erase_sector(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t some_page_addr =3D test_data->page_addr; - uint32_t page[FLASH_PAGE_SIZE / 4]; - int i; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - /* - * Previous page should be full of 0xffs after backend is - * initialized - */ - read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, PP); - flash_writel(test_data, 0, make_be32(some_page_addr)); - - /* Fill the page with its own addresses */ - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); - } - spi_ctrl_stop_user(test_data); - - /* Check the page is correctly written */ - read_page(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4); - } - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, ERASE_SECTOR); - flash_writel(test_data, 0, make_be32(some_page_addr)); - spi_ctrl_stop_user(test_data); - - /* Check the page is erased */ - read_page(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - flash_reset(test_data); -} - -static void test_erase_all(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t some_page_addr =3D test_data->page_addr; - uint32_t page[FLASH_PAGE_SIZE / 4]; - int i; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - /* - * Previous page should be full of 0xffs after backend is - * initialized - */ - read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, PP); - flash_writel(test_data, 0, make_be32(some_page_addr)); - - /* Fill the page with its own addresses */ - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); - } - spi_ctrl_stop_user(test_data); - - /* Check the page is correctly written */ - read_page(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4); - } - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, BULK_ERASE); - spi_ctrl_stop_user(test_data); - - /* Check the page is erased */ - read_page(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - flash_reset(test_data); -} - -static void test_write_page(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t my_page_addr =3D test_data->page_addr; - uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE; - uint32_t page[FLASH_PAGE_SIZE / 4]; - int i; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, PP); - flash_writel(test_data, 0, make_be32(my_page_addr)); - - /* Fill the page with its own addresses */ - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); - } - spi_ctrl_stop_user(test_data); - - /* Check what was written */ - read_page(test_data, my_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); - } - - /* Check some other page. It should be full of 0xff */ - read_page(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - flash_reset(test_data); -} - -static void test_read_page_mem(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t my_page_addr =3D test_data->page_addr; - uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE; - uint32_t page[FLASH_PAGE_SIZE / 4]; - int i; - - /* - * Enable 4BYTE mode for controller. - */ - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); - - /* Enable 4BYTE mode for flash. */ - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, PP); - flash_writel(test_data, 0, make_be32(my_page_addr)); - - /* Fill the page with its own addresses */ - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); - } - spi_ctrl_stop_user(test_data); - spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - /* Check what was written */ - read_page_mem(test_data, my_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); - } - - /* Check some other page. It should be full of 0xff */ - read_page_mem(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - flash_reset(test_data); -} - -static void test_write_page_mem(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t my_page_addr =3D test_data->page_addr; - uint32_t page[FLASH_PAGE_SIZE / 4]; - int i; - - /* - * Enable 4BYTE mode for controller. - */ - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); - - /* Enable 4BYTE mode for flash. */ - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - spi_ctrl_stop_user(test_data); - - /* move out USER mode to use direct writes to the AHB bus */ - spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP); - - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(test_data, my_page_addr + i * 4, - make_be32(my_page_addr + i * 4)); - } - - /* Check what was written */ - read_page_mem(test_data, my_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); - } - - flash_reset(test_data); -} - -static void test_read_status_reg(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint8_t r; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - - g_assert_cmphex(r & SR_WEL, =3D=3D, 0); - g_assert(!qtest_qom_get_bool - (test_data->s, test_data->node, "write-enable")); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - - g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL); - g_assert(qtest_qom_get_bool - (test_data->s, test_data->node, "write-enable")); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WRDI); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - - g_assert_cmphex(r & SR_WEL, =3D=3D, 0); - g_assert(!qtest_qom_get_bool - (test_data->s, test_data->node, "write-enable")); - - flash_reset(test_data); -} - -static void test_status_reg_write_protection(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint8_t r; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - /* default case: WP# is high and SRWD is low -> status register writab= le */ - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - /* test ability to write SRWD */ - flash_writeb(test_data, 0, WRSR); - flash_writeb(test_data, 0, SRWD); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - g_assert_cmphex(r & SRWD, =3D=3D, SRWD); - - /* WP# high and SRWD high -> status register writable */ - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - /* test ability to write SRWD */ - flash_writeb(test_data, 0, WRSR); - flash_writeb(test_data, 0, 0); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - g_assert_cmphex(r & SRWD, =3D=3D, 0); - - /* WP# low and SRWD low -> status register writable */ - qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0); - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - /* test ability to write SRWD */ - flash_writeb(test_data, 0, WRSR); - flash_writeb(test_data, 0, SRWD); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - g_assert_cmphex(r & SRWD, =3D=3D, SRWD); - - /* WP# low and SRWD high -> status register NOT writable */ - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0 , WREN); - /* test ability to write SRWD */ - flash_writeb(test_data, 0, WRSR); - flash_writeb(test_data, 0, 0); - flash_writeb(test_data, 0, RDSR); - r =3D flash_readb(test_data, 0); - spi_ctrl_stop_user(test_data); - /* write is not successful */ - g_assert_cmphex(r & SRWD, =3D=3D, SRWD); - - qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1); - flash_reset(test_data); -} - -static void test_write_block_protect(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t sector_size =3D 65536; - uint32_t n_sectors =3D 512; - - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - uint32_t bp_bits =3D 0b0; - - for (int i =3D 0; i < 16; i++) { - bp_bits =3D ((i & 0b1000) << 3) | ((i & 0b0111) << 2); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, BULK_ERASE); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, WRSR); - flash_writeb(test_data, 0, bp_bits); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - spi_ctrl_stop_user(test_data); - - uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors= ) : 0; - uint32_t protection_start =3D n_sectors - num_protected_sectors; - uint32_t protection_end =3D n_sectors; - - for (int sector =3D 0; sector < n_sectors; sector++) { - uint32_t addr =3D sector * sector_size; - - assert_page_mem(test_data, addr, 0xffffffff); - write_page_mem(test_data, addr, make_be32(0xabcdef12)); - - uint32_t expected_value =3D protection_start <=3D sector - && sector < protection_end - ? 0xffffffff : 0xabcdef12; - - assert_page_mem(test_data, addr, expected_value); - } - } - - flash_reset(test_data); -} - -static void test_write_block_protect_bottom_bit(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t sector_size =3D 65536; - uint32_t n_sectors =3D 512; - - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - /* top bottom bit is enabled */ - uint32_t bp_bits =3D 0b00100 << 3; - - for (int i =3D 0; i < 16; i++) { - bp_bits =3D (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, BULK_ERASE); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, WRSR); - flash_writeb(test_data, 0, bp_bits); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - spi_ctrl_stop_user(test_data); - - uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors= ) : 0; - uint32_t protection_start =3D 0; - uint32_t protection_end =3D num_protected_sectors; - - for (int sector =3D 0; sector < n_sectors; sector++) { - uint32_t addr =3D sector * sector_size; - - assert_page_mem(test_data, addr, 0xffffffff); - write_page_mem(test_data, addr, make_be32(0xabcdef12)); - - uint32_t expected_value =3D protection_start <=3D sector - && sector < protection_end - ? 0xffffffff : 0xabcdef12; - - assert_page_mem(test_data, addr, expected_value); - } - } - - flash_reset(test_data); -} - -static void test_write_page_qpi(const void *data) -{ - const TestData *test_data =3D (const TestData *)data; - uint32_t my_page_addr =3D test_data->page_addr; - uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE; - uint32_t page[FLASH_PAGE_SIZE / 4]; - uint32_t page_pattern[] =3D { - 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf - }; - int i; - - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); - - spi_ctrl_start_user(test_data); - flash_writeb(test_data, 0, EN_4BYTE_ADDR); - flash_writeb(test_data, 0, WREN); - flash_writeb(test_data, 0, PP); - flash_writel(test_data, 0, make_be32(my_page_addr)); - - /* Set QPI mode */ - spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO); - - /* Fill the page pattern */ - for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) { - flash_writel(test_data, 0, make_be32(page_pattern[i])); - } - - /* Fill the page with its own addresses */ - for (; i < FLASH_PAGE_SIZE / 4; i++) { - flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); - } - - /* Restore io mode */ - spi_ctrl_set_io_mode(test_data, 0); - spi_ctrl_stop_user(test_data); - - /* Check what was written */ - read_page(test_data, my_page_addr, page); - for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) { - g_assert_cmphex(page[i], =3D=3D, page_pattern[i]); - } - for (; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4); - } - - /* Check some other page. It should be full of 0xff */ - read_page(test_data, some_page_addr, page); - for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { - g_assert_cmphex(page[i], =3D=3D, 0xffffffff); - } - - flash_reset(test_data); -} +#include "aspeed-smc-utils.h" =20 static void test_palmetto_bmc(TestData *data) { diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 41f3678cee..fde4de902b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -353,6 +353,7 @@ qtests =3D { 'virtio-net-failover': files('migration-helpers.c'), 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), 'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'), + 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), } =20 if vnc.found() --=20 2.34.1