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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0f6462sm31681145ad.272.2024.10.21.17.11.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 17:11:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729555899; x=1730160699; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H7n2kQs8O6xhKUVpmF73KQCgmDDL6rYv6pHEMWFu6RQ=; b=v+nxVcM1a+mdYqbGYY979sski0EEq3TblhsE1YAtPi3G1sIhnRB5jsDd2LBQWxYVHo Ngvy0UrKfWb+1Y4ntjRnHoXdtfA2t84kp8L60ez78SW6prFSlS0QhZrfLN4+zEifd+1X TQI7PF7YQYG0k/hKTPQ4bkw6JFs5YbH0OcnOTSuo6JQ/rneqEzQD535cXtjBefzkGK9P tpp4lE9CIKGvgfwyWZPhgeGVjjL1CG+ko5t72ETx0HYB7g7CWk2X5pL2WkZdgsK73Cv/ tfbn1ZW5Dk9H+jtCNV03NzrAxVgj1yOey8qe1cI0qJe4emCSp0CzmnSTDdO5O/xgybS9 G2Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729555899; x=1730160699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H7n2kQs8O6xhKUVpmF73KQCgmDDL6rYv6pHEMWFu6RQ=; b=Wl6onbDt/COxsfde1wpJPQAJw8Zbl+VIYbV9Nea6O4AX84KDy+9q47bZ6K5guCpGZ4 QV3443AjvAJ+HiSjShbH7fCr6SegQ37K0otRqp6C18go7+381LBOtQ+/gtlo0NrOdlAO +wZNVJtDyYoxjaeKBsKscn5xFdi+fsxAdyskwAELmlnX8nQB9AFuIgIOeNz2HNq5e2LF 3Tiwk7na75WtHLECwOsYPaL3Gso6Gp4aayieG6ls7gO8pASVsFsh4uuOeSnIQkXiTQKm xEMi1Hkl5sE9HEb8X1/t3UIznoyJN1wH2eVlcn7RC0YiiKG9gI+ivrNmA/+8GliaMVD2 Cf0w== X-Gm-Message-State: AOJu0YyTbuwTlW9uFmBKeuQKguXM5dZQww3PK2NjoCcHYbNRiPDtlLmL UMSODdcpnnGFy0GsaA85w0EUEB0VOZMMuTEDzy/cmQVUGiAHYpxcZbSDZmP3VPeVcTKDjSiB77V 6 X-Google-Smtp-Source: AGHT+IHRdIA6LqRqV9IXLtDAxrkxk9P65X87LgHAlAYvYGslYlX5QwcyGvdkhYkNXS3Xkeh+hMLOtA== X-Received: by 2002:a17:903:244e:b0:20c:9da6:65b0 with SMTP id d9443c01a7336-20e5a8d64fdmr179662675ad.35.1729555898521; Mon, 21 Oct 2024 17:11:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, dbarboza@ventanamicro.com, alistair23@gmail.com, TANG Tiancheng , Liu Zhiwei Subject: [PATCH v7 03/14] util: Add RISC-V vector extension probe in cpuinfo Date: Mon, 21 Oct 2024 17:11:23 -0700 Message-ID: <20241022001134.828724-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241022001134.828724-1-richard.henderson@linaro.org> References: <20241022001134.828724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1729556007958116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means we can convert all of the division into subtraction. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is more strictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least in current QEMU implemenation, the V vector extension depends on the zve64d extension. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Message-ID: <20241007025700.47259-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson Tested-by: Daniel Henrique Barboza --- host/include/riscv/host/cpuinfo.h | 2 ++ util/cpuinfo-riscv.c | 34 ++++++++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cp= uinfo.h index 2b00660e36..cdc784e7b6 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,9 +10,11 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; +extern unsigned riscv_lg2_vlenb; =20 /* * We cannot rely on constructor ordering, so other constructors must diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 8cacc67645..971c924012 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -4,6 +4,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/host-utils.h" #include "host/cpuinfo.h" =20 #ifdef CONFIG_ASM_HWPROBE_H @@ -13,6 +14,7 @@ #endif =20 unsigned cpuinfo; +unsigned riscv_lg2_vlenb; static volatile sig_atomic_t got_sigill; =20 static void sigill_handler(int signo, siginfo_t *si, void *data) @@ -34,7 +36,7 @@ static void sigill_handler(int signo, siginfo_t *si, void= *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO= _ZVE64X; unsigned info =3D cpuinfo; =20 if (info) { @@ -50,6 +52,10 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |=3D CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && \ + (defined(__riscv_vector) || defined(__riscv_zve64x)) + info |=3D CPUINFO_ZVE64X; #endif left &=3D ~info; =20 @@ -69,11 +75,22 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #ifdef RISCV_HWPROBE_EXT_ZICOND info |=3D pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICO= ND : 0; left &=3D ~CPUINFO_ZICOND; +#endif + /* For rv64, V is Zve64d, a superset of Zve64x. */ + info |=3D pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : = 0; +#ifdef RISCV_HWPROBE_EXT_ZVE64X + info |=3D pair.value & RISCV_HWPROBE_EXT_ZVE64X ? CPUINFO_ZVE6= 4X : 0; #endif } } #endif /* CONFIG_ASM_HWPROBE_H */ =20 + /* + * We only detect support for vectors with hwprobe. All kernels with + * support for vectors in userspace also support the hwprobe syscall. + */ + left &=3D ~CPUINFO_ZVE64X; + if (left) { struct sigaction sa_old, sa_new; =20 @@ -113,6 +130,21 @@ unsigned __attribute__((constructor)) cpuinfo_init(voi= d) assert(left =3D=3D 0); } =20 + if (info & CPUINFO_ZVE64X) { + /* + * We are guaranteed by RVV-1.0 that VLEN is a power of 2. + * We are guaranteed by Zve64x that VLEN >=3D 64, and that + * EEW of {8,16,32,64} are supported. + */ + unsigned long vlenb; + /* csrr %0, vlenb */ + asm volatile(".insn i 0x73, 0x2, %0, zero, -990" : "=3Dr"(vlenb)); + assert(vlenb >=3D 8); + assert(is_power_of_2(vlenb)); + /* Cache VLEN in a convenient form. */ + riscv_lg2_vlenb =3D ctz32(vlenb); + } + info |=3D CPUINFO_ALWAYS; cpuinfo =3D info; return info; --=20 2.43.0