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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0dfc09sm16863485ad.236.2024.10.20.21.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 21:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1729483791; x=1730088591; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=mU9Y2091eNPkbvRh7WnNbCP4OcFDVevLfJDEfiHYXYs=; b=Xiq8INAy/BliS67UzsIB8/rzkc2Ap6cm+8GocijX5tLSlnOqskd4jn54VFB+41e7VU u1qZpUnAcXNOnaLTGjw2v3eQw8K2VAZ3dAQgYHtDzCQs1awWnIYuOKtaWdIgEFvQm+yS DcYPLqLYDGOxNuYvrLLmConuL1K2EeaehtJh0hWF/UhcYeMq6ZFi/8fsB42Lfme6Tc5m t0PC0fSjnWjOUvh7ISfVpT5eRjOMXs+xJKr9qp8P3mFf9WFxtw0D0y6f5KUbhCZn4NTo 6LmN3NaBR1TRSUAykrOioFQlRopa9vgjawFDVwuTxNuEYVv0YSqzDkh9UGfObFRnUszp uzaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729483791; x=1730088591; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mU9Y2091eNPkbvRh7WnNbCP4OcFDVevLfJDEfiHYXYs=; b=r9poTKFppG5//byjTV+nGwmPjhdSjfdufPSOSsoz1IJbiwoq1NTDoxl9tvOfov4wmU HP6YK7U+XhAnYFW2fRDk5beXFs2SF9q+JBQUbO5OUV7F8ZgA7Ls/O/dHDgYA/SJRwcPp luxDGAiyDQac8NSTOZ1SdFUdNu3hbXGox6bhejenIA0dR5vWGzhA87wwhEIqrMdvBN55 yGkCtwaMZwnRE7sGVE+AfI7qSKAcUUfDJxcJ0ViBUGpyMfSBy7lSObrEi5ZYYEuC7ZIv VEkgipW54sRRbndcbqfeptr0NU8q2HMgb3ObHc8/wHDeqZY6zAGSMXyuZQz3rtfJ5UtQ 1TGQ== X-Gm-Message-State: AOJu0YzfLc5nnN1+nd1th9sU0seGvOjt6FJdnGeqkOTosdRn1Jso2d4B eb2HUgd+d1eI7GcGLwNjYOtzghYU7Sdcka23Mt8uTtvXRb+N0VvO/q6y/8dyUpP0EYa7VCGbDRw WEJNC6f97yAL/UypvkEbRjpfXa4Hj3Z8Zzym64tv+4XtBp+5nNQNdODts374yQizrjl7DAwuDgO I/zSm2LrDLRSP0h6VS5Ghkm+HT/cJHA8Vq0w== X-Google-Smtp-Source: AGHT+IE/BycP34k2WFFt5sm+E5+LbxBaD/0Gfa0Ap8AQQEqiC7RHsdxqjFrQwJxTyCe5lTzxxTlBXQ== X-Received: by 2002:a17:903:2b04:b0:20b:ce88:1b9d with SMTP id d9443c01a7336-20e5a94effbmr154571095ad.45.1729483790842; Sun, 20 Oct 2024 21:09:50 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jim Shu Subject: [PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. Date: Mon, 21 Oct 2024 12:09:41 +0800 Message-Id: <20241021040942.400-2-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241021040942.400-1-jim.shu@sifive.com> References: <20241021040942.400-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1729483881587116600 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 8 ++++++-- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 6 files changed, 14 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 9115ecd91f..ad45bd7a6a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -293,7 +293,7 @@ out: * The FDT is fdt_packed() during the calculation. */ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, - MachineState *ms) + MachineState *ms, RISCVHartArrayState *har= ts) { int ret =3D fdt_pack(ms->fdt); hwaddr dram_end, temp; @@ -321,7 +321,11 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad= dr dram_size, * Thus, put it at an 2MB aligned address that less than fdt size from= the * end of dram or 3GB whichever is lesser. */ - temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_e= nd; + if (!riscv_is_32bit(harts)) { + temp =3D dram_end; + } else { + temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr= am_end; + } =20 return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); } diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f9a3b43d2e..ba8b0a2c26 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -519,7 +519,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) bool kernel_as_payload =3D false; target_ulong firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0); =20 /* Sanity check on RAM size */ @@ -625,7 +625,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR= AM_LO].base, memmap[MICROCHIP_PFSOC_DRAM= _LO].size, - machine); + machine, &s->soc.u_cpus); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* Load the reset vector */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9b3dcf3a7a..fd974f2357 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -519,7 +519,7 @@ static void sifive_u_machine_init(MachineState *machine) const char *firmware_name; uint32_t start_addr_hi32 =3D 0x00000000; int i; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; BlockBackend *blk; @@ -606,7 +606,7 @@ static void sifive_u_machine_init(MachineState *machine) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].bas= e, memmap[SIFIVE_U_DEV_DRAM].size, - machine); + machine, &s->soc.u_cpus); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index fceb91d946..acd7ab1ae1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -201,7 +201,7 @@ static void spike_board_init(MachineState *machine) hwaddr firmware_load_addr =3D memmap[SPIKE_DRAM].base; target_ulong kernel_start_addr; char *firmware_name; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; int i, base_hartid, hart_count; @@ -317,7 +317,7 @@ static void spike_board_init(MachineState *machine) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, memmap[SPIKE_DRAM].size, - machine); + machine, &s->soc[0]); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ee3129f3b3..cfbeeaf7d5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1399,7 +1399,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, memmap[VIRT_DRAM].size, - machine); + machine, &s->soc[0]); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 18bfe9f7bf..7ccbe5f62a 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -49,7 +49,7 @@ target_ulong riscv_load_kernel(MachineState *machine, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - MachineState *ms); + MachineState *ms, RISCVHartArrayState *har= ts); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.17.1 From nobody Tue Oct 22 22:19:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0dfc09sm16863485ad.236.2024.10.20.21.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 21:09:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1729483795; x=1730088595; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=OwVJe7wl6Df047z4n/QoSabetufigoEzxYrd+cn69aw=; b=VmyvRcgmf6B5iVq3QYy+SKUnuj4INlSXnBVUPne66WgnCWFWPuPjh6peclSPAsp9Qk bso5OgQJPbLEzDCfJIzojuAxA8++QUfKuZ8Dk+11kJALmGfK6nVLiR8xGg22DNJtmKwn I5nY4jmkZrNxqw75yMrrnksPRuyvknf5VTii5+E+0cNcJggUp9PmIpxp34KcrcfXldAg Fm5Gg/InOvDl5z3nlnVMfzoKkizUjnisqBfuXKAbZlYmfe3TAHAngD+P1EytFwR4efMY zHEODfU27f5o/N8qepVswtMqdes1AFZzpZtk2TvHrJHrbrBbfXkV9g6pGVxmfcK97AIA kVkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729483795; x=1730088595; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OwVJe7wl6Df047z4n/QoSabetufigoEzxYrd+cn69aw=; b=XgT1hZXaNm75hIPgNyLuT3jSu8x4A1tbnK4lDtxCxdLD0suqCsDedgch151HmCUNPC +YsqeSKeOFvGzc4TRDlniNQiulI034JS6HlOQLyowQcgk5ecrmSUQO7D/4bqY6b6xYCm 8K3hmMQaYt/aV34O8Txa82mZK+qjrvKA8Hr6N0uM/KX0VAwVma4fnHAR454lhaWKppSG aS28dSTZuq1QwhtSURfavUpb7hvK+yCgL5HTKvPKhk/zFOM0LnHZqD/BmfSNfTiUcDc5 lQd08kq0pJWdnXVbK1z1/b8Nu19sYARU3JmLugeYISPGNoJj6NU0X8zl9UWmJCeKILJy odMg== X-Gm-Message-State: AOJu0Yyv2czcJA4P9y8b/WiwNBFQxqQ13oqNmY8lWE+VCZGDziqBwS7b bxq7yE2295aYVnYWN6dYgRGVOCkEIGckyHsC1ddFEoBb+1Trkjln5jPcjd2yTRRkb54TA+pj1/0 pNB0ERefbUFb1nQQWmSJfbeM5H0XKGQLbZ1HFzFDkmAhiaBz+nCz1qsuTsKL6mRdHFf5mazgPuV ZCRlKd6iJEafHxGQkP73WEcXNNX6nM5vRZgg== X-Google-Smtp-Source: AGHT+IEYScQBVVlOFS2dVqmQWINMu2ecqVajApJTE975BxkebBmnPbcyBq5J1gXMVMe85A0RVjEVHg== X-Received: by 2002:a17:902:f9cc:b0:20c:9ecd:11c2 with SMTP id d9443c01a7336-20e5a95025amr125265865ad.55.1729483794962; Sun, 20 Oct 2024 21:09:54 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jim Shu Subject: [PATCH 2/2] hw/riscv: Support different address-cells for initrd Date: Mon, 21 Oct 2024 12:09:42 +0800 Message-Id: <20241021040942.400-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241021040942.400-1-jim.shu@sifive.com> References: <20241021040942.400-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1729483873450116600 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The cells of 'initrd-start/end' should follow the '#address-cell'. QEMU API could support 1 and 2 cells. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ad45bd7a6a..76b099c696 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -182,6 +182,7 @@ static void riscv_load_initrd(MachineState *machine, ui= nt64_t kernel_entry) void *fdt =3D machine->fdt; hwaddr start, end; ssize_t size; + uint32_t acells; =20 g_assert(filename !=3D NULL); =20 @@ -209,9 +210,18 @@ static void riscv_load_initrd(MachineState *machine, u= int64_t kernel_entry) =20 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ if (fdt) { + acells =3D qemu_fdt_getprop_cell(fdt, "/", "#address-cells", + NULL, NULL); + if (acells =3D=3D 0) { + error_report("dtb file invalid (#address-cells 0)"); + exit(1); + } + end =3D start + size; - qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end); + qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", + acells, start); + qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", + acells, end); } } =20 --=20 2.17.1