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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad368b25sm2348846a91.24.2024.10.20.20.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 20:04:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1729479853; x=1730084653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KWU/3HvbiuQXxAimlZ1VWI57uUkGUzFGIFx/JvTQ+9I=; b=Y1JobNPpu+29+CfSG6kzBz8xq5h0tcg14C6TwTCiYLKX/N2oJKw9LBo+WTAGFMc+SH yF7ZiiF/dTOCA1ne8aNZAAH1T9dqQV2QHYv/KeSYdPLzpjciZCyVdpU6aBDRcfFHimcf 43g4c/pGgN5vCEQ3ypWyh0QSlAulIONFQKZcVJxXahvs5Czqr97FcwwPRkv0KKpMlKNA BgIPFLDm7sp8HA2gmghCTe0pqTxTGNcDEvugrXfKeJE95RucBISBpehTyU9VswY1Rgdf JHMUrFfyfEIEiJdPR20K7A4348TnJIgdTyg8EsxDYaX/tyDAobDcIlMVNWLla08yEljV OS1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729479853; x=1730084653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KWU/3HvbiuQXxAimlZ1VWI57uUkGUzFGIFx/JvTQ+9I=; b=q2ivuQvzGIFK/dzdRrSDHEgSGDg0NJttJkV/9YDQIvap1bVmQ6jcoyv/KYtp61I7EI FAw1fxWQ6ObpVxL5vi2eSk7PATke55PezhqDy07VNlDQFBUaWxR4ptD7htQk84QM9xEt rPxq4uehBPxmsFQYNNLRKt/7puiasXiRZ1foNzkp4zGwC4JjTNNBy+qCrz9kkYNlOwsI OPN3etdEgL4FnzsaI9E6nUzG/hfwzRLCsbueiJtZY1QH4zRO54NWqhVmvv85KEP5D9zG zPN3uym4A6U6XeqiVN42dszaYd0ZKDoTltKYiVTsf5Gh4dx/sWwWxJzhW8g/DN8BYymu 6qcw== X-Gm-Message-State: AOJu0YyZZ3Qtvpz2JdOVvz/rBLKDhJ613zHT685Wqb4lgoxjbFFchrGq Go1UTkV5Qa/4/SL3y6oav86St7xOaqwzoxy7AZhBwtSUFw0t09ieZeMXzm10d8rdtYI0TWyeN5n 4eab7ebS/3/qrM3HTuRnUmgFlDNL4xXdeXer6xvLnIZyMsXxN78bErsY3166F/kIYd+Ey9jBhN5 +jkj6qkdbU6bD5CV32vWmGMB/01ftFfgurPviCs7g= X-Google-Smtp-Source: AGHT+IFQfood6RU515V/uljOiR7lPkvKQdGMkQbvKa2Ad1cITdchlq1QU5OkhfebASGh0LC76WZJgw== X-Received: by 2002:a17:90b:1d85:b0:2e2:b937:eeae with SMTP id 98e67ed59e1d1-2e5616db601mr12976323a91.5.1729479853079; Sun, 20 Oct 2024 20:04:13 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Tommy Wu , Frank Chang Subject: [PATCH v8 3/5] target/riscv: Add Smrnmi CSRs Date: Mon, 21 Oct 2024 11:03:56 +0800 Message-ID: <20241021030358.12454-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241021030358.12454-1-frank.chang@sifive.com> References: <20241021030358.12454-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1729479896406116600 Content-Type: text/plain; charset="utf-8" From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5ce6ed31ec..b3195da512 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1017,6 +1017,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) riscv_trigger_reset_hold(env); } =20 + if (cpu->cfg.ext_smrnmi) { + env->rnmip =3D 0; + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b2a863c50..832556cc34 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,10 @@ struct CPUArchState { #endif /* CONFIG_KVM */ =20 /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; target_ulong rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6df2cbc2be..1a5200d1d5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -350,6 +350,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf =20 +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -627,6 +633,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c88ee1265e..b84b436151 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -578,6 +578,17 @@ static RISCVException debug(CPURISCVState *env, int cs= rno) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 static RISCVException seed(CPURISCVState *env, int csrno) @@ -4566,6 +4577,67 @@ static RISCVException write_upmbase(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |=3D MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus =3D (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif =20 /* Crypto Extension */ @@ -5070,6 +5142,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* RNMI */ + [CSR_MNSCRATCH] =3D { "mnscratch", rnmi, read_mnscratch, write_mnscrat= ch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNEPC] =3D { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNCAUSE] =3D { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNSTATUS] =3D { "mnstatus", rnmi, read_mnstatus, write_mnstatu= s, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.43.2