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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad368b25sm2348846a91.24.2024.10.20.20.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 20:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1729479851; x=1730084651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0wnbYsxdZ7UPiClYf+4uY8I2hYOFKcpcPA8dpzgFenk=; b=XMi9RSvBhHJbU8ZC4HnHUGirqhueDuYQWjc2f9RfGJQOCAg8t66itAVRC6RSqcGjvU j3jg2KMS0tgIb7H8EoIAlRqPYHCB1zhRzDvwbwH3H83xDhmm3wNzlFXDHp7pVeBhaS4W WeL6faqeUESzhL1dfFeivxRV3+5VeacG4UjF9K9v5aU1vY9HRZU3tLxppDO3RZe5D4O7 ViyBS6Fdl7b3tQU32Z03ojnZTBOr4+QMXiGkAYIbErd90ZoAcMEYFTo9f263dFEcROH/ VzFOqgy2dt7VRj8s01yKR67rWhv8geOS83UP3tkXwJGwrJGyQhn+qGerjtCyJFeCds2R eYLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729479851; x=1730084651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0wnbYsxdZ7UPiClYf+4uY8I2hYOFKcpcPA8dpzgFenk=; b=HEbT21e/E06yRstb3pCxgYv8JCivUXjYgnVgC2DevLv9ZoF9jZQiMay27W1U5/Y5Oj Y7XvfAZ/1GYNd46k6aKF20IbO3uPsk8CMIZtTcvfmAzflAH3aK3JKPFMYAzK5YFzOAv2 TKEV2/OsP4rBnA+eoApZEBQVa3SVcXCcQ+8nEddZ8PVOs4ZzSooMxkjI5GaboQtC8SZN m/fjtUY+sLR/cPI7cvcPG0iaNCNNG3EVqKEBoEFO8QI/DarC7bHUIYCjR/y4rLvmAuWG lQrVH8hg1KEs5Zj4FjJ7aGMc9jWOesdF8CXFldnqB07rPMP2/HDGpsGdGqLG0noflOrU C9UA== X-Gm-Message-State: AOJu0YwLtYpTJHDSmQuusgJ7MyHY0mo9w1WRzIra1UgmajUcIaMD7ebT 7I8OGZeIgf+N7lmHKiKXHdH0Dwulbzxhd2Ld6byTvWJP6lpFeN1nYIknhw7Dd9fcfwjOqF5Zf8r 0XbNQxI1dtEI/eHNw2oCPNausJUjQFq7ji0Hrei4w4CF9zZD726QIrMCeyAa/oDCHe68jTSyz7p L+6pQ6/SNPKB87r/j0WROKaGkqmZ4pvLLkDuFZOas= X-Google-Smtp-Source: AGHT+IE4D91fsn//KsYw9AGTGZbORAJkAnU57ZBXhp7c4yu3tlL8JvVMGaIIxuKZJ54xwfJbho0+Kg== X-Received: by 2002:a17:90a:bc2:b0:2e2:e545:82c5 with SMTP id 98e67ed59e1d1-2e5615c770bmr11470063a91.3.1729479850436; Sun, 20 Oct 2024 20:04:10 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Tommy Wu , Frank Chang Subject: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception Date: Mon, 21 Oct 2024 11:03:55 +0800 Message-ID: <20241021030358.12454-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241021030358.12454-1-frank.chang@sifive.com> References: <20241021030358.12454-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1729479978805116600 From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the prope= rty of the harts. It=E2=80=99s very easy for users to set the address based on = their expectation. This patch also adds the functionality to handle the RNMI sign= als. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 18 ++++++++ include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c | 11 +++++ target/riscv/cpu.h | 6 +++ target/riscv/cpu_bits.h | 12 +++++ target/riscv/cpu_helper.c | 82 ++++++++++++++++++++++++++++++++--- 6 files changed, 128 insertions(+), 5 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..b7d73f7a82 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -33,6 +33,12 @@ static Property riscv_harts_props[] =3D { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, + uint64_t), + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, + uint64_t), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -47,6 +53,18 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, i= nt idx, { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); + if (s->harts[idx].cfg.ext_smrnmi) { + if (s->rnmi_irqvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-interrupt-vector", + s->rnmi_irqvec[idx]); + } + if (s->rnmi_excpvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-exception-vector", + s->rnmi_excpvec[idx]); + } + } s->harts[idx].env.mhartid =3D s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 912b4a2682..a6ed73a195 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,10 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint32_t num_rnmi_irqvec; + uint64_t *rnmi_irqvec; + uint32_t num_rnmi_excpvec; + uint64_t *rnmi_excpvec; RISCVCPU *harts; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a78cd639b..5ce6ed31ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1297,6 +1297,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) g_assert_not_reached(); } } + +static void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); +} #endif /* CONFIG_USER_ONLY */ =20 static bool riscv_cpu_is_dynamic(Object *cpu_obj) @@ -1320,6 +1325,8 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ =20 general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); @@ -2670,6 +2677,10 @@ static Property riscv_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), #endif =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a63a29744c..8b2a863c50 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -472,6 +472,11 @@ struct CPUArchState { uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; #endif /* CONFIG_KVM */ + + /* RNMI */ + target_ulong rnmip; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; }; =20 /* @@ -568,6 +573,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7e3f629356..6df2cbc2be 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -662,6 +662,12 @@ typedef enum { /* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 =20 +/* Default RNMI Interrupt Vector address */ +#define DEFAULT_RNMI_IRQVEC 0x0 + +/* Default RNMI Exception Vector address */ +#define DEFAULT_RNMI_EXCPVEC 0x0 + /* Exception causes */ typedef enum RISCVException { RISCV_EXCP_NONE =3D -1, /* sentinel value */ @@ -711,6 +717,9 @@ typedef enum RISCVException { /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 +/* RNMI causes */ +#define RNMI_MAX 16 + /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) @@ -942,6 +951,9 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 =20 +/* RISC-V-specific interrupt pending bits. */ +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 + /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 203c0a92ab..977bf97c16 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -434,6 +434,18 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) uint64_t vsbits, irq_delegated; int virq; =20 + /* Priority: RNMI > Other interrupt. */ + if (riscv_cpu_cfg(env)->ext_smrnmi) { + /* If mnstatus.NMIE =3D=3D 0, all interrupts are disabled. */ + if (!get_field(env->mnstatus, MNSTATUS_NMIE)) { + return RISCV_EXCP_NONE; + } + + if (env->rnmip) { + return ctz64(env->rnmip); /* since non-zero */ + } + } + /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { mie =3D 1; @@ -496,7 +508,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - if (interrupt_request & CPU_INTERRUPT_HARD) { + uint32_t mask =3D CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI; + + if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int interruptno =3D riscv_cpu_local_irq_pending(env); @@ -619,6 +633,30 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) env->geilen =3D geilen; } =20 +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) +{ + CPURISCVState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + bool release_lock =3D false; + + if (!bql_locked()) { + release_lock =3D true; + bql_lock(); + } + + if (level) { + env->rnmip |=3D 1 << irq; + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); + } else { + env->rnmip &=3D ~(1 << irq); + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); + } + + if (release_lock) { + bql_unlock(); + } +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env =3D &cpu->env; @@ -1661,6 +1699,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool virt =3D env->virt_enabled; bool write_gva =3D false; uint64_t s; + int mode; =20 /* * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -1679,6 +1718,23 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong mtval2 =3D 0; int sxlen =3D 0; int mxlen =3D 0; + bool nnmi_excep =3D false; + + if (cpu->cfg.ext_smrnmi && env->rnmip && async) { + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, + env->virt_enabled); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, + env->priv); + env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BITS - = 1)); + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_mode(env, PRV_M, false); + + return; + } =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1766,8 +1822,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && cause < 64 && - (((deleg >> cause) & 1) || s_injected || vs_injected)) { + mode =3D env->priv <=3D PRV_S && cause < 64 && + (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; + + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; @@ -1845,8 +1903,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval =3D tval; env->mtval2 =3D mtval2; env->mtinst =3D tinst; - env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nnmi_excep =3D cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; + + if (nnmi_excep) { + env->pc =3D env->rnmi_excpvec; + } else { + env->pc =3D (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : = 0); + } riscv_cpu_set_mode(env, PRV_M, virt); } =20 --=20 2.43.2