From nobody Tue Oct 22 22:21:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1729479944; cv=none; d=zohomail.com; s=zohoarc; b=M1UXJYlS1hur2s0KVZLw+VSMk3gh21IUpSYlZPmQPKJsUmn6J3eXgJ7Pvtko5lri6G7gtuotqU0TKVj26I/JdeT/fsCArry1KR37T4iOxfv0YJS/8on76t3IL8LcNb/0I0+C1z6a1UCbRFpNyng72fJ2o4VLb8E3chpmaUFMuzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729479944; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QlLGdc5fIPn5eaknq6/MET9nRw789lZrt09kcp9138w=; b=cgc1LgvbQLI+2dp/HcNoV3VHSs+4Okp/UzN2u9MDzNvriWWTf4zauSVmJqvdqgPWJ0eSJlxNBwEKr92BSWu5h1/57Hby7zG8K7B4I+cLREwh06aXaMbKCjA+x1Glvec3KJvcyec9k0aPlr1YyyxSnJXOpLG37xGR+FXP/OeXLu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172947994468018.3272359799646; Sun, 20 Oct 2024 20:05:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t2iiL-0004zO-An; Sun, 20 Oct 2024 23:04:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t2iiJ-0004yf-Vv for qemu-devel@nongnu.org; Sun, 20 Oct 2024 23:04:12 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t2iiI-00074W-Id for qemu-devel@nongnu.org; Sun, 20 Oct 2024 23:04:11 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2e30fb8cb07so2891259a91.3 for ; Sun, 20 Oct 2024 20:04:10 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad368b25sm2348846a91.24.2024.10.20.20.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 20:04:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1729479848; x=1730084648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QlLGdc5fIPn5eaknq6/MET9nRw789lZrt09kcp9138w=; b=HMQX2e5IIY/yO7K8cfglbFXMsrhWOJBRqBEaF2ArXjVCUd0Hs580XeIhWFnFFEX5Sc hdl8/Bhzr3txPNHhbNFiLNscXcUh0pvn/tLqKDGB4y8Gam9ZljvwjKsVUKlKsc50MRcC gnSWiCd0ulduypmUvMA175pZBvr/PxXiO84sCepb2kjXDXHEwpX4ac2UakfmhDBuKuWb C+0EHuqUjjAU3yWerh7xudOcW6/hAIZStXL/KqDnN6v2UGHlAQYZ70Zl/0JnAqUUQyy5 QJqbq8rEtayocNBaPeVOeZTHVc6WL7btvxI7phuQ5+G2ReG5P5tR/+Q4uGxwbJigZmcq BOZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729479848; x=1730084648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QlLGdc5fIPn5eaknq6/MET9nRw789lZrt09kcp9138w=; b=FHsRDKPbC7ZhxV86S7450Xs4h3/usOpmzjwJhm2ynb/rrPUJimCPDAWsP9FVANT97F gU5E9m+gb2nTXV/m1lT0hjdU84LjXJwphNhn1qQcrk7VtUmkBddAcE4cPjKUDmVa6wwB vPMqYeaIPv+zvyyVC2g27q/RDyfSi9CNXxUdmFBPrOWz09uV85+/fRD7bxGldotbykl1 UeJiBh7b70Mea0/jN1AxsvWMbvfgSWSo3lSs6w2ZykGzc54XGoskIXGM58vR7igVEKtz RyiDBnNisF1wLbm9sd1AiwYrCBgUP0XnMfGdGB295WF2o7ylWxK0ZXSWzuNIFGhSKqHZ IW8Q== X-Gm-Message-State: AOJu0Yw4+KRZ+MN9PNX2qTsf+bNXDLhk8w7+tBtGjkqIeQm8kwZ7Z+ny B2kempctDE6FdnKjJ+xdAIcQQ3PTGHQkKBAwxNLEH1eabbXghBftNKlSRH0wFLTb2MJGskbsMK0 7TfGX0ZlT/RsamS3GBh/UWwQzpIg5XJNaIcVm270I7rWoKjB1vkWZZ8FUpUgxRiVNEgfP/uLjSE AbOiAjoI6HUt24+l8wqd/5KkdiwCBli2mkKTCcZOE= X-Google-Smtp-Source: AGHT+IHwchW//LRjffYqpbmWDHk9Gb8drNRRIThjZ/1kv51L72i4PcFee28mqIyhkykNFa6sK3ZorQ== X-Received: by 2002:a17:90a:c08d:b0:2e2:bbcd:6cbb with SMTP id 98e67ed59e1d1-2e5616db70dmr10571635a91.6.1729479848001; Sun, 20 Oct 2024 20:04:08 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Tommy Wu , Frank Chang Subject: [PATCH v8 1/5] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig Date: Mon, 21 Oct 2024 11:03:54 +0800 Message-ID: <20241021030358.12454-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241021030358.12454-1-frank.chang@sifive.com> References: <20241021030358.12454-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1729479946681116600 Content-Type: text/plain; charset="utf-8" From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 355afedfd3..092744360e 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -126,6 +126,7 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_smrnmi; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl; --=20 2.43.2 From nobody Tue Oct 22 22:21:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1729479976; cv=none; d=zohomail.com; s=zohoarc; b=ecm26Egv2SfTueW1Tl8BaIi9K5OwJrPx4nV7K9Hx7toi5OZU92haFIfPeSc2EjTUCrJmqxtcYUbbddoEYCzFqhwnjjO6Bti5OSjCiFGhiAbUmfCCYPewgl8ki14isaOIxBGzXMlCny4ympnIpvr34ca1dgyAGRlyMtX+4dYrfNU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729479976; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0wnbYsxdZ7UPiClYf+4uY8I2hYOFKcpcPA8dpzgFenk=; b=AU8NSke3Ysn0QngIjp/Dqwjh+THfIdqIRi9nAAD/0mQ/4XcbFDEBitJgX6XStuLqfBFWLJtM+XC7bnA0x6AE1e3Hh8/h+/Fc2RCQ9pYQ+pGY/6pm0vrMws39hmK2SNBlq6Llar5JJg+6EtxpokD4KHaJyJHNuUFkRLDP9WPR8H8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729479976811123.36775846818091; Sun, 20 Oct 2024 20:06:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t2iiP-000515-1I; Sun, 20 Oct 2024 23:04:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t2iiM-0004zr-UF for qemu-devel@nongnu.org; Sun, 20 Oct 2024 23:04:14 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t2iiK-00075R-PL for qemu-devel@nongnu.org; Sun, 20 Oct 2024 23:04:14 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2e2e88cb0bbso2867954a91.3 for ; Sun, 20 Oct 2024 20:04:12 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad368b25sm2348846a91.24.2024.10.20.20.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 20:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1729479851; x=1730084651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0wnbYsxdZ7UPiClYf+4uY8I2hYOFKcpcPA8dpzgFenk=; b=XMi9RSvBhHJbU8ZC4HnHUGirqhueDuYQWjc2f9RfGJQOCAg8t66itAVRC6RSqcGjvU j3jg2KMS0tgIb7H8EoIAlRqPYHCB1zhRzDvwbwH3H83xDhmm3wNzlFXDHp7pVeBhaS4W WeL6faqeUESzhL1dfFeivxRV3+5VeacG4UjF9K9v5aU1vY9HRZU3tLxppDO3RZe5D4O7 ViyBS6Fdl7b3tQU32Z03ojnZTBOr4+QMXiGkAYIbErd90ZoAcMEYFTo9f263dFEcROH/ VzFOqgy2dt7VRj8s01yKR67rWhv8geOS83UP3tkXwJGwrJGyQhn+qGerjtCyJFeCds2R eYLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729479851; x=1730084651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0wnbYsxdZ7UPiClYf+4uY8I2hYOFKcpcPA8dpzgFenk=; b=HEbT21e/E06yRstb3pCxgYv8JCivUXjYgnVgC2DevLv9ZoF9jZQiMay27W1U5/Y5Oj Y7XvfAZ/1GYNd46k6aKF20IbO3uPsk8CMIZtTcvfmAzflAH3aK3JKPFMYAzK5YFzOAv2 TKEV2/OsP4rBnA+eoApZEBQVa3SVcXCcQ+8nEddZ8PVOs4ZzSooMxkjI5GaboQtC8SZN m/fjtUY+sLR/cPI7cvcPG0iaNCNNG3EVqKEBoEFO8QI/DarC7bHUIYCjR/y4rLvmAuWG lQrVH8hg1KEs5Zj4FjJ7aGMc9jWOesdF8CXFldnqB07rPMP2/HDGpsGdGqLG0noflOrU C9UA== X-Gm-Message-State: AOJu0YwLtYpTJHDSmQuusgJ7MyHY0mo9w1WRzIra1UgmajUcIaMD7ebT 7I8OGZeIgf+N7lmHKiKXHdH0Dwulbzxhd2Ld6byTvWJP6lpFeN1nYIknhw7Dd9fcfwjOqF5Zf8r 0XbNQxI1dtEI/eHNw2oCPNausJUjQFq7ji0Hrei4w4CF9zZD726QIrMCeyAa/oDCHe68jTSyz7p L+6pQ6/SNPKB87r/j0WROKaGkqmZ4pvLLkDuFZOas= X-Google-Smtp-Source: AGHT+IE4D91fsn//KsYw9AGTGZbORAJkAnU57ZBXhp7c4yu3tlL8JvVMGaIIxuKZJ54xwfJbho0+Kg== X-Received: by 2002:a17:90a:bc2:b0:2e2:e545:82c5 with SMTP id 98e67ed59e1d1-2e5615c770bmr11470063a91.3.1729479850436; Sun, 20 Oct 2024 20:04:10 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Tommy Wu , Frank Chang Subject: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception Date: Mon, 21 Oct 2024 11:03:55 +0800 Message-ID: <20241021030358.12454-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241021030358.12454-1-frank.chang@sifive.com> References: <20241021030358.12454-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1729479978805116600 From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the prope= rty of the harts. It=E2=80=99s very easy for users to set the address based on = their expectation. This patch also adds the functionality to handle the RNMI sign= als. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 18 ++++++++ include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c | 11 +++++ target/riscv/cpu.h | 6 +++ target/riscv/cpu_bits.h | 12 +++++ target/riscv/cpu_helper.c | 82 ++++++++++++++++++++++++++++++++--- 6 files changed, 128 insertions(+), 5 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..b7d73f7a82 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -33,6 +33,12 @@ static Property riscv_harts_props[] =3D { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, + uint64_t), + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, + uint64_t), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -47,6 +53,18 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, i= nt idx, { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); + if (s->harts[idx].cfg.ext_smrnmi) { + if (s->rnmi_irqvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-interrupt-vector", + s->rnmi_irqvec[idx]); + } + if (s->rnmi_excpvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-exception-vector", + s->rnmi_excpvec[idx]); + } + } s->harts[idx].env.mhartid =3D s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 912b4a2682..a6ed73a195 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,10 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint32_t num_rnmi_irqvec; + uint64_t *rnmi_irqvec; + uint32_t num_rnmi_excpvec; + uint64_t *rnmi_excpvec; RISCVCPU *harts; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a78cd639b..5ce6ed31ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1297,6 +1297,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) g_assert_not_reached(); } } + +static void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); +} #endif /* CONFIG_USER_ONLY */ =20 static bool riscv_cpu_is_dynamic(Object *cpu_obj) @@ -1320,6 +1325,8 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ =20 general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); @@ -2670,6 +2677,10 @@ static Property riscv_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), #endif =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a63a29744c..8b2a863c50 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -472,6 +472,11 @@ struct CPUArchState { uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; #endif /* CONFIG_KVM */ + + /* RNMI */ + target_ulong rnmip; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; }; =20 /* @@ -568,6 +573,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7e3f629356..6df2cbc2be 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -662,6 +662,12 @@ typedef enum { /* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 =20 +/* Default RNMI Interrupt Vector address */ +#define DEFAULT_RNMI_IRQVEC 0x0 + +/* Default RNMI Exception Vector address */ +#define DEFAULT_RNMI_EXCPVEC 0x0 + /* Exception causes */ typedef enum RISCVException { RISCV_EXCP_NONE =3D -1, /* sentinel value */ @@ -711,6 +717,9 @@ typedef enum RISCVException { /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 +/* RNMI causes */ +#define RNMI_MAX 16 + /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) @@ -942,6 +951,9 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 =20 +/* RISC-V-specific interrupt pending bits. */ +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 + /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 203c0a92ab..977bf97c16 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -434,6 +434,18 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) uint64_t vsbits, irq_delegated; int virq; =20 + /* Priority: RNMI > Other interrupt. */ + if (riscv_cpu_cfg(env)->ext_smrnmi) { + /* If mnstatus.NMIE =3D=3D 0, all interrupts are disabled. */ + if (!get_field(env->mnstatus, MNSTATUS_NMIE)) { + return RISCV_EXCP_NONE; + } + + if (env->rnmip) { + return ctz64(env->rnmip); /* since non-zero */ + } + } + /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { mie =3D 1; @@ -496,7 +508,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - if (interrupt_request & CPU_INTERRUPT_HARD) { + uint32_t mask =3D CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI; + + if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int interruptno =3D riscv_cpu_local_irq_pending(env); @@ -619,6 +633,30 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) env->geilen =3D geilen; } =20 +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) +{ + CPURISCVState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + bool release_lock =3D false; + + if (!bql_locked()) { + release_lock =3D true; + bql_lock(); + } + + if (level) { + env->rnmip |=3D 1 << irq; + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); + } else { + env->rnmip &=3D ~(1 << irq); + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); + } + + if (release_lock) { + bql_unlock(); + } +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env =3D &cpu->env; @@ -1661,6 +1699,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool virt =3D env->virt_enabled; bool write_gva =3D false; uint64_t s; + int mode; =20 /* * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -1679,6 +1718,23 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong mtval2 =3D 0; int sxlen =3D 0; int mxlen =3D 0; + bool nnmi_excep =3D false; + + if (cpu->cfg.ext_smrnmi && env->rnmip && async) { + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, + env->virt_enabled); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, + env->priv); + env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BITS - = 1)); + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_mode(env, PRV_M, false); + + return; + } =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1766,8 +1822,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && cause < 64 && - (((deleg >> cause) & 1) || s_injected || vs_injected)) { + mode =3D env->priv <=3D PRV_S && cause < 64 && + (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; + + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; @@ -1845,8 +1903,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval =3D tval; env->mtval2 =3D mtval2; env->mtinst =3D tinst; - env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nnmi_excep =3D cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; + + if (nnmi_excep) { + env->pc =3D env->rnmi_excpvec; + } else { + env->pc =3D (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : = 0); + } riscv_cpu_set_mode(env, PRV_M, virt); } =20 --=20 2.43.2 From nobody Tue Oct 22 22:21:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1729479895; cv=none; d=zohomail.com; s=zohoarc; b=AGLLosPDaQIBLNNL+ZqCrdASVa+AG83Q/t/qT+Z8vb2sG0uRt5l3pyoOD6MVzV3mnq8VI5iwBPwluNDZjQ9s1WDeLpPIeSYahf07SBETf0C9/je2ortPvyzZ00FrGVPPPw2PvCuIQ7kr/Zp/k/Yc10e20a4fJZ53+jNCvUTPqBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1729479895; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KWU/3HvbiuQXxAimlZ1VWI57uUkGUzFGIFx/JvTQ+9I=; b=Hn0I5sqFuJV5xBQgRy61UbN2BaVy+tV/V3PlhzC7anr0H2+0KHC4TJSJJpWLvxIWAG4MCdanjG1aqmrkmmzR61hlnAeJ7/UN4mtly90PwcqQ+ogvKFzTjLc5Q4LPLqVBLrWHPe+FPRyph+1LVUymoeC92Rh8z9WkycmaA/LmIJQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1729479895190896.2558580896425; Sun, 20 Oct 2024 20:04:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t2iiQ-00051U-Th; Sun, 20 Oct 2024 23:04:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t2iiO-000510-SH for qemu-devel@nongnu.org; Sun, 20 Oct 2024 23:04:16 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t2iiN-00076P-5k for qemu-devel@nongnu.org; Sun, 20 Oct 2024 23:04:16 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2e2dcf4b153so2898958a91.1 for ; Sun, 20 Oct 2024 20:04:14 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. 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Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5ce6ed31ec..b3195da512 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1017,6 +1017,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) riscv_trigger_reset_hold(env); } =20 + if (cpu->cfg.ext_smrnmi) { + env->rnmip =3D 0; + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b2a863c50..832556cc34 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,10 @@ struct CPUArchState { #endif /* CONFIG_KVM */ =20 /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; target_ulong rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6df2cbc2be..1a5200d1d5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -350,6 +350,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf =20 +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -627,6 +633,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c88ee1265e..b84b436151 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -578,6 +578,17 @@ static RISCVException debug(CPURISCVState *env, int cs= rno) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 static RISCVException seed(CPURISCVState *env, int csrno) @@ -4566,6 +4577,67 @@ static RISCVException write_upmbase(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |=3D MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus =3D (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif =20 /* Crypto Extension */ @@ -5070,6 +5142,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* RNMI */ + [CSR_MNSCRATCH] =3D { "mnscratch", rnmi, read_mnscratch, write_mnscrat= ch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNEPC] =3D { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNCAUSE] =3D { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNSTATUS] =3D { "mnstatus", rnmi, read_mnstatus, write_mnstatu= s, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.43.2 From nobody Tue Oct 22 22:21:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 20 +++++++++ target/riscv/op_helper.c | 45 ++++++++++++++++--- 4 files changed, 64 insertions(+), 5 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 451261ce5a..16ea240d26 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c45b8fa1d8..d320631e8c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -121,6 +121,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index bc5263a4e0..b51f30846d 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -18,6 +18,12 @@ * this program. If not, see . */ =20 +#define REQUIRE_SMRNMI(ctx) do { \ + if (!ctx->cfg_ptr->ext_smrnmi) { \ + return false; \ + } \ +} while (0) + static bool trans_ecall(DisasContext *ctx, arg_ecall *a) { /* always generates U-level ECALL, fixed in do_interrupt handler */ @@ -106,6 +112,20 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + REQUIRE_SMRNMI(ctx); + decode_save_opc(ctx); + gen_helper_mnret(cpu_pc, tcg_env); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 25a5263573..180886f32a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -312,24 +312,30 @@ target_ulong helper_sret(CPURISCVState *env) return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env) +static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, + target_ulong prev_priv) { if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - target_ulong retpc =3D env->mepc; if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - uint64_t mstatus =3D env->mstatus; - target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); - if (riscv_cpu_cfg(env)->pmp && !pmp_get_num_rules(env) && (prev_priv !=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } +} + +target_ulong helper_mret(CPURISCVState *env) +{ + target_ulong retpc =3D env->mepc; + uint64_t mstatus =3D env->mstatus; + target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); + + check_ret_from_m_mode(env, retpc, prev_priv); =20 target_ulong prev_virt =3D get_field(env->mstatus, MSTATUS_MPV) && (prev_priv !=3D PRV_M); @@ -353,6 +359,35 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } =20 +target_ulong helper_mnret(CPURISCVState *env) +{ + target_ulong retpc =3D env->mnepc; + target_ulong prev_priv =3D get_field(env->mnstatus, MNSTATUS_MNPP); + target_ulong prev_virt; + + check_ret_from_m_mode(env, retpc, prev_priv); + + prev_virt =3D get_field(env->mnstatus, MNSTATUS_MNPV) && + (prev_priv !=3D PRV_M); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, true); + + /* + * If MNRET changes the privilege mode to a mode + * less privileged than M, it also sets mstatus.MPRV to 0. + */ + if (prev_priv < PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, false); + } + + if (riscv_has_ext(env, RVH) && prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_mode(env, prev_priv, prev_virt); + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.43.2 From nobody Tue Oct 22 22:21:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; 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Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3195da512..fed64741d1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), @@ -1502,6 +1503,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { =20 MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), --=20 2.43.2