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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e77371193sm4859580b3a.21.2024.10.17.07.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 07:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1729176790; x=1729781590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y7VKEtn5rFJqEDMMyFqWRlHYBbefKBg0QW1klzQG6OU=; b=RSMZMMkh00P9Y3qx5g/rKzLE/Y7xljqx+GqH/F5+lzGsbme7049eIDBSc6RdkDaRmy wsePWAbr5YGGaCADxAPeN84RRFbZJ/GDZtNi0/M3BVkr8F7FxZaaOJu7KJAF+7jIPmQI FkiY0ZS2gpXnOPQVHwGahlnkUBzSbrhodMhTwQtvkR+jC5pRVO4kJYsQWklaSZBCHYr4 59sYC3cUVMwHQnOkEtP6FzRBG9Lfv2oXcrSKs9r2J3KVAU9urqpPoMDiYXCqwrrwMW05 wTgCvHfJYtDkUMnHkDOLVDk6e0t1FSehrL8k0Ef0sgw61NWObkMeEWhga6HBf/GZwwgB 6Mjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729176790; x=1729781590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y7VKEtn5rFJqEDMMyFqWRlHYBbefKBg0QW1klzQG6OU=; b=uDUHfj4yQFEgRdK2if7GSNvhAlNIxZutnuhZdfZtewIE/m/Jycr0wi0upJoaOnz+vI 8F2Ob+Ga0MMe9MSprNK5SIILFXbqjKWC9+UZDMbp62Le/OOjYeQ5gWWA7gM48EYqriZH p+cTVgWCm3QrWQmgeAdYK3H0u6UgwqNaW1n8behxX3pVP9xiEOaAI/72PKRhOn/aOC8y ed0vvdZBxBcmJbXtx1fElMgxph6tlk7RmrfZArAp9uACeRJ1d0m4Im3HxTuRxhiPKEyG Vduv3JQ3nQzx7WkmY1xw994PwAHYcLbXLWbSo2PlaHzUk16j9tMJFx3bjNYv7x4QiHNv iGnA== X-Forwarded-Encrypted: i=1; AJvYcCVs/MaHJpv7U5CaRZrrUCdMTPsTJ2LWfnQr9xjcVaK1WFp56ochKVgdBOXH8KBop1tEUmVAaWO7JTfK@nongnu.org X-Gm-Message-State: AOJu0Yyiqx23FbWkUfJRD9UHAmRGsK4Sk92Sv4qinzS0JPnKU/klSEab by1AZyCR0LBwI7OKasAl7tF23yGpTX+zrIIX9JH3wdGHI/LrfIAGRFXLhbVXNw8= X-Google-Smtp-Source: AGHT+IGaabGoe7Tp+cIaz7g8YGp0MIzjHfN+JbTmJ182ibOh54/kw4xjwOMFUjVI2cfJrv0KyYJHKA== X-Received: by 2002:a05:6a21:150d:b0:1d4:e638:d066 with SMTP id adf61e73a8af0-1d905e99a93mr12398090637.6.1729176790404; Thu, 17 Oct 2024 07:53:10 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v4 4/9] target/riscv: Implement Ssdbltrp exception handling Date: Thu, 17 Oct 2024 16:52:15 +0200 Message-ID: <20241017145226.365825-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241017145226.365825-1-cleger@rivosinc.com> References: <20241017145226.365825-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=cleger@rivosinc.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1729176828525116600 When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fed64741d1..5224eb356d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -285,7 +285,7 @@ static const char * const riscv_excp_names[] =3D { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 08cc5b2e22..0d0f253fcb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -699,6 +699,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP =3D 0x10, RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b9f36e8621..623a3abbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1715,6 +1715,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) CPURISCVState *env =3D &cpu->env; bool virt =3D env->virt_enabled; bool write_gva =3D false; + bool vsmode_exc; uint64_t s; int mode; =20 @@ -1729,6 +1730,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + bool smode_double_trap =3D false; + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1839,13 +1842,34 @@ void riscv_cpu_do_interrupt(CPUState *cs) mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; =20 + vsmode_exc =3D env->virt_enabled && (((hdeleg >> cause) & 1) || vs_inj= ected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv =3D=3D PRV_S && mode =3D=3D PRV= _S) { + bool dte =3D (env->menvcfg & MENVCFG_DTE) !=3D 0; + bool sdt =3D (env->mstatus & MSTATUS_SDT) !=3D 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte =3D (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else if (env->virt_enabled) { + /* VS -> HS, use mstatus_hs */ + sdt =3D (env->mstatus_hs & MSTATUS_SDT) !=3D 0; + } + } + smode_double_trap =3D dte && sdt; + if (smode_double_trap) { + mode =3D PRV_M; + } + } + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -1878,6 +1902,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s =3D set_field(s, MSTATUS_SDT, 1); + } env->mstatus =3D s; sxlen =3D 16 << riscv_cpu_sxl(env); env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); @@ -1913,9 +1940,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); + if (smode_double_trap) { + env->mtval2 =3D env->mcause; + env->mcause =3D RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 =3D mtval2; + } env->mepc =3D env->pc; env->mtval =3D tval; - env->mtval2 =3D mtval2; env->mtinst =3D tinst; =20 /* --=20 2.45.2