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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1729026973567116600 Content-Type: text/plain; charset="utf-8" From: Frederic Barrat Add XIVE2 tests for group interrupts and group interrupts that have been backlogged. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- tests/qtest/pnv-xive2-test.c | 160 +++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c index 4ec1cc1b0f..1705127da1 100644 --- a/tests/qtest/pnv-xive2-test.c +++ b/tests/qtest/pnv-xive2-test.c @@ -2,6 +2,8 @@ * QTest testcase for PowerNV 10 interrupt controller (xive2) * - Test irq to hardware thread * - Test 'Pull Thread Context to Odd Thread Reporting Line' + * - Test irq to hardware group + * - Test irq to hardware group going through backlog * * Copyright (c) 2024, IBM Corporation. * @@ -316,6 +318,158 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTe= stState *qts) word2 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2); g_assert_cmphex(xive_get_field32(TM_QW3W2_VT, word2), =3D=3D, 0); } + +static void test_hw_group_irq(QTestState *qts) +{ + uint32_t irq =3D 100; + uint32_t irq_data =3D 0xdeadbeef; + uint32_t end_index =3D 23; + uint32_t chosen_one; + uint32_t target_nvp =3D 0x81; /* group size =3D 4 */ + uint8_t priority =3D 6; + uint32_t reg32; + uint16_t reg16; + uint8_t pq, nsr, cppr; + + printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); + printf("# Testing irq %d to hardware group of size 4\n", irq); + + /* irq config */ + set_eas(qts, irq, end_index, irq_data); + set_end(qts, end_index, target_nvp, priority, true /* group */); + + /* enable and trigger irq */ + get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00); + set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0); + + /* check irq is raised on cpu */ + pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING); + + /* find the targeted vCPU */ + for (chosen_one =3D 0; chosen_one < SMT; chosen_one++) { + reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + if (nsr =3D=3D 0x82) { + break; + } + } + g_assert_cmphex(chosen_one, <, SMT); + cppr =3D (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x82); + g_assert_cmphex(cppr, =3D=3D, 0xFF); + + /* ack the irq */ + reg16 =3D get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG); + nsr =3D reg16 >> 8; + cppr =3D reg16 & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x82); + g_assert_cmphex(cppr, =3D=3D, priority); + + /* check irq data is what was configured */ + reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index)); + g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff)); + + /* End Of Interrupt */ + set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0); + pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET); + + /* reset CPPR */ + set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); + reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x00); + g_assert_cmphex(cppr, =3D=3D, 0xFF); +} + +static void test_hw_group_irq_backlog(QTestState *qts) +{ + uint32_t irq =3D 31; + uint32_t irq_data =3D 0x01234567; + uint32_t end_index =3D 129; + uint32_t target_nvp =3D 0x81; /* group size =3D 4 */ + uint32_t chosen_one =3D 3; + uint8_t blocking_priority, priority =3D 3; + uint32_t reg32; + uint16_t reg16; + uint8_t pq, nsr, cppr, lsmfb, i; + + printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); + printf("# Testing irq %d to hardware group of size 4 going through " \ + "backlog\n", + irq); + + /* + * set current priority of all threads in the group to something + * higher than what we're about to trigger + */ + blocking_priority =3D priority - 1; + for (i =3D 0; i < SMT; i++) { + set_tima8(qts, i, TM_QW3_HV_PHYS + TM_CPPR, blocking_priority); + } + + /* irq config */ + set_eas(qts, irq, end_index, irq_data); + set_end(qts, end_index, target_nvp, priority, true /* group */); + + /* enable and trigger irq */ + get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00); + set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0); + + /* check irq is raised on cpu */ + pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING); + + /* check no interrupt is pending on the 2 possible targets */ + for (i =3D 0; i < SMT; i++) { + reg32 =3D get_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + lsmfb =3D reg32 & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x0); + g_assert_cmphex(cppr, =3D=3D, blocking_priority); + g_assert_cmphex(lsmfb, =3D=3D, priority); + } + + /* lower priority of one thread */ + set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, priority + 1); + + /* check backlogged interrupt is presented */ + reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x82); + g_assert_cmphex(cppr, =3D=3D, priority + 1); + + /* ack the irq */ + reg16 =3D get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG); + nsr =3D reg16 >> 8; + cppr =3D reg16 & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x82); + g_assert_cmphex(cppr, =3D=3D, priority); + + /* check irq data is what was configured */ + reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index)); + g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff)); + + /* End Of Interrupt */ + set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0); + pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET); + + /* reset CPPR */ + set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); + reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + lsmfb =3D reg32 & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x00); + g_assert_cmphex(cppr, =3D=3D, 0xFF); + g_assert_cmphex(lsmfb, =3D=3D, 0xFF); +} + static void test_xive(void) { QTestState *qts; @@ -331,6 +485,12 @@ static void test_xive(void) /* omit reset_state here and use settings from test_hw_irq */ test_pull_thread_ctx_to_odd_thread_cl(qts); =20 + reset_state(qts); + test_hw_group_irq(qts); + + reset_state(qts); + test_hw_group_irq_backlog(qts); + reset_state(qts); test_flush_sync_inject(qts); =20 --=20 2.43.0