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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1729026890151116600 Content-Type: text/plain; charset="utf-8" From: Frederic Barrat The NSR has a (so far unused) grouping level field. When a interrupt is presented, that field tells the hypervisor or OS if the interrupt is for an individual VP or for a VP-group/crowd. This patch reworks the presentation API to allow to set/unset the level when raising/accepting an interrupt. It also renames xive_tctx_ipb_update() to xive_tctx_pipr_update() as the IPB is only used for VP-specific target, whereas the PIPR always needs to be updated. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive.h | 19 +++++++- include/hw/ppc/xive_regs.h | 20 +++++++-- hw/intc/xive.c | 90 +++++++++++++++++++++++--------------- hw/intc/xive2.c | 18 ++++---- hw/intc/trace-events | 2 +- 5 files changed, 100 insertions(+), 49 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 31242f0406..27ef6c1a17 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -510,6 +510,21 @@ static inline uint8_t xive_priority_to_ipb(uint8_t pri= ority) 0 : 1 << (XIVE_PRIORITY_MAX - priority); } =20 +static inline uint8_t xive_priority_to_pipr(uint8_t priority) +{ + return priority > XIVE_PRIORITY_MAX ? 0xFF : priority; +} + +/* + * Convert an Interrupt Pending Buffer (IPB) register to a Pending + * Interrupt Priority Register (PIPR), which contains the priority of + * the most favored pending notification. + */ +static inline uint8_t xive_ipb_to_pipr(uint8_t ibp) +{ + return ibp ? clz32((uint32_t)ibp << 24) : 0xff; +} + /* * XIVE Thread Interrupt Management Aera (TIMA) * @@ -532,8 +547,10 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString = *buf); Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); -void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); +void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, + uint8_t group_level); void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring); +void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level); =20 /* * KVM XIVE device helpers diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 326327fc79..b455728c9c 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -146,7 +146,14 @@ #define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line= */ /* XXX more... */ =20 -/* NSR fields for the various QW ack types */ +/* + * NSR fields for the various QW ack types + * + * P10 has an extra bit in QW3 for the group level instead of the + * reserved 'i' bit. Since it is not used and we don't support group + * interrupts on P9, we use the P10 definition for the group level so + * that we can have common macros for the NSR + */ #define TM_QW0_NSR_EB PPC_BIT8(0) #define TM_QW1_NSR_EO PPC_BIT8(0) #define TM_QW3_NSR_HE PPC_BITMASK8(0, 1) @@ -154,8 +161,15 @@ #define TM_QW3_NSR_HE_POOL 1 #define TM_QW3_NSR_HE_PHYS 2 #define TM_QW3_NSR_HE_LSI 3 -#define TM_QW3_NSR_I PPC_BIT8(2) -#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7) +#define TM_NSR_GRP_LVL PPC_BITMASK8(2, 7) +/* + * On P10, the format of the 6-bit group level is: 2 bits for the + * crowd size and 4 bits for the group size. Since group/crowd size is + * always a power of 2, we encode the log. For example, group_level=3D4 + * means crowd size =3D 0 and group size =3D 16 (2^4) + * Same encoding is used in the NVP and NVGC structures for + * PGoFirst and PGoNext fields + */ =20 /* * EAS (Event Assignment Structure) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index efcb63e8aa..bacf518fa6 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -27,16 +27,6 @@ * XIVE Thread Interrupt Management context */ =20 -/* - * Convert an Interrupt Pending Buffer (IPB) register to a Pending - * Interrupt Priority Register (PIPR), which contains the priority of - * the most favored pending notification. - */ -static uint8_t ipb_to_pipr(uint8_t ibp) -{ - return ibp ? clz32((uint32_t)ibp << 24) : 0xff; -} - static uint8_t exception_mask(uint8_t ring) { switch (ring) { @@ -87,10 +77,17 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_= t ring) =20 regs[TM_CPPR] =3D cppr; =20 - /* Reset the pending buffer bit */ - alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); + /* + * If the interrupt was for a specific VP, reset the pending + * buffer bit, otherwise clear the logical server indicator + */ + if (regs[TM_NSR] & TM_NSR_GRP_LVL) { + regs[TM_NSR] &=3D ~TM_NSR_GRP_LVL; + } else { + alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); + } =20 - /* Drop Exception bit */ + /* Drop the exception bit */ regs[TM_NSR] &=3D ~mask; =20 trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, @@ -101,7 +98,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t= ring) return ((uint64_t)nsr << 8) | regs[TM_CPPR]; } =20 -static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) +void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level) { /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; @@ -111,13 +108,13 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t = ring) if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) { switch (ring) { case TM_QW1_OS: - regs[TM_NSR] |=3D TM_QW1_NSR_EO; + regs[TM_NSR] =3D TM_QW1_NSR_EO | (group_level & 0x3F); break; case TM_QW2_HV_POOL: - alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6); + alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6) | (group_level = & 0x3F); break; case TM_QW3_HV_PHYS: - regs[TM_NSR] |=3D (TM_QW3_NSR_HE_PHYS << 6); + regs[TM_NSR] =3D (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x= 3F); break; default: g_assert_not_reached(); @@ -159,7 +156,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t = ring, uint8_t cppr) * Recompute the PIPR based on local pending interrupts. The PHYS * ring must take the minimum of both the PHYS and POOL PIPR values. */ - pipr_min =3D ipb_to_pipr(regs[TM_IPB]); + pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]); ring_min =3D ring; =20 /* PHYS updates also depend on POOL values */ @@ -169,7 +166,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t = ring, uint8_t cppr) /* POOL values only matter if POOL ctx is valid */ if (pool_regs[TM_WORD2] & 0x80) { =20 - uint8_t pool_pipr =3D ipb_to_pipr(pool_regs[TM_IPB]); + uint8_t pool_pipr =3D xive_ipb_to_pipr(pool_regs[TM_IPB]); =20 /* * Determine highest priority interrupt and @@ -185,17 +182,27 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_= t ring, uint8_t cppr) regs[TM_PIPR] =3D pipr_min; =20 /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring_min); + xive_tctx_notify(tctx, ring_min, 0); } =20 -void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) -{ +void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, + uint8_t group_level) + { + /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ + uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r= ing; + uint8_t *alt_regs =3D &tctx->regs[alt_ring]; uint8_t *regs =3D &tctx->regs[ring]; =20 - regs[TM_IPB] |=3D ipb; - regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]); - xive_tctx_notify(tctx, ring); -} + if (group_level =3D=3D 0) { + /* VP-specific */ + regs[TM_IPB] |=3D xive_priority_to_ipb(priority); + alt_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); + } else { + /* VP-group */ + alt_regs[TM_PIPR] =3D xive_priority_to_pipr(priority); + } + xive_tctx_notify(tctx, ring, group_level); + } =20 /* * XIVE Thread Interrupt Management Area (TIMA) @@ -411,13 +418,13 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr, X= iveTCTX *tctx, } =20 /* - * Adjust the IPB to allow a CPU to process event queues of other + * Adjust the PIPR to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. */ static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned= size) { - xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xf= f)); + xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0); } =20 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, @@ -495,16 +502,20 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, X= iveTCTX *tctx, /* Reset the NVT value */ nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); - } + + uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; + regs[TM_IPB] |=3D ipb; +} + /* - * Always call xive_tctx_ipb_update(). Even if there were no + * Always call xive_tctx_pipr_update(). Even if there were no * escalation triggered, there could be a pending interrupt which * was saved when the context was pulled and that we need to take * into account by recalculating the PIPR (which is not * saved/restored). * It will also raise the External interrupt signal if needed. */ - xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); + xive_tctx_pipr_update(tctx, TM_QW1_OS, 0xFF, 0); /* fxb */ } =20 /* @@ -841,9 +852,9 @@ void xive_tctx_reset(XiveTCTX *tctx) * CPPR is first set. */ tctx->regs[TM_QW1_OS + TM_PIPR] =3D - ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); + xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =3D - ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); + xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); } =20 static void xive_tctx_realize(DeviceState *dev, Error **errp) @@ -1660,6 +1671,12 @@ static uint32_t xive_tctx_hw_cam_line(XivePresenter = *xptr, XiveTCTX *tctx) return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); } =20 +static uint8_t xive_get_group_level(uint32_t nvp_index) +{ + /* FIXME add crowd encoding */ + return ctz32(~nvp_index) + 1; +} + /* * The thread context register words are in big-endian format. */ @@ -1745,6 +1762,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f= ormat, { XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb); XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 }; + uint8_t group_level; int count; =20 /* @@ -1758,9 +1776,9 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f= ormat, =20 /* handle CPU exception delivery */ if (count) { - trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring); - xive_tctx_ipb_update(match.tctx, match.ring, - xive_priority_to_ipb(priority)); + group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0; + trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le= vel); + xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve= l); } =20 return !!count; diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 4adc3b6950..db372f4b30 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -564,8 +564,10 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, = XiveTCTX *tctx, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { + uint8_t ipb, backlog_level; + uint8_t backlog_prio; + uint8_t *regs =3D &tctx->regs[TM_QW1_OS]; Xive2Nvp nvp; - uint8_t ipb; =20 /* * Grab the associated thread interrupt context registers in the @@ -594,15 +596,15 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr,= XiveTCTX *tctx, nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); } + regs[TM_IPB] =3D ipb; + backlog_prio =3D xive_ipb_to_pipr(ipb); + backlog_level =3D 0; + /* - * Always call xive_tctx_ipb_update(). Even if there were no - * escalation triggered, there could be a pending interrupt which - * was saved when the context was pulled and that we need to take - * into account by recalculating the PIPR (which is not - * saved/restored). - * It will also raise the External interrupt signal if needed. + * Compute the PIPR based on the restored state. + * It will raise the External interrupt signal if needed. */ - xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); + xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level); } =20 /* diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 3dcf147198..7435728c51 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -282,7 +282,7 @@ xive_router_end_notify(uint8_t end_blk, uint32_t end_id= x, uint32_t end_data) "EN xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_bl= k, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END = 0x%02x/0x%04x data 0x%08x" xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uin= t64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64 xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint= 64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64 -xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "fo= und NVT 0x%x/0x%x ring=3D0x%x" +xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uin= t8_t group_level) "found NVT 0x%x/0x%x ring=3D0x%x group_level=3D%d" xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "EN= D 0x%x/0x%x @0x%"PRIx64 =20 # pnv_xive.c --=20 2.43.0