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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1729026973631116600 Content-Type: text/plain; charset="utf-8" From: Glenn Miles Added new test for pool interrupts. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal --- tests/qtest/pnv-xive2-test.c | 77 ++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c index a6008bc053..6e7e7f0d9b 100644 --- a/tests/qtest/pnv-xive2-test.c +++ b/tests/qtest/pnv-xive2-test.c @@ -4,6 +4,7 @@ * - Test 'Pull Thread Context to Odd Thread Reporting Line' * - Test irq to hardware group * - Test irq to hardware group going through backlog + * - Test irq to pool thread * * Copyright (c) 2024, IBM Corporation. * @@ -267,6 +268,79 @@ static void test_hw_irq(QTestState *qts) g_assert_cmphex(cppr, =3D=3D, 0xFF); } =20 +static void test_pool_irq(QTestState *qts) +{ + uint32_t irq =3D 2; + uint32_t irq_data =3D 0x600d0d06; + uint32_t end_index =3D 5; + uint32_t target_pir =3D 1; + uint32_t target_nvp =3D 0x100 + target_pir; + uint8_t priority =3D 5; + uint32_t reg32; + uint16_t reg16; + uint8_t pq, nsr, cppr, ipb; + + printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); + printf("# Testing irq %d to pool thread %d\n", irq, target_pir); + + /* irq config */ + set_eas(qts, irq, end_index, irq_data); + set_end(qts, end_index, target_nvp, priority, false /* group */); + + /* enable and trigger irq */ + get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00); + set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0); + + /* check irq is raised on cpu */ + pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING); + + /* check TIMA values in the PHYS ring (shared by POOL ring) */ + reg32 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x40); + g_assert_cmphex(cppr, =3D=3D, 0xFF); + + /* check TIMA values in the POOL ring */ + reg32 =3D get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + ipb =3D (reg32 >> 8) & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0); + g_assert_cmphex(cppr, =3D=3D, 0); + g_assert_cmphex(ipb, =3D=3D, 0x80 >> priority); + + /* ack the irq */ + reg16 =3D get_tima16(qts, target_pir, TM_SPC_ACK_HV_REG); + nsr =3D reg16 >> 8; + cppr =3D reg16 & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x40); + g_assert_cmphex(cppr, =3D=3D, priority); + + /* check irq data is what was configured */ + reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index)); + g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff)); + + /* check IPB is cleared in the POOL ring */ + reg32 =3D get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0); + ipb =3D (reg32 >> 8) & 0xFF; + g_assert_cmphex(ipb, =3D=3D, 0); + + /* End Of Interrupt */ + set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0); + pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET); + + /* reset CPPR */ + set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); + reg32 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); + nsr =3D reg32 >> 24; + cppr =3D (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, =3D=3D, 0x00); + g_assert_cmphex(cppr, =3D=3D, 0xFF); +} + #define XIVE_ODD_CL 0x80 static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts) { @@ -485,6 +559,9 @@ static void test_xive(void) /* omit reset_state here and use settings from test_hw_irq */ test_pull_thread_ctx_to_odd_thread_cl(qts); =20 + reset_state(qts); + test_pool_irq(qts); + reset_state(qts); test_hw_group_irq(qts); =20 --=20 2.43.0