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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1729026988401116600 Content-Type: text/plain; charset="utf-8" From: Glenn Miles When booting with PHYP, the blk/index for a NVGC was being mistakenly treated as the blk/index for a NVP. Renamed nvp_blk/nvp_idx throughout the code to nvx_blk/nvx_idx to prevent confusion in the future and now we delay loading the NVP until the point where we know that the block and index actually point to a NVP. Suggested-by: Michael Kowal Fixes: 6d4c4f70262 ("ppc/xive2: Support crowd-matching when looking for tar= get") Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal --- hw/intc/xive2.c | 78 ++++++++++++++++++++++++------------------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index f812ba9624..8abccd2f4b 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -226,8 +226,8 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e= nd_idx, GString *buf) uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qentries =3D 1 << (qsize + 10); =20 - uint32_t nvp_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6); - uint32_t nvp_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6); + uint32_t nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6); + uint32_t nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6); uint8_t priority =3D xive_get_field32(END2_W7_F0_PRIORITY, end->w7); uint8_t pq; =20 @@ -256,7 +256,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e= nd_idx, GString *buf) xive2_end_is_firmware2(end) ? 'F' : '-', xive2_end_is_ignore(end) ? 'i' : '-', xive2_end_is_crowd(end) ? 'c' : '-', - priority, nvp_blk, nvp_idx); + priority, nvx_blk, nvx_idx); =20 if (qaddr_base) { g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", @@ -401,7 +401,7 @@ static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t = *nvgc_idx, * level of pending group interrupts. */ static uint8_t xive2_presenter_backlog_check(XivePresenter *xptr, - uint8_t nvp_blk, uint32_t nvp= _idx, + uint8_t nvx_blk, uint32_t nvx= _idx, uint8_t first_group, uint8_t *out_level) { @@ -413,8 +413,8 @@ static uint8_t xive2_presenter_backlog_check(XivePresen= ter *xptr, =20 for (prio =3D 0; prio <=3D XIVE_PRIORITY_MAX; prio++) { current_level =3D first_group & 0x3F; - nvgc_blk =3D nvp_blk; - nvgc_idx =3D nvp_idx; + nvgc_blk =3D nvx_blk; + nvgc_idx =3D nvx_idx; =20 while (current_level) { xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level); @@ -443,7 +443,7 @@ static uint8_t xive2_presenter_backlog_check(XivePresen= ter *xptr, } =20 static void xive2_presenter_backlog_decr(XivePresenter *xptr, - uint8_t nvp_blk, uint32_t nvp_idx, + uint8_t nvx_blk, uint32_t nvx_idx, uint8_t group_prio, uint8_t group_level) { @@ -452,8 +452,8 @@ static void xive2_presenter_backlog_decr(XivePresenter = *xptr, uint8_t nvgc_blk; Xive2Nvgc nvgc; =20 - nvgc_blk =3D nvp_blk; - nvgc_idx =3D nvp_idx; + nvgc_blk =3D nvx_blk; + nvgc_idx =3D nvx_idx; xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level); =20 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level), @@ -1317,9 +1317,8 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, uint8_t priority; uint8_t format; bool found, precluded; - Xive2Nvp nvp; - uint8_t nvp_blk; - uint32_t nvp_idx; + uint8_t nvx_blk; + uint32_t nvx_idx; =20 /* END cache lookup */ if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { @@ -1384,23 +1383,10 @@ static void xive2_router_end_notify(Xive2Router *xr= tr, uint8_t end_blk, /* * Follows IVPE notification */ - nvp_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end.w6); - nvp_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end.w6); - - /* NVP cache lookup */ - if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", - nvp_blk, nvp_idx); - return; - } - - if (!xive2_nvp_is_valid(&nvp)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", - nvp_blk, nvp_idx); - return; - } + nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end.w6); + nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end.w6); =20 - found =3D xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, + found =3D xive_presenter_notify(xrtr->xfb, format, nvx_blk, nvx_idx, xive2_end_is_crowd(&end), xive2_end_is_ignore(&e= nd), priority, xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w= 7), @@ -1428,6 +1414,21 @@ static void xive2_router_end_notify(Xive2Router *xrt= r, uint8_t end_blk, =20 if (!xive2_end_is_ignore(&end)) { uint8_t ipb; + Xive2Nvp nvp; + + /* NVP cache lookup */ + if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", + nvx_blk, nvx_idx); + return; + } + + if (!xive2_nvp_is_valid(&nvp)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid= \n", + nvx_blk, nvx_idx); + return; + } + /* * Record the IPB in the associated NVP structure for later * use. The presenter will resend the interrupt when the vCPU @@ -1436,7 +1437,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr= , uint8_t end_blk, ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2) | xive_priority_to_ipb(priority); nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); - xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); + xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2); } else { Xive2Nvgc nvgc; uint32_t backlog; @@ -1449,32 +1450,31 @@ static void xive2_router_end_notify(Xive2Router *xr= tr, uint8_t end_blk, * counters are stored in the NVG/NVC structures */ if (xive2_router_get_nvgc(xrtr, crowd, - nvp_blk, nvp_idx, &nvgc)) { + nvx_blk, nvx_idx, &nvgc)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", - crowd ? "NVC" : "NVG", nvp_blk, nvp_idx); + crowd ? "NVC" : "NVG", nvx_blk, nvx_idx); return; } =20 if (!xive2_nvgc_is_valid(&nvgc)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid= \n", - nvp_blk, nvp_idx); + nvx_blk, nvx_idx); return; } =20 /* * Increment the backlog counter for that priority. - * For the precluded case, we only call broadcast the - * first time the counter is incremented. broadcast will - * set the LSMFB field of the TIMA of relevant threads so - * that they know an interrupt is pending. + * We only call broadcast the first time the counter is + * incremented. broadcast will set the LSMFB field of the TIMA= of + * relevant threads so that they know an interrupt is pending. */ backlog =3D xive2_nvgc_get_backlog(&nvgc, priority) + 1; xive2_nvgc_set_backlog(&nvgc, priority, backlog); - xive2_router_write_nvgc(xrtr, crowd, nvp_blk, nvp_idx, &nvgc); + xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc); =20 - if (precluded && backlog =3D=3D 1) { + if (backlog =3D=3D 1) { XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb); - xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx, + xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, xive2_end_is_crowd(&end), xive2_end_is_ignore(&end), priority); --=20 2.43.0