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Iglesias" , Alistair Francis , Peter Maydell , "Jason Wang" , Francisco Iglesias Subject: [PATCH] hw/net: Extend ethernetlite driver with PHY layer Date: Tue, 15 Oct 2024 18:56:22 +0530 Message-ID: <20241015132622.3468066-1-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: sai.pavan.boddu@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6734:EE_|IA0PR12MB7650:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b0f80fe-bb6d-4291-34e1-08dced1cfa0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AKaDQDkXLEjwxBXdz7Jno+BsPOi7l/d8dtW/zdTWLZr0Tbg4Cz322EQeE9l9?= =?us-ascii?Q?s/i0HhcRS+R6X/bxZk0xoGIAK43OLCOsA32l/8z0SAwfnK0tdgYqoIV+FFwh?= =?us-ascii?Q?eeAI389Q/btbiDuYjrMlpu4gd32tQMpbIowCwSaxdrTekp+tKLsAHHknnxAu?= =?us-ascii?Q?f+W295SlOWKNInveoBVJu8oO91ZWl4yp6J+K9P71czFQZfmgZfX+xnC7b/dQ?= =?us-ascii?Q?OioXI1at76JEgd4IvnjobJAuyjsucMOKFJrgUd9ijkT767ObyS07p4UNlnHW?= =?us-ascii?Q?fz0zwwBx4IYOdV6AZIwmFwKLmlEu3pdS9sBEn/+u77ME+kXO24th9K/EWlCV?= =?us-ascii?Q?JrnoRpkmF4fsM4RIV0r/FC1CGGCCE0SURgnWkhuTQ1Ouo4ytuRm1ZVLlP2Vv?= =?us-ascii?Q?RVzD+DT2AGrJJkUOP+SEwwGwaxp1fqbFzMgu21fnn/UFG5iIMolai4y2bpj1?= =?us-ascii?Q?LEqoD5Umumkv4zwfsTIQz+TEfWtHB2QMQvI0Qww8Rvt9vqVV6AIj106FF538?= =?us-ascii?Q?h91JEDqTQ5CFCOJhEMC2C6mL2UX8PAs4gXZcnWHJkvMTclP1HCkeHAIjEkUb?= =?us-ascii?Q?20aUsQSCEaolV1XlLcf8cs7TAcOpg82C7eWvqUg2PYMAyu5NYKZvyxpKSbbN?= =?us-ascii?Q?LZPB/70fCD0fFX+pMCN8Y4ltpKd8yXiwPbI/FTP3GpcrNOidxN3aUPvkVaz/?= =?us-ascii?Q?WcJOcOCJU0AK6y4ImroEE9k6h/btT3rrHHpaX9RyV+UklnpGdtfVDqk5fAiG?= =?us-ascii?Q?Bs3i2mxznKcB1tEEXHCr4154jFTsJNAwyepIAdQh93oi0o29vs3zeryy5R5y?= =?us-ascii?Q?Ov3JyE15ai3e/m/SJPyNPxksDDpbVx3rXBVFgnTVp5uFiz5MNluIkz2GVqUT?= =?us-ascii?Q?5bP4ud9Wlih4w5Lh5kguz+YNE2s6yKzkg/tug+qcQnHpFTBvn4TeqvRUa9pw?= =?us-ascii?Q?nrgplHqn9XR6tT+D6ja+k5DgbU/PrCTT8Ox3U10GtMEByeehuATWCPoyERr5?= =?us-ascii?Q?0qoLzhi5Q3gGst9qYzD2H8QKFRbWu74lQqfNsBG0cggkSvMIHx1lfl4EHvC3?= =?us-ascii?Q?shX77fWTH6HXBJrbPiunt67KfvhyiI8CfnMnYPupJc6+1LQBhyR55RliUI+D?= =?us-ascii?Q?fNdXPrEX8BA8XPs5iyJsh4BUQg9Z4KdTrJ1KE96RtAEHMp23rSrdpelRt+zK?= =?us-ascii?Q?xX4eEYOrNgb90CUxb5u7uKOUNK4cDXTyjUe8G1VA8a7VJM7pCS2XpMsPMKqb?= =?us-ascii?Q?hxoQDUbt75VxFNN5+uAlLtlnFQcHNYi7yaznTQMLCegO6AVlXe0tEFgrxGyH?= =?us-ascii?Q?xJvLzk6+AmR36DDe6QIS5/Na7u4xDLC1CnXhHaLUHyVVXbFLKrsMA8qgbgiR?= =?us-ascii?Q?dsjIqJKwHxhSUxZa2QOPe/PRtmZF?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 13:26:28.8110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b0f80fe-bb6d-4291-34e1-08dced1cfa0b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6734.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7650 Received-SPF: permerror client-ip=2a01:111:f403:2414::61b; envelope-from=sai.pavan.boddu@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: 3 X-Spam_score: 0.3 X-Spam_bar: / X-Spam_report: (0.3 / 5.0 requ) AC_FROM_MANY_DOTS=2.499, BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.063, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1728998832044116600 Content-Type: text/plain; charset="utf-8" From: Michal Simek Add missing optional MDIO lines. Without it U-Boot is not working. Signed-off-by: Edgar E. Iglesias Signed-off-by: Michal Simek --- hw/net/xilinx_ethlite.c | 240 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 240 insertions(+) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index bd812908085..5b129ca7e4e 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -56,6 +56,215 @@ DECLARE_INSTANCE_CHECKER(struct xlx_ethlite, XILINX_ETHLITE, TYPE_XILINX_ETHLITE) =20 +#define R_MDIOADDR (0x07E4 / 4) /* MDIO Address Register */ +#define R_MDIOWR (0x07E8 / 4) /* MDIO Write Data Register */ +#define R_MDIORD (0x07EC / 4) /* MDIO Read Data Register */ +#define R_MDIOCTRL (0x07F0 / 4) /* MDIO Control Register */ + +/* MDIO Address Register Bit Masks */ +#define R_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ +#define R_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ +#define R_MDIOADDR_PHYADR_SHIFT 5 +#define R_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ + +/* MDIO Write Data Register Bit Masks */ +#define R_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ + +/* MDIO Read Data Register Bit Masks */ +#define R_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ + +/* MDIO Control Register Bit Masks */ +#define R_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ +#define R_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ + +/* Advertisement control register. */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ + +#define DPHY(x) + +struct PHY { + uint32_t regs[32]; + + int link; + + unsigned int (*read)(struct PHY *phy, unsigned int req); + void (*write)(struct PHY *phy, unsigned int req, + unsigned int data); +}; + +static unsigned int tdk_read(struct PHY *phy, unsigned int req) +{ + int regnum; + unsigned r =3D 0; + + regnum =3D req & 0x1f; + + switch (regnum) { + case 1: + if (!phy->link) { + break; + } + /* MR1. */ + /* Speeds and modes. */ + r |=3D (1 << 13) | (1 << 14); + r |=3D (1 << 11) | (1 << 12); + r |=3D (1 << 5); /* Autoneg complete. */ + r |=3D (1 << 3); /* Autoneg able. */ + r |=3D (1 << 2); /* link. */ + r |=3D (1 << 1); /* link. */ + break; + case 5: + /* + * Link partner ability. + * We are kind; always agree with whatever best mode + * the guest advertises. + */ + r =3D 1 << 14; /* Success. */ + /* Copy advertised modes. */ + r |=3D phy->regs[4] & (15 << 5); + /* Autoneg support. */ + r |=3D 1; + break; + case 17: + /* Marvel PHY on many xilinx boards. */ + r =3D 0x4c00; /* 100Mb */ + break; + case 18: + { + /* Diagnostics reg. */ + int duplex =3D 0; + int speed_100 =3D 0; + if (!phy->link) { + break; + } + /* Are we advertising 100 half or 100 duplex ? */ + speed_100 =3D !!(phy->regs[4] & ADVERTISE_100HALF); + speed_100 |=3D !!(phy->regs[4] & ADVERTISE_100FULL); + /* Are we advertising 10 duplex or 100 duplex ? */ + duplex =3D !!(phy->regs[4] & ADVERTISE_100FULL); + duplex |=3D !!(phy->regs[4] & ADVERTISE_10FULL); + r =3D (speed_100 << 10) | (duplex << 11); + } + break; + + default: + r =3D phy->regs[regnum]; + break; + } + DPHY(qemu_log("\n%s %x =3D reg[%d]\n", __func__, r, regnum)); + return r; +} + +static void +tdk_write(struct PHY *phy, unsigned int req, unsigned int data) +{ + int regnum; + + regnum =3D req & 0x1f; + DPHY(qemu_log("%s reg[%d] =3D %x\n", __func__, regnum, data)); + switch (regnum) { + default: + phy->regs[regnum] =3D data; + break; + } + + /* Unconditionally clear regs[BMCR][BMCR_RESET] */ + phy->regs[0] &=3D ~0x8000; +} + +static void +tdk_init(struct PHY *phy) +{ + phy->regs[0] =3D 0x3100; + /* PHY Id. */ + phy->regs[2] =3D 0x0141; + phy->regs[3] =3D 0x0cc2; + /* Autonegotiation advertisement reg. */ + phy->regs[4] =3D 0x01E1; + phy->link =3D 1; + + phy->read =3D tdk_read; + phy->write =3D tdk_write; +} + +struct MDIOBus { + /* bus. */ + int mdc; + int mdio; + + /* decoder. */ + enum { + PREAMBLE, + SOF, + OPC, + ADDR, + REQ, + TURNAROUND, + DATA + } state; + unsigned int drive; + + unsigned int cnt; + unsigned int addr; + unsigned int opc; + unsigned int req; + unsigned int data; + + struct PHY *devs[32]; +}; + +static void +mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) +{ + bus->devs[addr & 0x1f] =3D phy; +} + +#ifdef USE_THIS_DEAD_CODE +static void +mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) +{ + bus->devs[addr & 0x1f] =3D NULL; +} +#endif + +static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, + unsigned int reg) +{ + struct PHY *phy; + uint16_t data; + + phy =3D bus->devs[addr]; + if (phy && phy->read) { + data =3D phy->read(phy, reg); + } else { + data =3D 0xffff; + } + DPHY(qemu_log("%s addr=3D%d reg=3D%d data=3D%x\n", __func__, addr, reg= , data)); + return data; +} + +static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, + unsigned int reg, uint16_t data) +{ + struct PHY *phy; + + DPHY(qemu_log("%s addr=3D%d reg=3D%d data=3D%x\n", __func__, addr, reg= , data)); + phy =3D bus->devs[addr]; + if (phy && phy->write) { + phy->write(phy, reg, data); + } +} + +struct TEMAC { + struct MDIOBus mdio_bus; + struct PHY phy; + + void *parent; +}; + struct xlx_ethlite { SysBusDevice parent_obj; @@ -70,6 +279,9 @@ struct xlx_ethlite unsigned int txbuf; unsigned int rxbuf; =20 +uint32_t c_phyaddr; + struct TEMAC TEMAC; + uint32_t regs[R_MAX]; }; =20 @@ -101,11 +313,15 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) r =3D s->regs[addr]; D(qemu_log("%s " HWADDR_FMT_plx "=3D%x\n", __func__, addr * 4,= r)); break; + case R_MDIOCTRL: + r =3D s->regs[addr] & (~R_MDIOCTRL_MDIOSTS_MASK); /* Always re= ady. */ + break; =20 default: r =3D tswap32(s->regs[addr]); break; } + D(qemu_log("%s " HWADDR_FMT_plx "=3D%x\n", __func__, addr * 4, r)); return r; } =20 @@ -159,6 +375,26 @@ eth_write(void *opaque, hwaddr addr, __func__, addr * 4, value)); s->regs[addr] =3D value; break; + case R_MDIOCTRL: + if (((unsigned int)value & R_MDIOCTRL_MDIOSTS_MASK) !=3D 0) { + struct TEMAC *t =3D &s->TEMAC; + unsigned int op =3D s->regs[R_MDIOADDR] & R_MDIOADDR_OP_MA= SK; + unsigned int phyaddr =3D (s->regs[R_MDIOADDR] & + R_MDIOADDR_PHYADR_MASK) >> R_MDIOADDR_PHYADR_SHIFT; + unsigned int regaddr =3D s->regs[R_MDIOADDR] & + R_MDIOADDR_REGADR_MASK; + if (op) { + /* read PHY registers */ + s->regs[R_MDIORD] =3D mdio_read_req( + &t->mdio_bus, phyaddr, regaddr); + } else { + /* write PHY registers */ + mdio_write_req(&t->mdio_bus, phyaddr, regaddr, + s->regs[R_MDIOWR]); + } + } + s->regs[addr] =3D value; + break; =20 default: s->regs[addr] =3D tswap32(value); @@ -238,6 +474,9 @@ static void xilinx_ethlite_realize(DeviceState *dev, Er= ror **errp) object_get_typename(OBJECT(dev)), dev->id, &dev->mem_reentrancy_guard, s); qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); + + tdk_init(&s->TEMAC.phy); + mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); } =20 static void xilinx_ethlite_init(Object *obj) @@ -252,6 +491,7 @@ static void xilinx_ethlite_init(Object *obj) } =20 static Property xilinx_ethlite_properties[] =3D { + DEFINE_PROP_UINT32("phyaddr", struct xlx_ethlite, c_phyaddr, 7), DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, = 1), DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, = 1), DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), --=20 2.34.1