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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d7fa7a06dsm1241635f8f.5.2024.10.15.03.38.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 03:38:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728988693; x=1729593493; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uMQQ7fdyXd07jMQ0rVrq7jETk7cjRhNibU6XZ/lFh88=; b=PGMCd8GXUKSRl5AqD8c3+g+UnmEqSNzq6MDTqCmTSTipsgtKx6k5pbXifQ+tO2d+y5 v+BO2SNwngBqsH84URDZ9mFg1HWYVlcxNgMaWj+v6gFDkY+TBREohzkL5xe1S4hlnk2g LxB3FIbxxU0FYu+3r4WgJy5GTLnX68peS0/Dqb/n3tDD/82AHp03x9AKLSkmF9OpcLex JpbzChPmJsovlQ+dtkGCEuaMc+uU/+/Majk/9hKNL0HWnHPc/fk5KsKwnA8xrTIeagnz 5KnbYXRQOT4xa4u4zSqHqci+DWczhlwIaUyQffKyxuEK+x9hUS0Y5k+WgDO9o3tqfEVg Abpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728988693; x=1729593493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uMQQ7fdyXd07jMQ0rVrq7jETk7cjRhNibU6XZ/lFh88=; b=e4lBxfQ3tznX70giO+OHZk8SlnXBhgUsI6Oprn8QB0Ga1DZLVqp56GUG3dBfNKtB57 +F/yaiAv+8CbSSUlO6TSn8KDh1zXWX9p1xu2Rwv+klf7FAPLET263d7zV8KgqMrEAxRM aiIhL1y24Iq8Di1NEiGGYeB9CARkKAca0uabH0dnA67svIkUhrMMAKAuC0AHe5h4cbzY MhUmUYxym6xes/1vuE9l0Nl4zgfWUeRL1DR7OspoRNquyfDGg4Hal5pN2PTcgwnLfLo2 I/yjCUnCqFXCUQCxVw2GCRyHspYflxcR77HLtnRmhfecF44AL1HHeJbGf7gHuehpIZvp /K3Q== X-Gm-Message-State: AOJu0YxFfGQVXm5nJOOm/52XN4mbtVSI8DiRPk4hh7RGqxMwA4wmYKnD kyc4P/bCzfaYC07j5SXGeoiYLYJLJg5aH8lNu2uvKpzHN3RGDIG9kyiXti20n53K2luN3hBFEXW N X-Google-Smtp-Source: AGHT+IH/t4pjRBLvgpjtys5YCCNmPZEUd4N+E1omAikdRTF6o0Dq3HazMun3CU6aps+swMMUbx8PXg== X-Received: by 2002:a5d:6591:0:b0:37c:cdb6:6a9e with SMTP id ffacd0b85a97d-37d5518e759mr9495410f8f.9.1728988692609; Tue, 15 Oct 2024 03:38:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/28] hw/intc/arm_gicv3_cpuif: Add cast to match the documentation Date: Tue, 15 Oct 2024 11:37:46 +0100 Message-Id: <20241015103808.133024-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015103808.133024-1-peter.maydell@linaro.org> References: <20241015103808.133024-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728988798389116600 Content-Type: text/plain; charset="utf-8" From: Alexandra Diupina The result of 1 << regbit with regbit=3D=3D31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICH_AP[0/1]R_EL2 are reserved. Add an explicit cast to match the documentation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: c3f21b065a ("hw/intc/arm_gicv3_cpuif: Support vLPIs") Signed-off-by: Alexandra Diupina Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 89359db7004..ea1d1b34551 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -793,7 +793,7 @@ static void icv_activate_vlpi(GICv3CPUState *cs) int regno =3D aprbit / 32; int regbit =3D aprbit % 32; =20 - cs->ich_apr[cs->hppvlpi.grp][regno] |=3D (1 << regbit); + cs->ich_apr[cs->hppvlpi.grp][regno] |=3D (1U << regbit); gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0); } =20 --=20 2.34.1