From nobody Wed Oct 23 00:28:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728987066; cv=none; d=zohomail.com; s=zohoarc; b=bCI6EsM+E83rGy8ZU1e2dfRRm6QoPnImgdzBTd1QzB4Mh1wRVovxCax+UDyisupfd4nmd5gSPhaK7C8B32fxcn+5CoXNnGDzQzzVuvjNNj2Q7t/XhR/aDLPctz7D3yaSqqKEgkeJ7LI1Yu6jefCImYBX8MhOUTtrsZFw/af1Cvs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728987066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=941y336J4Aosp/Z+nB50nJkwKhcNLqIO+eVe0f4LkSI=; b=j8QOcOwOv61kjW6xrwzaszmiIyju19sNOp4M389s5QP8c1/t86aKnoiy24ENOGfuQNi/OFLoe77OXz2prSrtAFfHOnH/wMFN18rhypyBHdbJFx0jYUlXA8FknusciEtTf226HqmAo1eHv6SybnwQ/r597zergcZBeUycbgX6aX8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728987066778864.2310952461488; Tue, 15 Oct 2024 03:11:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0eW4-00084j-C2; Tue, 15 Oct 2024 06:11:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eUu-00076Z-Iq; Tue, 15 Oct 2024 06:09:55 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eUs-0002YL-Mr; Tue, 15 Oct 2024 06:09:48 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XSV8X2KtSz6DB4D; Tue, 15 Oct 2024 18:05:16 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id A3C5C1404F5; Tue, 15 Oct 2024 18:09:44 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.48.146.149) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Oct 2024 12:09:24 +0200 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V5 26/30] hw/intc/arm_gicv3_common: Add GICv3CPUState 'accessible' flag migration handling Date: Tue, 15 Oct 2024 11:00:08 +0100 Message-ID: <20241015100012.254223-27-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015100012.254223-1-salil.mehta@huawei.com> References: <20241015100012.254223-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.146.149] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728987068304116600 The QOM `GICv3CPUState` (and consequently the corresponding KVM VGIC `ICC_*= _EL1` registers) can be either 'accessible' or 'inaccessible', depending on the s= tate of the associated QOM vCPUs. This `gicc_accessible` state should be saved d= uring migration at the source and restored at the destination. Ideally, the number of possible and enabled QOM vCPUs should match between = the source and destination. Ensuring this consistency is the responsibility of = the administrator. However, if the destination QEMU has more enabled vCPUs than= the source, we can either fail the migration or override the destination QEMU= =E2=80=99s vCPU configuration to match the source. We have adopted the latter approach as a mitigation for the mismatch. Nonetheless, the administrator should still en= sure that the number of possible QOM vCPUs is consistent at both ends. Signed-off-by: Salil Mehta --- hw/intc/arm_gicv3_common.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index c21fff4903..53045ad6bc 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -126,6 +126,29 @@ static int vmstate_gicv3_cpu_pre_load(void *opaque) return 0; } =20 +static int vmstate_gicv3_cpu_post_load(void *opaque, int version_id) +{ + GICv3CPUState *cs =3D opaque; + + /* + * If the destination QEMU has more *enabled* vCPUs than the source, w= e can + * either *fail* the migration or override the destination QEMU=E2=80= =99s vCPU + * configuration to match the source. Since it is safe to override the + * `CPUState` of the extra *enabled* vCPUs at the destination, we have + * adopted the latter approach as a mitigation for the mismatch. + * RFC: Question: any suggestions on this are welcome? + */ + if (cs->cpu && !gicv3_cpu_accessible((cs))) { + warn_report("Found CPU %d enabled, for incoming *disabled* GICC St= ate", + cs->cpu->cpu_index); + warn_report("*Disabling* CPU %d, to match the incoming migrated st= ate", + cs->cpu->cpu_index); + qdev_unrealize(DEVICE(cs->cpu)); + } + + return 0; +} + static bool icc_sre_el1_reg_needed(void *opaque) { GICv3CPUState *cs =3D opaque; @@ -186,6 +209,7 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { .version_id =3D 1, .minimum_version_id =3D 1, .pre_load =3D vmstate_gicv3_cpu_pre_load, + .post_load =3D vmstate_gicv3_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(level, GICv3CPUState), VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), @@ -207,6 +231,7 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), + VMSTATE_BOOL(gicc_accessible, GICv3CPUState), VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription * const []) { --=20 2.34.1