From nobody Wed Oct 23 00:29:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728986852; cv=none; d=zohomail.com; s=zohoarc; b=ceOkKZCkXUIxMPfXNdtmn0cBr/t8oMHRhd6Hjrx4wSmbXaHoFtAM9oEK1PC/gazdNBKH8tlwYwypQVZ1S9y/p30ywjq78aokvA/SAEY7ZlXDuPGa3P7zyGfQ3TI+vzUTLuscx0jdERIRDiIa6P3CVgCKDMtSsw+txQJ0x9yyJhc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728986852; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ZLbr2phGfFy6BBhxwm5H2CSrUKYGe/4PR99Tzk8ZcQs=; b=C91EVx+WgZ4M9kFUpfpSzQhF8H6Fj9ZyD0SzVWy1fEdwV0r0x4hr8Bgv/YwnGlQfNndRpyD9pjKIzwJ2gohyKAFuL1MRchN2jchFLpGRyLVLHWKT9dnWb6I+7GuIZyJ0ZZyah5OY4A27FwG4+mzDHNJnkRQngxJkXj+hj/55D7A= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728986852184627.2921826537021; Tue, 15 Oct 2024 03:07:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0eSb-0003m5-UV; Tue, 15 Oct 2024 06:07:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eSL-0003c7-S9; Tue, 15 Oct 2024 06:07:11 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eSJ-0001nN-NY; Tue, 15 Oct 2024 06:07:09 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XSV9y30m5z6K5sy; Tue, 15 Oct 2024 18:06:30 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 8B527140451; Tue, 15 Oct 2024 18:07:04 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.48.146.149) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Oct 2024 12:06:44 +0200 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V5 18/30] arm/virt: Changes to (un)wire GICC<->vCPU IRQs during hot-(un)plug Date: Tue, 15 Oct 2024 11:00:00 +0100 Message-ID: <20241015100012.254223-19-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015100012.254223-1-salil.mehta@huawei.com> References: <20241015100012.254223-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.146.149] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728986853199116600 Content-Type: text/plain; charset="utf-8" Refactors the existing GIC create code to extract common code to wire the vcpu<->gic interrupts. This function could be used with cold-plug case and = also used when vCPU is hot-plugged. It also introduces a new function to unwire = the vcpu<->gic interrupts for the vCPU hot-unplug cases. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reported-by: Vishnu Pajjuri [4/05/2024: Issue with total number of PPI available during create GIC] Suggested-by: Miguel Luis [5/05/2024: Fix the total number of PPIs available as per ARM BSA to avoid = overflow] Signed-off-by: Salil Mehta --- hw/arm/virt.c | 154 ++++++++++++++++++++++++++++------------- hw/core/gpio.c | 2 +- include/hw/qdev-core.h | 2 + target/arm/cpu-qom.h | 18 +++-- 4 files changed, 118 insertions(+), 58 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bcaedb8f..0a912919ec 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -765,6 +765,107 @@ static bool gicv3_nmi_present(VirtMachineState *vms) (vms->gic_version !=3D VIRT_GIC_VERSION_2); } =20 +/* + * Mapping from the output timer irq lines from the CPU to the GIC PPI inp= uts + * we use for the virt board. + */ +const int timer_irq[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, +}; + +static void unwire_gic_cpu_irqs(VirtMachineState *vms, CPUState *cs) +{ + MachineState *ms =3D MACHINE(vms); + unsigned int max_cpus =3D ms->smp.max_cpus; + DeviceState *cpudev =3D DEVICE(cs); + DeviceState *gicdev =3D vms->gic; + int cpu =3D CPU(cs)->cpu_index; + int type =3D vms->gic_version; + int irq, num_gpio_in; + + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_disconnect_gpio_out_named(cpudev, NULL, irq); + } + + if (type !=3D VIRT_GIC_VERSION_2) { + qdev_disconnect_gpio_out_named(cpudev, "gicv3-maintenance-interrup= t", + 0); + } else if (vms->virt) { + qdev_disconnect_gpio_out_named(gicdev, SYSBUS_DEVICE_GPIO_IRQ, + cpu + 4 * max_cpus); + } + + /* + * RFC: Question: This currently does not takes care of intimating the + * devices which might be sitting on system bus. Do we need a + * sysbus_disconnect_irq() which also does the job of notification bes= ide + * disconnection? + */ + qdev_disconnect_gpio_out_named(cpudev, "pmu-interrupt", 0); + + /* Unwire GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to CPU */ + num_gpio_in =3D (vms->gic_version !=3D VIRT_GIC_VERSION_2) ? + NUM_GPIO_IN : NUM_GICV2_GP= IO_IN; + for (irq =3D 0; irq < num_gpio_in; irq++) { + qdev_disconnect_gpio_out_named(gicdev, SYSBUS_DEVICE_GPIO_IRQ, + cpu + irq * max_cpus); + } +} + +static void wire_gic_cpu_irqs(VirtMachineState *vms, CPUState *cs) +{ + MachineState *ms =3D MACHINE(vms); + unsigned int max_cpus =3D ms->smp.max_cpus; + DeviceState *cpudev =3D DEVICE(cs); + DeviceState *gicdev =3D vms->gic; + int cpu =3D CPU(cs)->cpu_index; + int type =3D vms->gic_version; + SysBusDevice *gicbusdev; + int intidbase; + int irqn; + + intidbase =3D NUM_IRQS + cpu * GIC_INTERNAL; + + for (irqn =3D 0; irqn < ARRAY_SIZE(timer_irq); irqn++) { + qdev_connect_gpio_out(cpudev, irqn, + qdev_get_gpio_in(gicdev, + intidbase + timer_irq[irqn]= )); + } + + gicbusdev =3D SYS_BUS_DEVICE(gicdev); + if (type !=3D VIRT_GIC_VERSION_2) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + intidbase + ARCH_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", + 0, irq); + } else if (vms->virt) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + intidbase + ARCH_GIC_MAINT_IRQ); + sysbus_connect_irq(gicbusdev, cpu + 4 * max_cpus, irq); + } + + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, + qdev_get_gpio_in(gicdev, + intidbase + VIRTUAL_PMU_I= RQ)); + + sysbus_connect_irq(gicbusdev, cpu, qdev_get_gpio_in(cpudev, ARM_CPU_IR= Q)); + sysbus_connect_irq(gicbusdev, cpu + max_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicbusdev, cpu + 2 * max_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicbusdev, cpu + 3 * max_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { + sysbus_connect_irq(gicbusdev, cpu + 4 * max_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); + sysbus_connect_irq(gicbusdev, cpu + 5 * max_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); + } +} + static void create_gic(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); @@ -868,54 +969,7 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) * CPU's inputs. */ for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); - int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; - /* Mapping from the output timer irq lines from the CPU to the - * GIC PPI inputs we use for the virt board. - */ - const int timer_irq[] =3D { - [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, - [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, - [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, - [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, - [GTIMER_HYPVIRT] =3D ARCH_TIMER_NS_EL2_VIRT_IRQ, - }; - - for (unsigned irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { - qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(vms->gic, - intidbase + timer_irq[i= rq])); - } - - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - intidbase + ARCH_GIC_MAINT_IRQ= ); - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", - 0, irq); - } else if (vms->virt) { - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - intidbase + ARCH_GIC_MAINT_IRQ= ); - sysbus_connect_irq(gicbusdev, i + 4 * max_cpus, irq); - } - - qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(vms->gic, intidbase - + VIRTUAL_PMU_IRQ)); - - sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); - sysbus_connect_irq(gicbusdev, i + max_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); - sysbus_connect_irq(gicbusdev, i + 2 * max_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); - sysbus_connect_irq(gicbusdev, i + 3 * max_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); - - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); - sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); - } + wire_gic_cpu_irqs(vms, qemu_get_cpu(i)); } =20 fdt_add_gic_node(vms); @@ -3089,7 +3143,7 @@ static void virt_cpu_pre_plug(HotplugHandler *hotplug= _dev, DeviceState *dev, */ if (vms->acpi_dev) { /* TODO: update GIC about this hotplug change here */ - /* TODO: wire the GIC<->CPU irqs */ + wire_gic_cpu_irqs(vms, cs); } } =20 @@ -3172,7 +3226,7 @@ static void virt_cpu_unplug(HotplugHandler *hotplug_d= ev, DeviceState *dev, =20 /* TODO: update the acpi cpu hotplug state for cpu hot-unplug */ =20 - /* TODO: unwire the gic-cpu irqs here */ + unwire_gic_cpu_irqs(vms, cs); /* TODO: update the GIC about this hot unplug change */ =20 /* TODO: unregister cpu for reset & update F/W info for the next boot = */ diff --git a/hw/core/gpio.c b/hw/core/gpio.c index 80d07a6ec9..abb164d5c0 100644 --- a/hw/core/gpio.c +++ b/hw/core/gpio.c @@ -143,7 +143,7 @@ qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, = const char *name, int n) =20 /* disconnect a GPIO output, returning the disconnected input (if any) */ =20 -static qemu_irq qdev_disconnect_gpio_out_named(DeviceState *dev, +qemu_irq qdev_disconnect_gpio_out_named(DeviceState *dev, const char *name, int n) { char *propname =3D g_strdup_printf("%s[%d]", diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index aa97c34a4b..71f169718c 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -739,6 +739,8 @@ qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, = const char *name, int n); */ qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt, const char *name, int n); +qemu_irq qdev_disconnect_gpio_out_named(DeviceState *dev, + const char *name, int n); =20 BusState *qdev_get_child_bus(DeviceState *dev, const char *name); =20 diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b497667d61..e49fb096de 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -37,13 +37,17 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) =20 /* Meanings of the ARMCPU object's seven inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 -#define ARM_CPU_NMI 4 -#define ARM_CPU_VINMI 5 -#define ARM_CPU_VFNMI 6 +enum { + ARM_CPU_IRQ =3D 0, + ARM_CPU_FIQ =3D 1, + ARM_CPU_VIRQ =3D 2, + ARM_CPU_VFIQ =3D 3, + NUM_GICV2_GPIO_IN =3D (ARM_CPU_VFIQ+1), + ARM_CPU_NMI =3D 4, + ARM_CPU_VINMI =3D 5, + /* ARM_CPU_VFNMI =3D 6, */ /* not used? */ + NUM_GPIO_IN =3D (ARM_CPU_VINMI+1), +}; =20 /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first element --=20 2.34.1