From nobody Wed Oct 23 00:23:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728986788; cv=none; d=zohomail.com; s=zohoarc; b=XrUSgYZwr6ZW3QzSxIom9Nta3n4r4+YuMnJVspbaqxW0Dyam6E49IOXNB1X/Xq1GC6Hm3Qn31OSPnibNB/+76tm9uqONx6qgQIZYhOMF5NtS3Rgs11N0Xo97WQKdVmJT44fmDsKMGGgWVyR/PHoHZFZfnTn4F5jBhsgwpRrMiIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728986788; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=2iEdWYHhMXNeq0WtMjLtROqrDM5oN/5U94NE8jtz+JQ=; b=NYk6v9ps2VN4u9ipd1YNOtfvPK0A2EcdwNk3fNrn/8B1cLn0lpvtOfVgu2J15K7zbeZ0cmfNAWLTGhbmpPTFKVXsNbhDVt7pybWbKQMnd5qXennN4QelaSK67SVsimE/RYeWFx+w0mwzDu0X4s8k8/VEvuhkomeed6W8huN7brI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728986788665137.30298047732083; Tue, 15 Oct 2024 03:06:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0eRR-0001TI-HB; Tue, 15 Oct 2024 06:06:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eRP-0001AP-1i; Tue, 15 Oct 2024 06:06:11 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eRL-0001bv-1Z; Tue, 15 Oct 2024 06:06:09 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XSV7b2GYpz6FH29; Tue, 15 Oct 2024 18:04:27 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 83382140451; Tue, 15 Oct 2024 18:06:04 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.48.146.149) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Oct 2024 12:05:44 +0200 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V5 15/30] hw/arm/acpi: MADT Tbl change to size the guest with possible vCPUs Date: Tue, 15 Oct 2024 10:59:57 +0100 Message-ID: <20241015100012.254223-16-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015100012.254223-1-salil.mehta@huawei.com> References: <20241015100012.254223-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.146.149] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728986788856116600 Content-Type: text/plain; charset="utf-8" When QEMU builds the MADT table, modifications are needed to include inform= ation about possible vCPUs that are exposed as ACPI-disabled (i.e., `_STA.Enabled= =3D0`). This new information will help the guest kernel pre-size its resources duri= ng boot time. Pre-sizing based on possible vCPUs will facilitate the future hot-plugging of the currently disabled vCPUs. Additionally, this change addresses updates to the ACPI MADT GIC CPU interf= ace flags, as introduced in the UEFI ACPI 6.5 specification. These updates enab= le deferred virtual CPU onlining in the guest kernel. Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.ht= ml#gic-cpu-interface-gicc-structure Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++------ include/hw/acpi/cpu.h | 19 +++++++++++++++++++ 2 files changed, 49 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 32238170ab..ff104b3496 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -663,6 +663,29 @@ static void build_append_gicr(GArray *table_data, uint= 64_t base, uint32_t size) build_append_int_noprefix(table_data, size, 4); /* Discovery Range Len= gth */ } =20 +static uint32_t virt_acpi_get_gicc_flags(CPUState *cpu) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(qdev_get_machine()); + + /* can only exist in 'enabled' state */ + if (!mc->has_hotpluggable_cpus) { + return 1; + } + + /* + * ARM GIC CPU Interface can be 'online-capable' or 'enabled' at boot + * We MUST set 'online-capable' bit for all hotpluggable CPUs except t= he + * first/boot CPU. Cold-booted CPUs without 'Id' can also be unplugged. + * Though as-of-now this is only used as a debugging feature. + * + * UEFI ACPI Specification 6.5 + * Section: 5.2.12.14. GIC CPU Interface (GICC) Structure + * Table: 5.37 GICC CPU Interface Flags + * Link: https://uefi.org/specs/ACPI/6.5 + */ + return cpu && !cpu->cpu_index ? 1 : (1 << 3); +} + static void build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { @@ -689,12 +712,13 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, vms->gic_version, 1); build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 - for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); + for (i =3D 0; i < MACHINE(vms)->smp.max_cpus; i++) { + CPUState *cpu =3D qemu_get_possible_cpu(i); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; uint32_t vgic_interrupt =3D vms->virt ? ARCH_GIC_MAINT_IRQ : 0; - uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? - VIRTUAL_PMU_IRQ : 0; + uint32_t pmu_interrupt =3D vms->pmu ? VIRTUAL_PMU_IRQ : 0; + uint32_t flags =3D virt_acpi_get_gicc_flags(cpu); + uint64_t mpidr =3D acpi_get_cpu_archid(i); =20 if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { physical_base_address =3D memmap[VIRT_GIC_CPU].base; @@ -709,7 +733,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, i, 4); /* GIC ID */ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor = UID */ /* Flags */ - build_append_int_noprefix(table_data, 1, 4); /* Enabled */ + build_append_int_noprefix(table_data, flags, 4); /* Parking Protocol Version */ build_append_int_noprefix(table_data, 0, 4); /* Performance Interrupt GSIV */ @@ -723,7 +747,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, vgic_interrupt, 4); build_append_int_noprefix(table_data, 0, 8); /* GICR Base Addre= ss*/ /* MPIDR */ - build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu),= 8); + build_append_int_noprefix(table_data, mpidr, 8); /* Processor Power Efficiency Class */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index bd3f9973c9..c688bb2141 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -96,4 +96,23 @@ static inline bool acpi_persistent_cpu(CPUState *cpu) */ return cpu && cpu->acpi_persistent; } + +/** + * acpi_get_cpu_archid: + * @cpu_index: possible vCPU for which arch-id needs to be retreived + * + * Fetches the vCPU arch-id of the possible vCPU. This should be same + * same as the one configured at KVM Host. + * + * Returns: arch-id of the possible vCPU + */ +static inline uint64_t acpi_get_cpu_archid(int cpu_index) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + const CPUArchIdList *possible_cpus =3D ms->possible_cpus; + + assert((cpu_index >=3D 0) && (cpu_index < possible_cpus->len)); + + return possible_cpus->cpus[cpu_index].arch_id; +} #endif --=20 2.34.1