From nobody Wed Oct 23 00:39:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1728986709; cv=none; d=zohomail.com; s=zohoarc; b=afkHYRQ3GIiHkZQEAkXDxohKPbduMtFw2vEHfn/lOT3eTpRAd4x/y1HlZglq64CdJtPW5BwboFTrQys1dbtVURS337+w7CwC3wjOdXsnNJBz7Grw+ZIpda3xMioYhS099SAZ1rltAff8wUMRjK9nnLpTfG4RQrAI86hC8lpLEmg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728986709; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=CMoV7zZUALGj6hBtSl65gVsUqE4OQrZg6akQzjwVytE=; b=hHCl2pIwW1Tt8Vyyjx//XKTG6TvSn2mng3A/DzCmS5Po5qPnPzOr+WgX3HP3oTWLR7aJE0GJadzrQ67hkx00ogPZWMGrZzJD9D8c7IZqJbTaI19MRC2NTR9BsAcLzrluXjTqAr9/JJ5rdHXbnwv83+4RCzeVTAWPDHPJW8YP9ik= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728986709054330.77190192791693; Tue, 15 Oct 2024 03:05:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0eQA-00077S-Ro; Tue, 15 Oct 2024 06:04:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eQ7-0006zN-J4; Tue, 15 Oct 2024 06:04:52 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0eQ4-0001Is-IU; Tue, 15 Oct 2024 06:04:51 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XSV630ltTz6FH25; Tue, 15 Oct 2024 18:03:07 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 4FCC61400D9; Tue, 15 Oct 2024 18:04:44 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.48.146.149) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Oct 2024 12:04:24 +0200 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V5 11/30] arm/virt: Init PMU at host for all possible vCPUs Date: Tue, 15 Oct 2024 10:59:53 +0100 Message-ID: <20241015100012.254223-12-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015100012.254223-1-salil.mehta@huawei.com> References: <20241015100012.254223-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.146.149] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500007.china.huawei.com (7.182.85.172) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728986710532116600 Content-Type: text/plain; charset="utf-8" The PMU for all possible vCPUs must be initialized during VM initialization. Refactor the existing code to accommodate possible vCPUs. This assumes that= all processors being used are identical. It is an architectural constraint of A= RM CPUs that all vCPUs MUST have identical feature sets, at least until the ARM specification is updated to allow otherwise. Past discussion for reference: Link: https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00131.html Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt.c | 9 +++++---- include/hw/arm/virt.h | 1 + include/hw/core/cpu.h | 5 +++++ 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b9df428049..6ac2d8826e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2035,12 +2035,13 @@ static void finalize_gic_version(VirtMachineState *= vms) */ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) { + CPUArchIdList *possible_cpus =3D vms->parent.possible_cpus; int max_cpus =3D MACHINE(vms)->smp.max_cpus; - bool aarch64, pmu, steal_time; + bool aarch64, steal_time; CPUState *cpu; =20 aarch64 =3D object_property_get_bool(OBJECT(first_cpu), "aarch64", NUL= L); - pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); + vms->pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); steal_time =3D object_property_get_bool(OBJECT(first_cpu), "kvm-steal-time", NULL); =20 @@ -2067,8 +2068,8 @@ static void virt_cpu_post_init(VirtMachineState *vms,= MemoryRegion *sysmem) memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); } =20 - CPU_FOREACH(cpu) { - if (pmu) { + CPU_FOREACH_POSSIBLE(cpu, possible_cpus) { + if (vms->pmu) { assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); if (kvm_irqchip_in_kernel()) { kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index b5bfb75f71..98ce68eae1 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -161,6 +161,7 @@ struct VirtMachineState { bool mte; bool dtb_randomness; bool second_ns_uart_present; + bool pmu; OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0be1984698..4a74c383ab 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -618,6 +618,11 @@ extern CPUTailQ cpus_queue; #define CPU_FOREACH_SAFE(cpu, next_cpu) \ QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) =20 +#define CPU_FOREACH_POSSIBLE(cpu, poslist) \ + for (int iter =3D 0; \ + iter < (poslist)->len && ((cpu) =3D (poslist)->cpus[iter].cpu, 1)= ; \ + iter++) + extern __thread CPUState *current_cpu; =20 /** --=20 2.34.1