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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728904958; x=1729509758; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fQQO2T5uiR+FYgD4cQeDW1X+EPKbvqM649D/aATLO28=; b=Rsdz0dKLUyq4qvZLGDmpXelSsVwgsoCPmyjgxL7fVFSGycmF8jIh+M/iuFbLD/gpc+ 05y4bZZiuUIzhFvIXg0z0TwESvvbmvlpDyOEvAyBkKAmzmvdCOQV4lLsHYiBi6O/xhil Z7mIxHVcNkwbXzEalMqWcOIgwRVujZ2SgqUf/hfe5Y+1NRKpqQyzh9cK6DAPJOznnCdl 9sKZXgUeoFOtCfYIX84MniyHVMuU1O3YEmIfwRXFBEQ+Ps07guxa3ulN6tFJCZDsQ/vF aWR6uqbDGfEjdbnkWno1B87lyNgyb2JCfn+pKDspDZpvu1RJ6bm3OsqYd7wa0zm8siAo /32A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728904958; x=1729509758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fQQO2T5uiR+FYgD4cQeDW1X+EPKbvqM649D/aATLO28=; b=iOQRbVdxy66VvlOpGRrDXYwvczA7br1FFk054Dp6n5IRC0j50p6zpBdYNgUe1iBmJa F7bqRBWaaNYqJkknrl5z433bDlkQOai6stPEX5XUPMvr42MeyEChJkPqCDMaA/mJvJRU 6Hx27mVzp7EwMM7oR8FuEZBNtOVwOSKgWSty8/Oab2u1fTE6mcsiHbOs6w9/2Q2RepM/ mCIYcP74xwnJg+iOzpSHmMn+EAytiaAR0+3QwtFPCyS7zOHFebYMgtfK4YLDJAnneaRV j2n8916X34pLQIRWEv1oW4xXgqxBwyhJDwsI9oY+i7YifhrrgdmwWXVAFskNaAmF2xVC yfVg== X-Forwarded-Encrypted: i=1; AJvYcCWQaPRWFt94LYxrqZsJnWrw/i9gNrkeXs+OVDzmt/hhs0N9DKwzYhRgLeOh5PgYHOO5Fd8N4JjUhcDy@nongnu.org X-Gm-Message-State: AOJu0Yz3Cazfd2EKoqlFv9tDDoTc9jdEczY4CmY0C9wKhg0KTFvMmnHT WrHEx4uzb1PPyVeXZjYTwhUsWFwqB1h1MM6gF/nC/n/pV7K6KUSp9x2n8CjFBdA= X-Google-Smtp-Source: AGHT+IEjYxqgLJ2n8zlhNXgKVsYmlQ03KfR0qpjFGlsWbLm/7uQv5GlqIwVpRXnShmdSKGUsKvnKTw== X-Received: by 2002:adf:ffc5:0:b0:374:c1c5:43ca with SMTP id ffacd0b85a97d-37d5ffa3561mr6197519f8f.32.1728904957840; Mon, 14 Oct 2024 04:22:37 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 5/8] target/riscv: Add Smdbltrp CSRs handling Date: Mon, 14 Oct 2024 13:22:15 +0200 Message-ID: <20241014112225.90297-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1728905062436116600 Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 15 +++++++++++++++ 4 files changed, 20 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4a146bb637..53e3bb6b37 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -946,6 +946,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType= type) env->mstatus_hs =3D set_field(env->mstatus_hs, MSTATUS64_UXL, env->misa_mxl); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 1); + } } env->mcause =3D 0; env->miclaim =3D MIP_SGEIP; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5557a86348..62bab1bf55 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -561,6 +561,7 @@ #define MSTATUS_SDT 0x01000000 #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index dd804f95d4..4c4caa2b39 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,6 +78,7 @@ struct RISCVCPUConfig { bool ext_sstc; bool ext_smcntrpmf; bool ext_ssdbltrp; + bool ext_smdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d8280ec956..cc1940447a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1617,6 +1617,14 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, } } =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |=3D MSTATUS_MDT; + if ((val & MSTATUS_MDT) !=3D 0) { + mstatus &=3D ~MSTATUS_MIE; + val &=3D ~MSTATUS_MIE; + } + } + if (xl !=3D MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |=3D MSTATUS_MPV | MSTATUS_GVA; @@ -1655,6 +1663,13 @@ static RISCVException write_mstatush(CPURISCVState *= env, int csrno, uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA = : 0; =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |=3D MSTATUS_MDT; + if ((val & MSTATUS_MDT) !=3D 0) { + env->mstatus &=3D ~MSTATUS_MIE; + val &=3D ~MSTATUS_MIE; + } + } env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 return RISCV_EXCP_NONE; --=20 2.45.2