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@linaro.org) X-ZM-MESSAGEID: 1728903103406116600 Signed-off-by: Manos Pitsidianakis --- target/arm/cpu-features.h | 5 + target/arm/helper.c | 366 +++++++++++++++++++++++++++---------------= ---- 2 files changed, 218 insertions(+), 153 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 04ce2818263e2c3b99c59940001b65302e1d26d2..b4dcd429c3540e18c44d3c30f82= f030be45719f2 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -970,6 +970,11 @@ static inline bool isar_feature_aa64_sme_fa64(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); } =20 +static inline bool isar_feature_aa64_xs(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64isar1, ID_AA64ISAR1, XS) >=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f77b40734f2db831254a0e4eb205751aec0d1e5..3104a2d1dab6e58bf454c75afd4= 78ec6d5fe521f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5671,98 +5671,111 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ - { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, accessfn, type, fgt= , \ + writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + accessfn, type, fgt, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, accessfn, type, fgt, writefn } + TLBI(.name =3D "TLBI_VMALLE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVMALLE1IS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_ASIDE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIASIDE1IS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAAE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVALE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VAALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAALE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VMALLE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVMALLE1, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1_write), + TLBI(.name =3D "TLBI_VAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVAE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), + TLBI(.name =3D "TLBI_ASIDE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIASIDE1, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1_write), + TLBI(.name =3D "TLBI_VAAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVAAE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), + TLBI(.name =3D "TLBI_VALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVALE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), + TLBI(.name =3D "TLBI_VAALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVAALE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, \ + type, writefn }, \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,\ + access, type, writefn } + TLBI(.name =3D "TLBI_IPAS2E1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, - { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1is_write), + TLBI(.name =3D "TLBI_IPAS2LE1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, - { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1is_write), + TLBI(.name =3D "TLBI_ALLE1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), + TLBI(.name =3D "TLBI_VMALLS12E1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), + TLBI(.name =3D "TLBI_IPAS2E1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, - { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1_write), + TLBI(.name =3D "TLBI_IPAS2LE1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, - { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1_write), + TLBI(.name =3D "TLBI_ALLE1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1_write }, - { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1_write), + TLBI(.name =3D "TLBI_VMALLS12E1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write), +#undef TLBI #ifndef CONFIG_USER_ONLY /* 64 bit address translation operations */ { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, @@ -5819,41 +5832,49 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D par_write }, #endif /* TLB invalidate last level of translation table walk */ - { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, +#define TLBI(name, cp, opc1, crn, crm, opc2, type, access, accessfn, write= fn)\ +{ name, cp, opc1, crn, crm, opc2, type, access, accessfn, writefn }, = \ +{ name"NXS", cp, opc1, crn + 1, crm, opc2, type, access, accessfn, writefn= } + TLBI(.name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimva_is_write }, - { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, + .writefn =3D tlbimva_is_write), + TLBI(.name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimvaa_is_write }, - { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, + .writefn =3D tlbimvaa_is_write), + TLBI(.name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, - { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, + .writefn =3D tlbimva_write), + TLBI(.name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_write }, - { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, + .writefn =3D tlbimvaa_write), +#undef TLBI +#define TLBI(name, cp, opc1, crn, crm, opc2, type, access, writefn)\ +{ name, cp, opc1, crn, crm, opc2, type, access, writefn }, \ +{ name"NXS", cp, opc1, crn + 1, crm, opc2, type, access, writefn } + TLBI(.name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, - { .name =3D "TLBIMVALHIS", + .writefn =3D tlbimva_hyp_write), + TLBI(.name =3D "TLBIMVALHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, - { .name =3D "TLBIIPAS2", + .writefn =3D tlbimva_hyp_is_write), + TLBI(.name =3D "TLBIIPAS2", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_hyp_write }, - { .name =3D "TLBIIPAS2IS", + .writefn =3D tlbiipas2_hyp_write), + TLBI(.name =3D "TLBIIPAS2IS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2is_hyp_write }, - { .name =3D "TLBIIPAS2L", + .writefn =3D tlbiipas2is_hyp_write), + TLBI(.name =3D "TLBIIPAS2L", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_hyp_write }, - { .name =3D "TLBIIPAS2LIS", + .writefn =3D tlbiipas2_hyp_write), + TLBI(.name =3D "TLBIIPAS2LIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2is_hyp_write }, + .writefn =3D tlbiipas2is_hyp_write), +#undef TLBI /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab = }, @@ -7829,207 +7850,245 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { }; =20 static const ARMCPRegInfo tlbirange_reginfo[] =3D { - { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, accessfn, type, fgt= , \ + writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + accessfn, type, fgt, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, accessfn, type, fgt, writefn } + TLBI(.name =3D "TLBI_RVAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAAE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVALE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAALE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAAE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVALE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAALE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVAE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), + TLBI(.name =3D "TLBI_RVAAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVAAE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), + TLBI(.name =3D "TLBI_RVALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVALE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), + TLBI(.name =3D "TLBI_RVAALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVAALE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + type, writefn }, \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, type, writefn } + TLBI(.name =3D "TLBI_RIPAS2E1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1is_write }, - { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1is_write), + TLBI(.name =3D "TLBI_RIPAS2LE1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1is_write }, - { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1is_write), + TLBI(.name =3D "TLBI_RVAE2IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RVALE2IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RIPAS2E1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1_write }, - { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1_write), + TLBI(.name =3D "TLBI_RIPAS2LE1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1_write }, - { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1_write), + TLBI(.name =3D "TLBI_RVAE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RVALE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RVAE2", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2_write }, - { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2_write), + TLBI(.name =3D "TLBI_RVALE2", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2_write }, - { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2_write), + TLBI(.name =3D "TLBI_RVAE3IS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVALE3IS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVAE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVALE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVAE3", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3_write }, - { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3_write), + TLBI(.name =3D "TLBI_RVALE3", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3_write }, + .writefn =3D tlbi_aa64_rvae3_write), +#undef TLBI }; =20 static const ARMCPRegInfo tlbios_reginfo[] =3D { - { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, accessfn, type, fgt= , \ + writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + accessfn, type, fgt, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, accessfn, type, fgt, writefn } + TLBI(.name =3D "TLBI_VMALLE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVMALLE1OS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .fgt =3D FGT_TLBIVAE1OS, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_ASIDE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIASIDE1OS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAAE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVALE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VAALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAALE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + type, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, type, writefn } + TLBI(.name =3D "TLBI_ALLE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle2is_write), + TLBI(.name =3D "TLBI_VAE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae2is_write), + TLBI(.name =3D "TLBI_ALLE1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), + TLBI(.name =3D "TLBI_VALE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae2is_write), + TLBI(.name =3D "TLBI_VMALLS12E1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type) \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, \ + type }, \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,\ + access, type } + TLBI(.name =3D "TLBI_IPAS2E1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), + TLBI(.name =3D "TLBI_RIPAS2E1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), + TLBI(.name =3D "TLBI_IPAS2LE1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), + TLBI(.name =3D "TLBI_RIPAS2LE1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + type, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, type, writefn } + TLBI(.name =3D "TLBI_ALLE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, - { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle3is_write), + TLBI(.name =3D "TLBI_VAE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae3is_write), + TLBI(.name =3D "TLBI_VALE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, + .writefn =3D tlbi_aa64_vae3is_write), +#undef TLBI }; =20 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) @@ -9201,7 +9260,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) R_ID_AA64ISAR1_SB_MASK | R_ID_AA64ISAR1_BF16_MASK | R_ID_AA64ISAR1_DGH_MASK | - R_ID_AA64ISAR1_I8MM_MASK }, + R_ID_AA64ISAR1_I8MM_MASK | + R_ID_AA64ISAR1_XS_MASK }, { .name =3D "ID_AA64ISAR2_EL1", .exported_bits =3D R_ID_AA64ISAR2_WFXT_MASK | R_ID_AA64ISAR2_RPRES_MASK | --=20 2.45.2