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@linaro.org) X-ZM-MESSAGEID: 1728903103406116600 Signed-off-by: Manos Pitsidianakis --- target/arm/cpu-features.h | 5 + target/arm/helper.c | 366 +++++++++++++++++++++++++++---------------= ---- 2 files changed, 218 insertions(+), 153 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 04ce2818263e2c3b99c59940001b65302e1d26d2..b4dcd429c3540e18c44d3c30f82= f030be45719f2 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -970,6 +970,11 @@ static inline bool isar_feature_aa64_sme_fa64(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); } =20 +static inline bool isar_feature_aa64_xs(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64isar1, ID_AA64ISAR1, XS) >=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f77b40734f2db831254a0e4eb205751aec0d1e5..3104a2d1dab6e58bf454c75afd4= 78ec6d5fe521f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5671,98 +5671,111 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ - { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, accessfn, type, fgt= , \ + writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + accessfn, type, fgt, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, accessfn, type, fgt, writefn } + TLBI(.name =3D "TLBI_VMALLE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVMALLE1IS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_ASIDE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIASIDE1IS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAAE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVALE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VAALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAALE1IS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VMALLE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVMALLE1, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1_write), + TLBI(.name =3D "TLBI_VAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVAE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), + TLBI(.name =3D "TLBI_ASIDE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIASIDE1, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1_write), + TLBI(.name =3D "TLBI_VAAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVAAE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), + TLBI(.name =3D "TLBI_VALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVALE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), + TLBI(.name =3D "TLBI_VAALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIVAALE1, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, \ + type, writefn }, \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,\ + access, type, writefn } + TLBI(.name =3D "TLBI_IPAS2E1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, - { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1is_write), + TLBI(.name =3D "TLBI_IPAS2LE1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, - { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1is_write), + TLBI(.name =3D "TLBI_ALLE1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), + TLBI(.name =3D "TLBI_VMALLS12E1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), + TLBI(.name =3D "TLBI_IPAS2E1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, - { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1_write), + TLBI(.name =3D "TLBI_IPAS2LE1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, - { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ipas2e1_write), + TLBI(.name =3D "TLBI_ALLE1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1_write }, - { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1_write), + TLBI(.name =3D "TLBI_VMALLS12E1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, + .writefn =3D tlbi_aa64_alle1is_write), +#undef TLBI #ifndef CONFIG_USER_ONLY /* 64 bit address translation operations */ { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, @@ -5819,41 +5832,49 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D par_write }, #endif /* TLB invalidate last level of translation table walk */ - { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, +#define TLBI(name, cp, opc1, crn, crm, opc2, type, access, accessfn, write= fn)\ +{ name, cp, opc1, crn, crm, opc2, type, access, accessfn, writefn }, = \ +{ name"NXS", cp, opc1, crn + 1, crm, opc2, type, access, accessfn, writefn= } + TLBI(.name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimva_is_write }, - { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, + .writefn =3D tlbimva_is_write), + TLBI(.name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, - .writefn =3D tlbimvaa_is_write }, - { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, + .writefn =3D tlbimvaa_is_write), + TLBI(.name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, - { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, + .writefn =3D tlbimva_write), + TLBI(.name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_write }, - { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, + .writefn =3D tlbimvaa_write), +#undef TLBI +#define TLBI(name, cp, opc1, crn, crm, opc2, type, access, writefn)\ +{ name, cp, opc1, crn, crm, opc2, type, access, writefn }, \ +{ name"NXS", cp, opc1, crn + 1, crm, opc2, type, access, writefn } + TLBI(.name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, - { .name =3D "TLBIMVALHIS", + .writefn =3D tlbimva_hyp_write), + TLBI(.name =3D "TLBIMVALHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, - { .name =3D "TLBIIPAS2", + .writefn =3D tlbimva_hyp_is_write), + TLBI(.name =3D "TLBIIPAS2", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_hyp_write }, - { .name =3D "TLBIIPAS2IS", + .writefn =3D tlbiipas2_hyp_write), + TLBI(.name =3D "TLBIIPAS2IS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2is_hyp_write }, - { .name =3D "TLBIIPAS2L", + .writefn =3D tlbiipas2is_hyp_write), + TLBI(.name =3D "TLBIIPAS2L", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_hyp_write }, - { .name =3D "TLBIIPAS2LIS", + .writefn =3D tlbiipas2_hyp_write), + TLBI(.name =3D "TLBIIPAS2LIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2is_hyp_write }, + .writefn =3D tlbiipas2is_hyp_write), +#undef TLBI /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab = }, @@ -7829,207 +7850,245 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { }; =20 static const ARMCPRegInfo tlbirange_reginfo[] =3D { - { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, accessfn, type, fgt= , \ + writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + accessfn, type, fgt, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, accessfn, type, fgt, writefn } + TLBI(.name =3D "TLBI_RVAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAAE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAAE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVALE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAALE1IS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAALE1IS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAAE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVALE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIRVAALE1OS, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1is_write), + TLBI(.name =3D "TLBI_RVAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVAE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), + TLBI(.name =3D "TLBI_RVAAE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVAAE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), + TLBI(.name =3D "TLBI_RVALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVALE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), + TLBI(.name =3D "TLBI_RVAALE1", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .fgt =3D FGT_TLBIRVAALE1, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae1_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + type, writefn }, \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, type, writefn } + TLBI(.name =3D "TLBI_RIPAS2E1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1is_write }, - { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1is_write), + TLBI(.name =3D "TLBI_RIPAS2LE1IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1is_write }, - { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1is_write), + TLBI(.name =3D "TLBI_RVAE2IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RVALE2IS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RIPAS2E1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1_write }, - { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1_write), + TLBI(.name =3D "TLBI_RIPAS2LE1", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ripas2e1_write }, - { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_ripas2e1_write), + TLBI(.name =3D "TLBI_RVAE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RVALE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2is_write), + TLBI(.name =3D "TLBI_RVAE2", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2_write }, - { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2_write), + TLBI(.name =3D "TLBI_RVALE2", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_rvae2_write }, - { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae2_write), + TLBI(.name =3D "TLBI_RVAE3IS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVALE3IS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVAE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVALE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3is_write), + TLBI(.name =3D "TLBI_RVAE3", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3_write }, - { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_rvae3_write), + TLBI(.name =3D "TLBI_RVALE3", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3_write }, + .writefn =3D tlbi_aa64_rvae3_write), +#undef TLBI }; =20 static const ARMCPRegInfo tlbios_reginfo[] =3D { - { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, accessfn, type, fgt= , \ + writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + accessfn, type, fgt, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, accessfn, type, fgt, writefn } + TLBI(.name =3D "TLBI_VMALLE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVMALLE1OS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .fgt =3D FGT_TLBIVAE1OS, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_ASIDE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIASIDE1OS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vmalle1is_write), + TLBI(.name =3D "TLBI_VAAE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAAE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVALE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), + TLBI(.name =3D "TLBI_VAALE1OS", .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, .fgt =3D FGT_TLBIVAALE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae1is_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + type, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, type, writefn } + TLBI(.name =3D "TLBI_ALLE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle2is_write), + TLBI(.name =3D "TLBI_VAE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae2is_write), + TLBI(.name =3D "TLBI_ALLE1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), + TLBI(.name =3D "TLBI_VALE2OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae2is_write), + TLBI(.name =3D "TLBI_VMALLS12E1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle1is_write), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type) \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, \ + type }, \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,\ + access, type } + TLBI(.name =3D "TLBI_IPAS2E1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), + TLBI(.name =3D "TLBI_RIPAS2E1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), + TLBI(.name =3D "TLBI_IPAS2LE1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), + TLBI(.name =3D "TLBI_RIPAS2LE1OS", .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .access =3D PL2_W, .type =3D ARM_CP_NOP), +#undef TLBI +#define TLBI(name, opc0, opc1, crn, crm, opc2, access, type, writefn) = \ +{ name, .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn, crm, opc2, access, = \ + type, writefn }, = \ +{ name"NXS", .state =3D ARM_CP_STATE_AA64, opc0, opc1, crn + 1, crm, opc2,= \ + access, type, writefn } + TLBI(.name =3D "TLBI_ALLE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, - { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_alle3is_write), + TLBI(.name =3D "TLBI_VAE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64, + .writefn =3D tlbi_aa64_vae3is_write), + TLBI(.name =3D "TLBI_VALE3OS", .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, + .writefn =3D tlbi_aa64_vae3is_write), +#undef TLBI }; =20 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) @@ -9201,7 +9260,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) R_ID_AA64ISAR1_SB_MASK | R_ID_AA64ISAR1_BF16_MASK | R_ID_AA64ISAR1_DGH_MASK | - R_ID_AA64ISAR1_I8MM_MASK }, + R_ID_AA64ISAR1_I8MM_MASK | + R_ID_AA64ISAR1_XS_MASK }, { .name =3D "ID_AA64ISAR2_EL1", .exported_bits =3D R_ID_AA64ISAR2_WFXT_MASK | R_ID_AA64ISAR2_RPRES_MASK | --=20 2.45.2 From nobody Sat Nov 23 21:41:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728903101176116600 The DSB nXS variant is always both a reads and writes request type. Ignore the domain field like we do in plain DSB and perform a full system barrier operation. The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7. Signed-off-by: Manos Pitsidianakis --- target/arm/tcg/a64.decode | 3 +++ target/arm/tcg/translate-a64.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 331a8e180c0b14e2abe3ec641a867235574316f7..c4f516abc18224932082cdf3e75= 30edc7a304bc1 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -245,6 +245,9 @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5 =20 CLREX 1101 0101 0000 0011 0011 ---- 010 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 +# For the DSB nXS variant, types always equals MBReqTypes_All and we ignor= e the +# domain bits. +DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111 SB 1101 0101 0000 0011 0011 0000 111 11111 =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 071b6349fc38802a62f4b4056e369c4d8b1ecf94..85e71599203eee62b4d22a0b10e= d676cc815dab6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1959,6 +1959,12 @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_D= MB *a) return true; } =20 +static bool trans_DSB_nXS(DisasContext *ctx, arg_DSB_nXS *a) +{ + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + return true; +} + static bool trans_ISB(DisasContext *s, arg_ISB *a) { /* --=20 2.45.2 From nobody Sat Nov 23 21:41:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1728903092; cv=none; d=zohomail.com; s=zohoarc; b=lRSjl3oerUWQkomTVQIycz1M6xh9zEqlJ/lE8VM9uIQyMHCc2Z3c+RkNJxhmWzIc/rmMxn7zb2ly/3HudxNCZwLytK4d3h9ex0f/QXtcPeTEhcw4OTIFoQO68UzW30c9NYC5K7YxgNxBeVmbm7vgz/HKw7asdbTJWgmPs9BeY7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728903092; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FqdRX8rWWQZot3qHzNkktBViXx6N2VJ6p90ru7IT+NI=; b=MG/SaTi03XBOVtv4WjMdWPs/U36qUBYieQSbFSpk/7UfJtTfcgUJk35oscH7ZqV64GfcWlA8VkQMjTeNeNHnBPT7MpeVrDyiIck7wF5+rx6PDkR8Tc4uPHZEx5ONA0RlMTbciCgMipQM9JA7ZyG6InMAmS1s0u0zj7VUJ7MXCFQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728903092363340.8667250829685; Mon, 14 Oct 2024 03:51:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0Iez-00040F-KD; Mon, 14 Oct 2024 06:50:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0Ier-0003z8-3x for qemu-devel@nongnu.org; Mon, 14 Oct 2024 06:50:37 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0Iep-0006Ui-5a for qemu-devel@nongnu.org; Mon, 14 Oct 2024 06:50:36 -0400 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a99f3a5a44cso192967266b.3 for ; Mon, 14 Oct 2024 03:50:34 -0700 (PDT) Received: from [127.0.1.1] (adsl-161.109.242.225.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728903093282116600 Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register. Signed-off-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/arm/tcg/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 0168920828651492b1114d66ab0fc72c20dda2a8..8c8f88d84151952872f1b1987e9= 8d789b501fb23 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1163,6 +1163,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64isar2; --=20 2.45.2 From nobody Sat Nov 23 21:41:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1728903121; cv=none; d=zohomail.com; s=zohoarc; b=funmAN47L3oFkir+mlFSKhFOBBPb5uZ6QqUjOKd3wLxwiAIMzKBl+O/FFDSPEDMtF8ApAcil4/VuR7n41XaR4I+4Vowj7XQxiWCl5AFsgoEidpj0YOdaios/qw6SBO6FMrwOcJhkq+P5nrzLkU+ehY+vn4Azr+DIGO0KQKM0UOI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728903121; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ME8nUhQFFvx2jCgImr+jNjdB7rn6Qorc/P0rb7qligk=; b=K01BlpAHuPOLyy/LWePGXST5uX1J3qhGxW64MO/wKfw+hnN0BvH5EUGh9aVa53sKGrQ5IwnGu8tC1+rDvRH5V5o/abWrSy0rMv1BpWiaH8gUQ3uQTVRnolA9DH0rzQr3dE2/7KCyfDcyVdQOinpd1qf8KNrw+4oDNUmXStzIALM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172890312163342.61258878094827; Mon, 14 Oct 2024 03:52:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0If5-00042r-6I; Mon, 14 Oct 2024 06:50:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0Ier-0003zh-SW for qemu-devel@nongnu.org; Mon, 14 Oct 2024 06:50:39 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0Ieq-0006V3-Bs for qemu-devel@nongnu.org; Mon, 14 Oct 2024 06:50:37 -0400 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a9a0ec0a94fso119620166b.1 for ; Mon, 14 Oct 2024 03:50:35 -0700 (PDT) Received: from [127.0.1.1] (adsl-161.109.242.225.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728903123261116600 Add system test to make sure FEAT_XS is enabled for max cpu emulation and that QEMU doesn't crash when encountering an NXS instruction variant. Signed-off-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- tests/tcg/aarch64/system/feat-xs.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tests/tcg/aarch64/system/feat-xs.c b/tests/tcg/aarch64/system/= feat-xs.c new file mode 100644 index 0000000000000000000000000000000000000000..52a481c577f9420fa2f6d6a794c= 1f26772cb4bff --- /dev/null +++ b/tests/tcg/aarch64/system/feat-xs.c @@ -0,0 +1,27 @@ +/* + * FEAT_XS Test + * + * Copyright (c) 2024 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +int main(void) +{ + uint64_t isar1; + + asm volatile ("mrs %0, id_aa64isar1_el1" : "=3Dr"(isar1)); + if (((isar1 >> 56) & (0xff)) !=3D 1) { + ml_printf("FEAT_XS not supported by CPU"); + return 1; + } + /* VMALLE1NXS */ + asm volatile (".inst 0xd508971f"); + /* VMALLE1OSNXS */ + asm volatile (".inst 0xd508911f"); + + return 0; +} --=20 2.45.2