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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728857580; x=1729462380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oOELs1GBJLtlq8nQGFT7BbF8Y02om3aScvqBsVkX7+Q=; b=t1H7PVN6m8eHoMXNAjpjy/tQ8bk4o7HLTHpxddvugB3HQPMP2Mq8g6jHVv3/BJHc7+ eWeXZM8KocZS538p/VDxpuMnbRG+bonTLKSDVizWsz1g1OAaU96W1Hzx6veysmLOoZzI rNWzzYG26m5AypyZszrmA+rfHoyZneOD5rrD0q0MNzD1Sb4Q6iNHJl9m+dz7UszaDPbV xWFZFxIVZGgBA9bbdtZAlFg1pudAtZM1aUnyul/QYw4MCw5h9RwFZXmk2H3aI5Urv9Aw nF0MpyGk+USkYm3zD9vV94VXNGQeovyJqCHwFwot0lyr4OrZdukt37qJeD3CbTmIhyfI 3Z9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728857580; x=1729462380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oOELs1GBJLtlq8nQGFT7BbF8Y02om3aScvqBsVkX7+Q=; b=PbRshuBM9p1rFctqMK+uu1wN7ZH8psHfwhQqeRd0QPpNciTzJSmBBgNCiZ4Ze6+taR yW6W6RM0NP4v1MY0OP9IurYVy5MjAfNp/Qr4KFP+76XPL6OA6kUti9j3r8HS0249PX17 xhomq9uArInV0TI5W05RjwQfbAWPbhrBbBdx+IBScTolGi6rL2PwlGPRiwtRS4VU+Kaq RygeULf7845YsmuOTR3BKdtaB5XbvYzg8WKudplfysZYME4gaMGy84hLL4DTmqq6sVsa C0efJPtM/ezYEeyV1tk36cGg8iEQ50aiWI8UKuIEASxZS3Hmg8x9TrZlIkl1akNCJo18 2VPg== X-Gm-Message-State: AOJu0YwyEMepyGH/olrI4XIbDX8Hjwz8FaVRQCz5OwjrdsoyF73PWxfs 5Tq0ZutblXfoOebEQHl4TN+AoJ2iMB6jFzoQNG5MgLsLYuEwwfipL7Ek0AjIgGdGDguwQr/EMGD / X-Google-Smtp-Source: AGHT+IGvF2YTqWLWFscInM+uhdd/nr1DtHKoPW8/pCJ3G3EGGnqFEvq0YbYJn8nIsX1MzrsqXiPPyA== X-Received: by 2002:a17:90b:2242:b0:2e2:a667:1a10 with SMTP id 98e67ed59e1d1-2e2f0f08c2emr11229279a91.38.1728857579842; Sun, 13 Oct 2024 15:12:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 25/27] target/arm: Move device detection earlier in get_phys_addr_lpae Date: Sun, 13 Oct 2024 15:12:33 -0700 Message-ID: <20241013221235.1585193-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728858049280116600 Content-Type: text/plain; charset="utf-8" Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 238b2c92a9..0a1a820362 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2029,8 +2029,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } + + result->cacheattrs.is_s2_format =3D true; + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device =3D S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { int nse, ns =3D extract32(attrs, 5, 1); + uint8_t attrindx; + uint64_t mair; + switch (out_space) { case ARMSS_Root: /* @@ -2102,6 +2114,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, result->f.attrs.space, out_space); + + /* Index into MAIR registers for cache attributes */ + attrindx =3D extract32(attrs, 2, 3); + mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <=3D 7); + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ + } + device =3D S1_attrs_are_device(result->cacheattrs.attrs); } =20 if (!(result->f.prot & (1 << access_type))) { @@ -2131,30 +2156,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, result->f.attrs.space =3D out_space; result->f.attrs.secure =3D arm_space_is_secure(out_space); =20 - if (regime_is_stage2(mmu_idx)) { - result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 2, 4); - /* - * Security state does not really affect HCR_EL2.FWB; - * we only need to filter FWB for aa32 or other FEAT. - */ - device =3D S2_attrs_are_device(arm_hcr_el2_eff(env), - result->cacheattrs.attrs); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 2, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - result->cacheattrs.is_s2_format =3D false; - result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); - - /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ - } - device =3D S1_attrs_are_device(result->cacheattrs.attrs); - } - /* * Enable alignment checks on Device memory. * --=20 2.43.0