From nobody Sun Nov 24 02:01:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1728729117; cv=none; d=zohomail.com; s=zohoarc; b=KSeznm+nhWFWm3Gd+mdyNiZCaiw52EdMaZnP9BmXxhBvhdoc5ZaEsY3o5kYO1GBSKavpe6Z5ft4vbqXlffdybtTiYzHQM0GL+upqFSiTM8zlv55EyUfqFuKabSJ0EMBHNHQu0LFl6AaRQWOeDToeNdcsbxtpgN1lsb4yAstHmcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1728729117; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q9zF/N6hMuRRTkOUgrB/PPOzpXrluyvcKDRv6DZQjcU=; b=m2W0+uf9YLPJQJ2J63JqnGFMGwiVqcTrd7jH1rJu4pEj+IqtLkILXPg5uUl3M3GKl+0a4VX1geinQ+444ZIaBlk4FVMYn5CINfpSfyQ5DP4lLBTzGF2zELt+DidkTsa2Z5Jb7GwTMtxWd4NMqzaATT2OuAHTBkj1ai3tcSz6pjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728729117628262.423833804742; Sat, 12 Oct 2024 03:31:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1szZN1-0003zJ-62; Sat, 12 Oct 2024 06:29:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1szZMy-0003w4-GV; Sat, 12 Oct 2024 06:29:08 -0400 Received: from mgamail.intel.com ([192.198.163.8]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1szZMw-0007EI-R0; Sat, 12 Oct 2024 06:29:08 -0400 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2024 03:29:05 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 12 Oct 2024 03:29:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728728947; x=1760264947; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uqz0CxeEMFYodgXeRDwdMplzhXLtp/KziGXuIPivbUo=; b=fpiW9fxtgqK6xP1u1spfgqu9Nlh474HFs4ouLEiNmUec5E6TrbxLFN3D B62CFYHDOaM3jz9/jmy4wz/IVeXN4DYceOssZ/GRZy57Ex0GcZJnIHrpO ViKjRj9rHf4a0ykft/xOtEgaEsTCZCTbqlDYVw7BVE+aIbX/sAbzNGMkq dEQfUMrluBYLBPFQ/rATtr1XCTyzSgXs+kAdDgxn1jdoFvMKxWB3aic4l 39ABxyBbaI8UpNnB49UjvNmlXjbo6FYpdXz2660nCa4mkS0FBkGeAEjJs 3QCJf9SVkwgbDaIJuRthRjGsrZqD7OEFNucdNGMu/SXiNvZw96Hs15QFX g==; X-CSE-ConnectionGUID: sS7snSsdRoWjhfZlAFpvog== X-CSE-MsgGUID: OmEJkGhRSbmzB4nCBguA2w== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="45634943" X-IronPort-AV: E=Sophos;i="6.11,198,1725346800"; d="scan'208";a="45634943" X-CSE-ConnectionGUID: zpEiaCQ/TIq2/9zNkRBHqQ== X-CSE-MsgGUID: 3VXD5jpMQOiVZMGySxNoPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,198,1725346800"; d="scan'208";a="77050867" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhao Liu , Yongwei Ma Subject: [PATCH v3 6/7] i386/pc: Support cache topology in -machine for PC machine Date: Sat, 12 Oct 2024 18:44:28 +0800 Message-Id: <20241012104429.1048908-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241012104429.1048908-1-zhao1.liu@intel.com> References: <20241012104429.1048908-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.15, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1728729119106116600 Content-Type: text/plain; charset="utf-8" Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v2: * Polished the document. (Jonathan) Changes since Patch v1: * Merged document into this patch. (Markus) Changes since RFC v2: * Used cache_supported array. --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 26 +++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2047633e4cf7..8aea2308dcb9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1791,6 +1791,10 @@ static void pc_machine_class_init(ObjectClass *oc, v= oid *data) mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; mc->smp_props.modules_supported =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_AUTO; =20 diff --git a/qemu-options.hx b/qemu-options.hx index d5afefe5b63c..8a0cd7393f34 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=3D@var{} memory encryption object t= o use (default=3Dnone)\n" " hmat=3Don|off controls ACPI HMAT support (default=3Do= ff)\n" " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n" - " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n", + " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n" + " smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3D= topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=3D]name[,prop=3Dvalue[,...]]`` @@ -159,6 +160,29 @@ SRST :: =20 -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512 + + ``smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3Dtopologylevel`` + Define cache properties for SMP system. + + ``cache=3Dcachename`` specifies the cache that the properties will= be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=3Dtopologylevel`` sets the cache topology level. It acc= epts + CPU topology levels including ``thread``, ``core``, ``module``, + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a speci= al + value ``default``. If ``default`` is set, then the cache topology = will + follow the architecture's default cache topology model. If another + topology level is set, the cache will be shared at corresponding C= PU + topology level. For example, ``topology=3Dcore`` makes the cache s= hared + by all threads within a core. + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dcore,s= mp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dcore ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, --=20 2.34.1