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Thu, 10 Oct 2024 14:52:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Rikalo , Aurelien Jarno Subject: [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Date: Thu, 10 Oct 2024 18:50:13 -0300 Message-ID: <20241010215015.44326-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010215015.44326-1-philmd@linaro.org> References: <20241010215015.44326-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728597156373116600 Have the CPS expose a 'cpu-big-endian' property so it can set it to the vCPUs it creates. Note, since the number of vCPUs created is dynamic, we can not use QOM aliases. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson --- include/hw/mips/cps.h | 1 + hw/mips/cps.c | 4 ++++ hw/mips/malta.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 04d636246ab..05ef9f76b74 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -38,6 +38,7 @@ struct MIPSCPSState { uint32_t num_vp; uint32_t num_irq; char *cpu_type; + bool cpu_is_bigendian; =20 MemoryRegion container; MIPSGCRState gcr; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 07b73b0a1f4..13046628cd2 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -77,6 +77,9 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) MIPSCPU *cpu =3D MIPS_CPU(object_new(s->cpu_type)); CPUMIPSState *env =3D &cpu->env; =20 + object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bige= ndian, + &error_abort); + /* All VPs are halted on reset. Leave powering up to CPC. */ object_property_set_bool(OBJECT(cpu), "start-powered-off", true, &error_abort); @@ -167,6 +170,7 @@ static Property mips_cps_properties[] =3D { DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), + DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, fal= se), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 1df00c4bf99..964d3592da7 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1054,6 +1054,8 @@ static void create_cps(MachineState *ms, MaltaState *= s, object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, &error_fatal); + object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian", + TARGET_BIG_ENDIAN, &error_abort); object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); --=20 2.45.2