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[201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:04:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587049; x=1729191849; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PUee2NQrvjsGKbH1dpkkylkOYkQbKE2imhmGuff3t2o=; b=OEf2wg2VBusX/nstOBrYk19Zh9FCv8ZNsXn3w1PA01iCQPmTDc3P+LObB/YhtOW4vu jXymc/EwUACslIiLjCnH3z4wjiR6+0gCGl5EiKbjV9TcZATkoCuP3dqMIjDDBLRAZewr sALDjGl5kp94WjqPZH2BnTzUxS4ColU41wO0WZH82La8k1mLVfQSKcqSLg+qJXnlpAFQ eu9JlsV8aPvV5Bb2ap0Qbu0im6cH1t7+gyzVyH5n6UcYwBK3bvMjKoKIPrFR6ogVolM7 ImDh/C5XazUf5nDiqv0Zw4tdTVOi6GGf52mGNrX4y+/8T1TPkgCkHJPEQuR5n2PqoqTX 7fOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587049; x=1729191849; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PUee2NQrvjsGKbH1dpkkylkOYkQbKE2imhmGuff3t2o=; b=AZdgYk+b+PF4OAtPMQF3Z/3Zc0d+fLzI5IT3gQQaZ7glmZRN3lQmx8+DlgFE3KtdnK sByN50w0GwSfuL1g3UQQPz7WR7gfyRuoBEzwrVMZtRZpgQ1TEZ9+PQe0fYCBZxOVH1/C FhKkhpojfdlCDF8hwIuNWliwPij3KC6STnxl7gjZHlLtRVTHnjixA54i2Wv8CSTxRyxt myBlB0Cs++GgTzcWT0ayThHYVR9LTowhBeA+mr4ZBDVbCe5sSrSJ2sUnpXzIS92ml3tl 57qlfThwnPY1gDvaO3LKn5CJsR56hTPKbPXwLbT6kUQ4f/BeOpZ5o+9SGv96KINIcqTY Mx0g== X-Gm-Message-State: AOJu0YynswaPXflpwKnmXMnjJLgEZbYPg3IgqY85lK7wo6Ekoc9bPxTx 1xLIkAKdbm6vX2SrcDD6d7jfEYLT/3szL08N9rzdZ4iZeaHAwg9HdbOvfi9T6srXUXsUrlL0ijU n X-Google-Smtp-Source: AGHT+IF4Xei35zUQ8hRY/TdCvyvNusWYc9A56aQqDUKJ0WFf+/iEbc04bycPwJj13+5mzuCCiG2+/Q== X-Received: by 2002:a05:6a00:2d9b:b0:714:1ca1:7134 with SMTP id d2e1a72fcca58-71e37f4eefdmr74136b3a.18.1728587048971; Thu, 10 Oct 2024 12:04:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 8/8] docs: update riscv/virt.rst with kernel-irqchip=split support Date: Thu, 10 Oct 2024 16:03:37 -0300 Message-ID: <20241010190337.376987-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1728587155413116600 Content-Type: text/plain; charset="utf-8" Also add a new page, docs/specs/riscv-aia.rst, where we're documenting the state of AIA support in QEMU w.r.t the controllers being emulated or not depending on the AIA and accelerator settings. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/index.rst | 1 + docs/specs/riscv-aia.rst | 83 ++++++++++++++++++++++++++++++++++++++ docs/system/riscv/virt.rst | 7 ++++ 3 files changed, 91 insertions(+) create mode 100644 docs/specs/riscv-aia.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 6495ed5ed9..9a7d61161f 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -36,3 +36,4 @@ guest hardware that is specific to QEMU. vmgenid rapl-msr rocker + riscv-aia diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst new file mode 100644 index 0000000000..8097e2f897 --- /dev/null +++ b/docs/specs/riscv-aia.rst @@ -0,0 +1,83 @@ +.. _riscv-aia: + +RISC-V AIA support for RISC-V machines +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +AIA (Advanced Interrupt Architecture) support is implemented in the ``virt= `` +RISC-V machine for TCG and KVM accelerators. + +The support consists of two main modes: + +- "aia=3Daplic": adds one or more APLIC (Advanced Platform Level Interrupt= Controller) + devices +- "aia=3Daplic-imsic": adds one or more APLIC device and an IMSIC (Incomin= g MSI + Controller) device for each CPU + +From an user standpoint, these modes will behave the same regardless of th= e accelerator +used. From a developer standpoint the accelerator settings will change wh= at it being +emulated in userspace versus what is being emulated by an in-kernel irqchi= p. + +When running TCG, all controllers are emulated in userspace, including mac= hine mode +(m-mode) APLIC and IMSIC (when applicable). + +When running KVM: + +- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation re= gardless of + the AIA mode chosen +- with "aia=3Daplic", s-mode APLIC will be emulated by userspace +- with "aia=3Daplic-imsic" there are two possibilities. If no additional = KVM option + is provided there will be no APLIC or IMSIC emulation in userspace, and = the virtual + machine will use the provided in-kernel APLIC and IMSIC controllers. If= the user + chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip= =3Dsplit", + s-mode APLIC will be emulated while using the s-mode IMSIC from the irqc= hip + +The following table summarizes how the AIA and accelerator options defines= what +we will emulate in userspace: + + +.. list-table:: How AIA and accel options changes controller emulation + :widths: 25 25 25 25 25 25 25 + :header-rows: 1 + + * - Accel + - Accel props + - AIA type + - APLIC m-mode + - IMSIC m-mode + - APLIC s-mode + - IMSIC s-mode + * - tcg + - --- + - aplic + - emul + - n/a + - emul + - n/a + * - tcg + - --- + - aplic-imsic + - emul + - emul + - emul + - emul + * - kvm + - --- + - aplic + - n/a + - n/a + - emul + - n/a + * - kvm + - none + - aplic-imsic + - n/a + - n/a + - in-kernel + - in-kernel + * - kvm + - irqchip=3Dsplit + - aplic-imsic + - n/a + - n/a + - emul + - in-kernel diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 9a06f95a34..8cbedf73ef 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -110,6 +110,13 @@ The following machine-specific options are supported: MSIs. When not specified, this option is assumed to be "none" which sele= cts SiFive PLIC to handle wired interrupts. =20 + This option also interacts with '-accel kvm'. When using "aia=3Daplic-i= msic" + with KVM, it is possible to set the use of the kernel irqchip in split m= ode + by using "-accel kvm,kernel-irqchip=3Dsplit". In this case the ``virt``= machine + will emulate the APLIC controller instead of using the APLIC controller = from + the irqchip. See :ref:`riscv-aia` for more details on all available AIA + modes. + - aia-guests=3Dnnn =20 The number of per-HART VS-level AIA IMSIC pages to be emulated for a gue= st --=20 2.45.2