From nobody Sun Nov 24 01:44:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1728543263306188.25396194139466; Wed, 9 Oct 2024 23:54:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syn32-00019M-Nm; Thu, 10 Oct 2024 02:53:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syn30-00017i-2M for qemu-devel@nongnu.org; Thu, 10 Oct 2024 02:53:18 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syn2w-00040a-5Z for qemu-devel@nongnu.org; Thu, 10 Oct 2024 02:53:17 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxqrHUeQdn7+IRAA--.25543S3; Thu, 10 Oct 2024 14:53:08 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMBxXuTTeQdnBiAiAA--.41709S3; Thu, 10 Oct 2024 14:53:07 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, maobibo@loongson.cn, philmd@linaro.org Subject: [PATCH v2 1/5] target/loongarch: Add a new cpu_type la664 Date: Thu, 10 Oct 2024 14:35:32 +0800 Message-Id: <20241010063536.2276871-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20241010063536.2276871-1-gaosong@loongson.cn> References: <20241010063536.2276871-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxXuTTeQdnBiAiAA--.41709S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1728543265471116600 Content-Type: text/plain; charset="utf-8" Add a new LoongArch cpu type la664. The la664 has many new features, such as new atomic instructions, hardware page table walk, etc. We will implement them later. Signed-off-by: Song Gao --- target/loongarch/cpu.c | 50 +++++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 7212fb5f8f..d55b4110a9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -374,20 +374,11 @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool= ifetch) return MMU_DA_IDX; } =20 -static void loongarch_la464_initfn(Object *obj) +static void loongarch_common_initfn(CPULoongArchState *env, Object *obj) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - CPULoongArchState *env =3D &cpu->env; - int i; - - for (i =3D 0; i < 21; i++) { - env->cpucfg[i] =3D 0x0; - } - - cpu->dtb_compatible =3D "loongarch,Loongson-3A5000"; - env->cpucfg[0] =3D 0x14c010; /* PRID */ + uint32_t data; =20 - uint32_t data =3D 0; + data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 2); data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); @@ -472,14 +463,42 @@ static void loongarch_la464_initfn(Object *obj) loongarch_cpu_post_init(obj); } =20 -static void loongarch_la132_initfn(Object *obj) +static void loongarch_la664_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; =20 - int i; + for (unsigned i =3D 0; i < ARRAY_SIZE(env->cpucfg); i++) { + env->cpucfg[i] =3D 0x0; + } + + cpu->dtb_compatible =3D "loongarch,Loongson-3A6000"; + env->cpucfg[0] =3D 0x14d000; /* PRID */ + + loongarch_common_initfn(env, obj); +} + +static void loongarch_la464_initfn(Object *obj) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + CPULoongArchState *env =3D &cpu->env; + + for (unsigned i =3D 0; i < ARRAY_SIZE(env->cpucfg); i++) { + env->cpucfg[i] =3D 0x0; + } + + cpu->dtb_compatible =3D "loongarch,Loongson-3A5000"; + env->cpucfg[0] =3D 0x14c010; /* PRID */ + + loongarch_common_initfn(env, obj); +} + +static void loongarch_la132_initfn(Object *obj) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + CPULoongArchState *env =3D &cpu->env; =20 - for (i =3D 0; i < 21; i++) { + for (unsigned i =3D 0; i < ARRAY_SIZE(env->cpucfg); i++) { env->cpucfg[i] =3D 0x0; } =20 @@ -872,6 +891,7 @@ static const TypeInfo loongarch_cpu_type_infos[] =3D { .abstract =3D true, .class_init =3D loongarch64_cpu_class_init, }, + DEFINE_LOONGARCH_CPU_TYPE(64, "la664", loongarch_la664_initfn), DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), --=20 2.33.0