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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0d65278sm7881094b3a.160.2024.10.09.08.09.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 08:09:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728486541; x=1729091341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=24CMkQMrWOo8hDSF+GETpHYU0Rfi9fKfFw2PUYnta2A=; b=eVIoe5ckJBAkJ5mvp5U1hZZ51/r0B3EReei2bzEP5PvCZwrC3X+vDXkN+VfaN3Mb+A aSduhAfJEnwoTM1rgihVRgKBJ8nyZJ+osiCSZ9M/j69HHD3kqFD2U3OnOHqlytD4d9Xx 3n46waff8z1QE6aF+5W7dCKiaUq//Lgmni/oOxXb8ZypqU67iE395gMWNqXiLo5gAYoU J9VbhKE0DFKA8+BnWojQ3WkNkPWsQfurPYddvBLAX1M5CFHsZNoQjQwCz3rL5U/LD6yB A15THJ004xiHwLlnBEORa4TKe0hISOgJKgHvHnqNxaWA8h3VH9XfEtfDEYYJLouWxGs0 x1lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728486541; x=1729091341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=24CMkQMrWOo8hDSF+GETpHYU0Rfi9fKfFw2PUYnta2A=; b=EltBpBd3b+5i+1YjtbPDAg7CScOiHNW8vUi/iuldtp0WzLNQIMoR4ytsebEGrsbnu2 vev6e2ojST9yY6RYVZdCS3vDwOA5UWNS3EUAYDlXau2ViaruJs2YLs2HyBATytX8orHh BK/Gpo6ViF+KXyalP6n6PLRGxE5S9/7N1UqLMlBQljYY3ojUA4heV1rtA4EoNZi9Qx+j Gk2Viyu/KnhFebp7dJgvZzRbXn+ikT/elwynz4BWDCOw8fchgh5ZKco1Pa0evpemULtd aFAXPf9ExWMNxp8x2Q1zmuEDJ9PwBXThmvBy/U7C9hdaNBpG7S61KjwCaNcA7CSbTVL/ d9xQ== X-Gm-Message-State: AOJu0Yzpbd1+rLEd9zAqtLqbamH2We9AnQ2J/2wu8uOBGXW94jH3mcMe Sx6+f25NVwi/0dV/BFxGarP1RFDJXS/dlz679/8ZVZ6vyZHB5GYNarQBTTypxOvk2p9wB6StYBA S X-Google-Smtp-Source: AGHT+IFW6X21xATWnjs19uf+VAQ6MGgZYTZoVKA/0G6LpR232u94VmzYtKkSIJheRagPblZypXdAZQ== X-Received: by 2002:a05:6a00:1a8b:b0:71e:48b:6422 with SMTP id d2e1a72fcca58-71e1db64785mr4342135b3a.2.1728486540635; Wed, 09 Oct 2024 08:09:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/23] accel/tcg: Split out tlbfast_flush_range_locked Date: Wed, 9 Oct 2024 08:08:36 -0700 Message-ID: <20241009150855.804605-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241009150855.804605-1-richard.henderson@linaro.org> References: <20241009150855.804605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1728486584923116600 Content-Type: text/plain; charset="utf-8" While this may at present be overly complicated for use by single page flushes, do so with the expectation that this will eventually allow simplification of large pages. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 61 +++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e37af24525..6773874f2d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -520,10 +520,37 @@ static inline void tlb_flush_vtlb_page_locked(CPUStat= e *cpu, int mmu_idx, tlb_flush_vtlb_page_mask_locked(cpu, mmu_idx, page, -1); } =20 +static void tlbfast_flush_range_locked(CPUTLBDesc *desc, CPUTLBDescFast *f= ast, + vaddr addr, vaddr len, vaddr mask) +{ + /* + * If @mask is smaller than the tlb size, there may be multiple entries + * within the TLB; for now, just flush the entire TLB. + * Otherwise all addresses that match under @mask hit the same TLB ent= ry. + * + * If @len is larger than the tlb size, then it will take longer to + * test all of the entries in the TLB than it will to flush it all. + */ + if (mask < fast->mask || len > fast->mask) { + tlbfast_flush_locked(desc, fast); + return; + } + + for (vaddr i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { + vaddr page =3D addr + i; + CPUTLBEntry *entry =3D tlbfast_entry(fast, page); + + if (tlb_flush_entry_mask_locked(entry, page, mask)) { + desc->n_used_entries--; + } + } +} + static void tlb_flush_page_locked(CPUState *cpu, int midx, vaddr page) { - vaddr lp_addr =3D cpu->neg.tlb.d[midx].large_page_addr; - vaddr lp_mask =3D cpu->neg.tlb.d[midx].large_page_mask; + CPUTLBDesc *desc =3D &cpu->neg.tlb.d[midx]; + vaddr lp_addr =3D desc->large_page_addr; + vaddr lp_mask =3D desc->large_page_mask; =20 /* Check if we need to flush due to large pages. */ if ((page & lp_mask) =3D=3D lp_addr) { @@ -532,9 +559,8 @@ static void tlb_flush_page_locked(CPUState *cpu, int mi= dx, vaddr page) midx, lp_addr, lp_mask); tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); } else { - if (tlb_flush_entry_locked(tlb_entry(cpu, midx, page), page)) { - tlb_n_used_entries_dec(cpu, midx); - } + tlbfast_flush_range_locked(desc, &cpu->neg.tlb.f[midx], + page, TARGET_PAGE_SIZE, -1); tlb_flush_vtlb_page_locked(cpu, midx, page); } } @@ -689,24 +715,6 @@ static void tlb_flush_range_locked(CPUState *cpu, int = midx, CPUTLBDescFast *f =3D &cpu->neg.tlb.f[midx]; vaddr mask =3D MAKE_64BIT_MASK(0, bits); =20 - /* - * If @bits is smaller than the tlb size, there may be multiple entries - * within the TLB; otherwise all addresses that match under @mask hit - * the same TLB entry. - * TODO: Perhaps allow bits to be a few bits less than the size. - * For now, just flush the entire TLB. - * - * If @len is larger than the tlb size, then it will take longer to - * test all of the entries in the TLB than it will to flush it all. - */ - if (mask < f->mask || len > f->mask) { - tlb_debug("forcing full flush midx %d (" - "%016" VADDR_PRIx "/%016" VADDR_PRIx "+%016" VADDR_PRIx = ")\n", - midx, addr, mask, len); - tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); - return; - } - /* * Check if we need to flush due to large pages. * Because large_page_mask contains all 1's from the msb, @@ -720,13 +728,10 @@ static void tlb_flush_range_locked(CPUState *cpu, int= midx, return; } =20 + tlbfast_flush_range_locked(d, f, addr, len, mask); + for (vaddr i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { vaddr page =3D addr + i; - CPUTLBEntry *entry =3D tlb_entry(cpu, midx, page); - - if (tlb_flush_entry_mask_locked(entry, page, mask)) { - tlb_n_used_entries_dec(cpu, midx); - } tlb_flush_vtlb_page_mask_locked(cpu, midx, page, mask); } } --=20 2.43.0